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Messages from 84525

Article: 84525
Subject: Memec Virtex-4 LX25 LC
From: Shakith <cybershakith@hotmail.com>
Date: Fri, 20 May 2005 01:40:27 -0700
Links: << >>  << T >>  << A >>
Hello, I am working on the Virtex-4 LX25 LC for a project.

Whenever I create edk project using Base Design builder for this and generate the bitstream I get the following error

Timing constraints have not been met.

NET "fpga_0_Ethernet_MAC_PHY_rx_clk" PERIOD = 40 nS HIGH 14 nS

NET "fpga_0_Ethernet_MAC_PHY_tx_clk" PERIOD = 40 nS HIGH 14 nS

TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "RXCLK_GRP_Ethernet_ MAC" 6 nS

I have reduced the system frequency to 75Mhz and reduced the above the 3rd constraint to 6.5ns to get generate the bitstream using timing packing with high effort level for map and par.

But when I add extra user IP, the timing constraints cannot be met again.

I would appreciate any help in solving this problem.

My setup is ISE and EDK 6.3i with SP2.

Best Regards, Shakith

Article: 84526
Subject: Re: Xilinx V2Pro DCM config and settling time questions
From: "Ken" <no@spam.com>
Date: Fri, 20 May 2005 10:46:09 +0200
Links: << >>  << T >>  << A >>
Hi Peter,

> Ken, I suggest you use Frequency Synthesis mode (where the 24 MHz min
> does not apply to the input, but rather to the output), and you
> multiply by 4 and divide by 1. That uses only one DCM, and gives you 40
> MHz, which you can easily divide by 2 in a flip-flop.

Excellent.

I take I cannot connect up CLKFB since both CLK0 and CLK2X will be < 24MHz?


> When you say "the input frequency will be held.." I assume that means
> you have a constant fequency for that time, then change to another
> frequency...

Correct.


> DCMs do not like interruptions in the input signal.
> Adjusting to the slightly higher/lower frequency takes a few clock
> ticks.

Thats fine.  There is 800us available to adjust and a few periods of 0.1us 
should be fine! :-)

Many thanks,

Ken




Article: 84527
Subject: Re: Detaching the schematic viewer under ISE Webpack
From: "Geogle" <georgevarughese@indiatimes.com>
Date: 20 May 2005 01:52:49 -0700
Links: << >>  << T >>  << A >>

W A wrote:
> Try the ">>" button in the upper right corner
>

Is it only on MS Windows ? I cant see them under X(linux).

Thanks,
George

> "Geogle" <georgevarughese@indiatimes.com> wrote in message
> news:1116392539.922971.178880@g49g2000cwa.googlegroups.com...
> > Just wondering if it is possible to detach the schematic
> > viewer from the main ise window. (in 7.1i or so.)
> > Also is it possible to configure a third party tool for
> > viewing the schematic ?
> >
> > I know that it is possible to configure the text editor.
> > But is it possible for the schematic viewer too ?
> >
> > Thanks,
> > George
> >


Article: 84528
Subject: Re: Bullshit Achieves Literary Status
From: "Neo" <zingafriend@yahoo.com>
Date: 20 May 2005 01:55:39 -0700
Links: << >>  << T >>  << A >>
Hey, cool it off guys. MBA schooling makes the top-nought executives do
that. Lets worry about actual designs and how each of you can help
others with their problems in using your devices.


Article: 84529
Subject: Re: A Short Pulse Catcher
From: "Neo" <zingafriend@yahoo.com>
Date: 20 May 2005 02:14:28 -0700
Links: << >>  << T >>  << A >>
warning is not a problem its just reminding you about comb feedback. It
is not advised to model latches as comb logic in fpga as they have a
seperate latch primitive for that. but you will have difficulty
simulating it.


Article: 84530
Subject: Re: Bullshit Achieves Literary Status
From: "Jon Beniston" <jon@beniston.com>
Date: 20 May 2005 02:17:23 -0700
Links: << >>  << T >>  << A >>
> Stratix-2 having lower power consumption than Virtex-4.

Instead of worrying about the competition, why can't you spend some
time specifying you own parts? How long has the Spartan 3 supposed to
have been out? (2 years?) Why are there still blanks in the datasheet
(i.e. page 5, max quiescent supply current)? Why is the datasheet still
listed as being "Advance Product Spefication"?

Cheers,
Jon


Article: 84531
Subject: Re: Memec Virtex-4 LX25 LC
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Fri, 20 May 2005 10:32:54 +0100
Links: << >>  << T >>  << A >>
Adding  the IP will change the place and route implementation. Depending on 
what you are doing you may be adding or generating logic paths with lots of 
level of LUTs etc which are hard to meet timing on.

If you run Timing Analyser it will tell you the paths that fail and you can 
work out where your problems are and possibly fix them by adding pipelining 
of the logic or simply changing the logic you may be able to meeting.

Another approach is to use multiple place and route which ISE supports. 
Takes time but may find a timing solution without you delving into the 
logic.

Another thing to consider is floorplanning your design which may assist the 
p&r tools to make a better, faster, solution.

One general comment is that the first 2 constraints appear to be clocks with 
a poor mark/space ratio. Are your clocks that bad? If you have logic that 
uses both edges of the clock then you may be making the p&r task much more 
difficult as it will be trying to make timing on effectively 71MHz rather 
than the 50 MHz of a "perfect" clock.


John Adair
Enterpoint Ltd. - Home of MINI-CAN. Low Cost PCI Development Board.
http://www.enterpoint.co.uk


"Shakith" <cybershakith@hotmail.com> wrote in message 
news:ee8e6a5.-1@webx.sUN8CHnE...
> Hello, I am working on the Virtex-4 LX25 LC for a project.
>
> Whenever I create edk project using Base Design builder for this and 
> generate the bitstream I get the following error
>
> Timing constraints have not been met.
>
> NET "fpga_0_Ethernet_MAC_PHY_rx_clk" PERIOD = 40 nS HIGH 14 nS
>
> NET "fpga_0_Ethernet_MAC_PHY_tx_clk" PERIOD = 40 nS HIGH 14 nS
>
> TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP 
> "RXCLK_GRP_Ethernet_ MAC" 6 nS
>
> I have reduced the system frequency to 75Mhz and reduced the above the 3rd 
> constraint to 6.5ns to get generate the bitstream using timing packing 
> with high effort level for map and par.
>
> But when I add extra user IP, the timing constraints cannot be met again.
>
> I would appreciate any help in solving this problem.
>
> My setup is ISE and EDK 6.3i with SP2.
>
> Best Regards, Shakith 



Article: 84532
Subject: Re: About back annotated simulations...
From: Ray Andraka <ray@andraka.com>
Date: Fri, 20 May 2005 05:35:00 -0400
Links: << >>  << T >>  << A >>

Right you are Bob.  Functional simulation and timing analysis generally 
finishes faster and provides a more comprehensive result than depending 
on timing sim.  Timing sim is next to useless for actual timing analysis 
because it only checks the particular timing scenario indicated by the 
gate delays used.  Chances are the gate delays in simulation will only 
have a loose correlation to what the actual delays are in the actual 
device.  While timing simulation can get you the same functional 
verification with a little bit of added comfort that any grossly too 
long delay paths are not kiling the design (at least for the vectors 
your test uses), it doesn't provide as complete a timing analysis as a 
good static analysis does, and it runs slower.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 84533
Subject: Re: Bullshit Achieves Literary Status
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 20 May 2005 21:45:05 +1200
Links: << >>  << T >>  << A >>
did you know that the year Intel made the 8031 obsolete.. its latest data
sheet still said preliminary!

Simon

"Jon Beniston" <jon@beniston.com> wrote in message
news:1116580643.528544.3840@z14g2000cwz.googlegroups.com...
> > Stratix-2 having lower power consumption than Virtex-4.
>
> Instead of worrying about the competition, why can't you spend some
> time specifying you own parts? How long has the Spartan 3 supposed to
> have been out? (2 years?) Why are there still blanks in the datasheet
> (i.e. page 5, max quiescent supply current)? Why is the datasheet still
> listed as being "Advance Product Spefication"?
>
> Cheers,
> Jon
>



Article: 84534
Subject: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
From: "sankalp.singhal" <sankalp.singhal@rediffmail.com>
Date: 20 May 2005 02:48:49 -0700
Links: << >>  << T >>  << A >>
 I have checked "input tri-state" option in the compiler setting.
dwesterg@gmail.com wrote:
> Make sure that unused IO are tri-stated in your fpga design.
> 
> --Dalon


Article: 84535
Subject: ALTERA EPXA1 SDRAM BUG
From: "Ralf" <panse@kip.uni-heidelberg.de>
Date: Fri, 20 May 2005 12:57:02 +0200
Links: << >>  << T >>  << A >>
Hi all,

have everyone experience about a second SDRAM with the Altera
FPGA+HARCORE-CPU EPXA1?
Its is unpossible for me to access the second SDRAM.
I used a modified "Hello World" program from ALTERA, Linux running on the
hardcore CPU and ARMBOOT to address the second SDRAM (Chip-Select SD-CS1)
device. But I always get the content of the first SDRAM (Chip-Select
SD-CS0). Both SDRAM devices shared the address and data signals, but every
device get his own chip_select signal.

I would appreciate any help in solving this problem.

Regards Ralf



Article: 84536
Subject: Re: FFT with FPGA
From: Luc <lb.edc@pandora.be>
Date: Fri, 20 May 2005 13:09:24 +0200
Links: << >>  << T >>  << A >>
Mike,

Xilinx, Altera and Lattice have devices that can do the job. You
didn't mention the clock frequency however, and this will limit the
number of devices to pick from.
Some reference points:
Xilinx's Spartan3 has multipliers(18x18 only), but no Add/Sub in the
DSP block, Virtex4 has a full featured DSP engine (see datasheet)

Altera's Cyclone has no DSP block at all, Cyclone2 has multipliers
(18x18 and 9x9), Stratix and Stratix2 also have a full featured DSP
block (9x9, 18x18 and 36x36) with Add/sub/Accum.

Lattice's ECP has a full featured DSP block (9x9, 18x18 and 36x36),
Add, Sum and Accumulate, Input & Output and Intermediate registers.
They don't have a high-end FPGA fabric comparable with Stratix and
Virtex4. The DSP performance of the low cost ECP is comparable with
Stratix. So maybe this device can be a good starting point for a
benchmark study.

All of the 3 vendors have IP to support the multiplier blocks
(including FFT128). But as I mentioned above, performance and price
will depend on the family of devices you will chose. If you consult
the website, you will find at least a datasheet which will answer your
questions.

Regards,

Luc

On 19 May 2005 22:12:37 -0700, "Mike" <mail2mz@gmail.com> wrote:

>Hi All,
>
>I am trying to speed up the FFT on my embedded system. Here are some
>details questions on my project.
>
>1, For different FPGA venders, what are the Pros and Cons of Xilinx?
>2. How long would it take for a 128 pt complex FFT?
>3, How does my CPU connect to the FPGA?
>4. How many gate or memory do I need, which Xilinx chip should I pick?
>
>Thanks for your help,
>
>Mike


Article: 84537
Subject: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
From: "Jon Beniston" <jon@beniston.com>
Date: 20 May 2005 06:01:58 -0700
Links: << >>  << T >>  << A >>
Check out Synplicity's Synplify Proto.

Cheers,
Jon


Article: 84538
Subject: Re: For accessing my SDRAM,what should i do?
From: ARRON <mlpei279@gmail.com>
Date: Fri, 20 May 2005 06:28:33 -0700
Links: << >>  << T >>  << A >>
I have tested my project,but i find writing the SDRAM will success if the system's cpu is ppc,when the cpu is Microblaze,that i write to the SDRAM must wait for initializing the SDRAM and will not success, what is the matter? which parameter of SDRAM controller must be changed? thanks for your help!!!

Article: 84539
Subject: How to download uClinux on Virtex4 Board.
From: "ivan" <ivan.fed@gmail.com>
Date: 20 May 2005 07:52:39 -0700
Links: << >>  << T >>  << A >>
Hi All,

    Have anybody tried downloading uClinux on Virtex4 board.We have got
the bsp sources from
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html#bsp_package

and the hardware from
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html#ml401_uclinux_66mhz

We have generated the bit stream using EDK6.3.02.But don't know how to
compile the kernel(uclinux) and download it.It would be very helpful if
anyone could explain the steps to be followed to bring up the shell of
uClinux.

Thanks & Regards,
Ivan


Article: 84540
Subject: Re: Universal logic modules vs NAND-like modules
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 20 May 2005 08:06:57 -0700
Links: << >>  << T >>  << A >>
Candida Ferreira wrote:
> "rickman" wrote:
>
> > I don't follow.  Multiplexers are as complete as any logic element.
> > I'm not sure what you mean by a 3-multiplexer, but I will assume
you
> > mean a 2 input mux with a single control input.  You can get a NOT
> > function by putting a 1 on the I0 input and a 0 on the I1 input and
> > your signal on the sel input.
>
> That's true and does not contradict the definition of a ULM, but you
need
> the 1 and the 0 to create a NOT. Without them you cannot create a NOT
with
> the 3-multiplexer. But there are other functions, such as the NAND
and the
> NOR functions that, by themselves, can create any other function,
without
> needing the NOT, the ZERO and the ONE. These are the ULMs I want to
> distinguish from the more ordinary ones.

Why?


Article: 84541
Subject: Re: A Short Pulse Catcher
From: "Johnschool" <tanceqi@yahoo.com>
Date: 20 May 2005 08:07:58 -0700
Links: << >>  << T >>  << A >>
Hi Neo,
Thank you for your reply!
Do you know if there is other methods to realize short pulse catcher,
so that I can remove the latch and the warning (you are right, the
warning doesn't affect the software work, but I still want to remove
it. :-)).


Article: 84542
Subject: Re: Universal logic modules vs NAND-like modules
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 20 May 2005 08:19:13 -0700
Links: << >>  << T >>  << A >>
Gabor wrote:
> Mike Treseler wrote:
> > Candida Ferreira wrote:
> >
> > > NAND and NOR functions by themselves can be used to describe any
> other
> > > function, including NOT, ZERO and ONE.
> >
> > True. NCR once produced a computer using only NAND gates.
> >
>
> It's a good bet that they didn't use any NAND gates to generate
> ones or zeroes!  This sounds like a mathematician kind of question
> rather than engineering...

Someone needs to tell me how to create a one or zero using only NAND
gates.

The only thing I can think of would be to use two gates in a loop.
This will have two stable states, 1-0 and 0-1.  The two free inputs
will set the gates to the two states when taken low since any input at
a zero will make the output of the gate a one.  One of these free
inputs is tied to its twin input to make an inverter.  The other is
tied to its own gate output.  If the gate output is a one, it causes no
action on the gate and is stable.  If a zero, it will cause itself to
become a one and be then be stable.

But this will only generate a stable output after some period of time.
Not exactly my idea of a useful circuit.


Article: 84543
Subject: Re: A Short Pulse Catcher
From: Jonathan Bromley <jonathan.bromley@doulos.com>
Date: Fri, 20 May 2005 16:28:32 +0100
Links: << >>  << T >>  << A >>
On 20 May 2005 08:07:58 -0700, "Johnschool" <tanceqi@yahoo.com> wrote:

>Hi Neo,
>Thank you for your reply!
>Do you know if there is other methods to realize short pulse catcher,
>so that I can remove the latch and the warning (you are right, the
>warning doesn't affect the software work, but I still want to remove
>it. :-)).

The Flancter circuit will do it nicely, and IMHO is much more
suitable for typical FPGA implementation than your latch thing.

Flancter is an unusual word; Google is your friend :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 84544
Subject: Re: Universal logic modules vs NAND-like modules
From: "Gabor" <gabor@alacron.com>
Date: 20 May 2005 08:32:21 -0700
Links: << >>  << T >>  << A >>

rickman wrote:
> Gabor wrote:
> > Mike Treseler wrote:
> > > Candida Ferreira wrote:
> > >
> > > > NAND and NOR functions by themselves can be used to describe
any
> > other
> > > > function, including NOT, ZERO and ONE.
> > >
> > > True. NCR once produced a computer using only NAND gates.
> > >
> >
> > It's a good bet that they didn't use any NAND gates to generate
> > ones or zeroes!  This sounds like a mathematician kind of question
> > rather than engineering...
>
> Someone needs to tell me how to create a one or zero using only NAND
> gates.
>
> The only thing I can think of would be to use two gates in a loop.
> This will have two stable states, 1-0 and 0-1.  The two free inputs
> will set the gates to the two states when taken low since any input
at
> a zero will make the output of the gate a one.  One of these free
> inputs is tied to its twin input to make an inverter.  The other is
> tied to its own gate output.  If the gate output is a one, it causes
no
> action on the gate and is stable.  If a zero, it will cause itself to
> become a one and be then be stable.
>
> But this will only generate a stable output after some period of
time.
> Not exactly my idea of a useful circuit.


This is why I said the problem was mathematical and not engineering.
A Boolian NAND gate performs a truth function on ones and zeroes only.
This is not the same as a Verilog NAND gate which can take X or Z
as well as 1 or 0 and produce X as well as 0 or 1.

The Boolian NAND also does not imply a time delay.  So given such a
gate with an unknown input "A", you can produce the inversion of the
unknown input "A_BAR" (A NAND A), and then create 1 by NANDing "A"
with "A_BAR" (A NAND A_BAR).
Zero requires an additional inverter (1 NAND 1).

In the real world this would produce glitches whenever "A" changed
state.


Article: 84545
Subject: Re: Coloring by clock?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 20 May 2005 09:09:57 -0700
Links: << >>  << T >>  << A >>
Gabor wrote:

> The point is to find the "inputs that need it" without
> going crazy in a large design...

The inputs that need it are device
pins driven by logic not synchronous
to the fpga clock.
No need to pore over your code.

         -- Mike Treseler

Article: 84546
Subject: Re: Coloring by clock?
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 20 May 2005 09:44:17 -0700
Links: << >>  << T >>  << A >>
"Thomas Stanka" <usenet_10@stanka-web.de> wrote in message
news:ef424d2c.0505192309.1cfbe1b4@posting.google.com...
>
> But is also written what to do if timing constraint meets power
> constraints?
>
> I like to have each design synchronous. And actually doing a
> _synchronous_ ASIC using several different clocks runing on various
> frequencies, but this is nearly  impossible if it comes to do a
> prototype with an fpga and would be complete impossible if the design
> would need to hit the edge of technology, as often seen when doing
> high speed data processing.
>
> bye Thomas
>
Hi Thomas,
Ah, but this isn't comp.arch.asic. Those heretics have their own book! They
need to as they don't get FFs with CE for (kind of) free like we do in
FPGAs.
But, point taken!
Thanks, Syms.



Article: 84547
Subject: Re: Bullshit Achieves Literary Status
From: "Peter Alfke" <peter@xilinx.com>
Date: 20 May 2005 11:09:22 -0700
Links: << >>  << T >>  << A >>
It is time to stop the bickering.
Altera will never admit that Stratix-2 uses more power than Virtex-4,
so this debate could go on forever, boring the audience to death.
Xilinx is confident in the low-power advantage of Virtex-4. That's why
we went to the trouble and expense of building dozens of 1-to-1
evaluation boards. We have demonstrated them publicly, we have shown
them to individual important customers, loaned them to customers, and
even sold them to some customers.
The customers can (and have) put any design they want into the Xilinx
and the Altera parts on these boards. It's all out in the open. And
they can (and did) easily measure and compare power consumption (and
also signal integrity, if they care about that).

Would we have done all this if there were even the slightest doubt that
we would be the winner in this low-power comparison ?
We did put our money where our mouth is. Let the best product win!
Enough said.
Peter Alfke, Xilinx Applications


Article: 84548
Subject: Re: Simulation of rocket IO in virtex 2 pro
From: Duane Clark <dclark@junkmail.com>
Date: Fri, 20 May 2005 18:36:07 GMT
Links: << >>  << T >>  << A >>
Stephen Lohning wrote:
> I am trying to fine some information about simulating the virtex 2 pro 
> rocket io model in model sim for a couple of my students. Does it work 
> like simulating other standard xilnix components, just write down the 
> port map ( VHDL) and  include the unisim library?
> Any help would be appreciated regards

In general, the "Answers Database" at Xilinx is very good for this kind 
of question. Plug rocketio simulation into the search box, and you will 
quickly find that record 14019 answers this ("MGT" being the term used 
for the RocketIO).


Article: 84549
Subject: Re: Bullshit Achieves Literary Status
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 20 May 2005 19:09:09 GMT
Links: << >>  << T >>  << A >>
Hi - 

On 20 May 2005 02:17:23 -0700, "Jon Beniston" <jon@beniston.com>
wrote:

>> Stratix-2 having lower power consumption than Virtex-4.
>
>Instead of worrying about the competition, why can't you spend some
>time specifying you own parts? How long has the Spartan 3 supposed to
>have been out? (2 years?) Why are there still blanks in the datasheet
>(i.e. page 5, max quiescent supply current)? Why is the datasheet still
>listed as being "Advance Product Spefication"?
>
>Cheers,
>Jon

I used to tell new designers that IC data sheets came in three
versions: advanced, preliminary, and end-of-life.

Bob Perlman
Cambrian Design Works



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2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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