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Peter Alfke wrote: > It is time to stop the bickering. > Altera will never admit that Stratix-2 uses more power than Virtex-4, > so this debate could go on forever, boring the audience to death. > Xilinx is confident in the low-power advantage of Virtex-4. That's why > we went to the trouble and expense of building dozens of 1-to-1 > evaluation boards. We have demonstrated them publicly, we have shown > them to individual important customers, loaned them to customers, and > even sold them to some customers. > The customers can (and have) put any design they want into the Xilinx > and the Altera parts on these boards. It's all out in the open. And > they can (and did) easily measure and compare power consumption (and > also signal integrity, if they care about that). > > Would we have done all this if there were even the slightest doubt that > we would be the winner in this low-power comparison ? > We did put our money where our mouth is. Let the best product win! > Enough said. > Peter Alfke, Xilinx Applications Perhaps whoever directed you to all this effort,(which may have impressed a few customers who saw the dozens of PCBs), could reflect on whether all that time and effort would have been BETTER spent on running your own 7.1 release SW, and shipping it with far fewer of the school-boy bugs that have appeared in this newsgroup ? A much wider number of customers would appreciate that, not to mention the massive accumulated cost in lost man-hours ? Instead, they now know that, in some conditions, either company can claim to be #1. -jgArticle: 84551
ARRON wrote: > I have tested my project,but i find writing the SDRAM will success if the system's cpu is ppc,when the cpu is Microblaze,that i write to the SDRAM must wait for initializing the SDRAM and will not success, what is the matter? which parameter of SDRAM controller must be changed? thanks for your help!!! Without looking at your design (and no, I don't want to see it), I'd wager that the interface between the processor and the SDRAM controller has to change when you change the processor. Different timing and different bus transactions, perhaps? -aArticle: 84552
"rickman" <spamgoeshere4@yahoo.com> writes:
> Someone needs to tell me how to create a one or zero using only NAND
> gates.
Not desperately needing it, but anyway:
x nand (x nand x) = x nand not(x) = 1
and then
[x nand (x nand x)] nand [x nand (x nand x)] = 0
MB
--
Michel BILLAUD billaud@labri.fr
LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792
351, cours de la Libération http://www.labri.fr/~billaud
33405 Talence (FRANCE)
Article: 84553"Marco" <marcotoschi_no_spam@email.it> writes: > Does it function with every distribution of Linux? No. It is supported on Red Hat Enterprise Linux 3. You *might* be able to get it working on another distribution, but Xilinx won't help you with it. I suspect that it would run on CentOS 3.x without too much hassle, because that's a clone of RHEL3. I've been able to use ISE BaseX 7.1i on Fedora Core 3 with only some minor annoyances. > There is a way to try the 64 bit version or I need to recompile everything > by myself? Good luck recompiling ISE without the source code. EricArticle: 84554
"Gabor" <gabor@alacron.com> writes: > The Boolian NAND also does not imply a time delay. So given such a > gate with an unknown input "A", you can produce the inversion of the > unknown input "A_BAR" (A NAND A), and then create 1 by NANDing "A" > with "A_BAR" (A NAND A_BAR). > Zero requires an additional inverter (1 NAND 1). [nand] > > In the real world this would produce glitches whenever "A" changed > state. In the real world, who needs to get 0 and 1 from whatever gate anyway ? BTW, this reminds me of a funny paper on how to build a triple not circuit using only 2 not gates (and a number of and- and or- gates). MB > -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 84555
"rickman" wrote:
> Candida Ferreira wrote:
> > "rickman" wrote:
> >
> > > I don't follow. Multiplexers are as complete as any logic element.
> > > I'm not sure what you mean by a 3-multiplexer, but I will assume
> you
> > > mean a 2 input mux with a single control input. You can get a NOT
> > > function by putting a 1 on the I0 input and a 0 on the I1 input and
> > > your signal on the sel input.
> >
> > That's true and does not contradict the definition of a ULM, but you
> need
> > the 1 and the 0 to create a NOT. Without them you cannot create a NOT
> with
> > the 3-multiplexer. But there are other functions, such as the NAND
> and the
> > NOR functions that, by themselves, can create any other function,
> without
> > needing the NOT, the ZERO and the ONE. These are the ULMs I want to
> > distinguish from the more ordinary ones.
>
> Why?
>
Because with them you can find interesting solutions using just one kind of
gate. I think that, if for nothing else, this might be fun. And if fpga
technology allows people to use different kinds of gate such as the
3-multiplexer, why not use other complex modules? And if you know for sure
the module you are using is a NAND-like module you can even relinquish the
use of inverters and build circuits using just that gate.
Candida
---
Candida Ferreira, Ph.D.
Chief Scientist, Gepsoft
http://www.gene-expression-programming.com/author.asp
GEP: Mathematical Modeling by an Artificial Intelligence
http://www.gene-expression-programming.com/gep/Books/index.asp
Modeling Software
http://www.gepsoft.com/gepsoft/
Get APS 3.0 Std free with the book!
Article: 84556The C source code for the Jam Bytecode Player version 2.2 is available at http://www.jamisp.com. Altera has not published a version ported to the 8051 platform, because of the large memory requirements of the application, but an 8051 expert should be able to create an optimized version. The Jam STAPL format is a JEDEC standard, JESD71. The Jam Bytecode v2.0 format is an Altera format, and is not promoted as an industry standard. However, it is not a secret -- the player source code is public, and the format specification is available under NDA. If you would like the Jam Bytecode format specification please file a Service Request with our support center through http://mysupport.altera.com requesting the information. The applications engineer assigned to your service request will send you an non-disclosure agreement (NDA) that requires signature to receive the specification. Hope this helps. Subroto Datta Altera Corp.Article: 84557
Simon wrote: > Well, that's nice in theory, but certainly with the Wind/U toolkit it's > a no-go. Some X widgets (especially pulldown menus) are rendered in the > top-left corner of the screen, and the first choice is unavailable. In > other cases, the program simply crashes with a BadAccess error. Have you tried running it in VNC? I have many reasons to love VNC, persistence of my session in itself is enough. TommyArticle: 84558
Hi Y'all : I have many years of experience with hardware design, software design & implementation etc (i.e. I'm comfortable with C++, soldering or anything in between) I'm using FPGA"s more and more. So far, I've used schematic capture exclusively. I use Altera's Megawizard, so I know someone wrote some parameterizable VHDL behind this, but I still think in hardware terms. I never learned VHDL, and wonder if it's worth it. My take has been that I am designing hardware - configuring the LE's and interconnects and not writing algorithms. This seems to me to be mind-set that best fits what I'm doing. I notice that a lot of people here refer to "code" - suggesting they have an algorithmic mind-set What am I missing ? What would be some examples of something better done in VHDL ? Are there examples of stuff that cannot be done in schematic ? Any comments will be appreciated. GaryArticle: 84559
Greetings. I saw only two posts in the archives about reading the contents of a FPGA. I have a design based around an Altera Max7000 part that I am resurrecting after 5 years. I would rather not remove it from the circuit, but I can if need be. Can anyone with some experience give me some pointers or ideas? Thanks so much. -SteveArticle: 84560
> But the strange thing is that I connect the output of the PLL
> in my top level file to a net with the name "clk_90_sys"
> So
> pll_bank3:PLL_B_3|altpll:altpll_component|_clk1
> = clk_90_sys
>
> And yet it makes a difference, why?
Andre,
Quartus only has one name per net. So the long name above is the name of
the clock coming out of the PLL.
It sounds like you connected this net to an FPGA output I/O, with a name of
clk_90_sys. In that case, the signal going to the board will be called
clk_90_sys. However, that signal (clk_90_sys) is driven by an output I/O
cell, and is considered a different net than the PLL clock above, which was
an input to that I/O cell.
In an ASCII schematic you have:
------------ net = pll_bank3...|_clk1 -------------- net =
clk_90_sys
PLL block |----------------+------------->| I/O cell
|------------------------>
------------ | --------------
|
+----> to clock ports of
registers
Regards,
Vaughn
Altera
[v b e t z (at) altera.com]
Article: 84561Any idea why these special drivers are used ? Even simple parallel port access won't work without windrvr I guess! I was trying an old coolrunner board ( from the days of philips coolrunners ) which apparently has a parallel port JTAG interfae. Just trying to see if I could use that board. Thanks, George http://www.geocities.com/eda4linuxArticle: 84562
Hi > My take has been that I am designing hardware - configuring the LE's and > interconnects and not writing algorithms. This seems to me to be mind-set > that best fits what I'm doing. > > I notice that a lot of people here refer to "code" - suggesting they have an > algorithmic mind-set > > What am I missing ? What would be some examples of something better done in > VHDL ? Are there examples of stuff that cannot be done in schematic ? Well, when doing VHDL, you'd better be thinking hardware as well. VHDL is a language to describe the hardware you want built. When you code in VHDL, you don't think "algorithm", you think register, combinatorial logic and you describe that in VHDL. Note the exception about that is when you code testbench and "code generation". The first is just a behovioral description of the test environment and stimulus and don't need to be synthetizable. The latter is when you write "generic" VHDL code that needs to adapt somewhat to static option at synthesis time (not unlike the C preprocessor). The main advantage I see about HDL over schematic capture would be : - Vendor independent : I don't think the schematics are interoperable but I may be mistaken - Text edition : To write the vhdl, you can do it every where where you have a text editor, no need to have the vendor tools - Genericity : When you have a complex block that needs different fine tuning for different application, you can use parameters to change details. But that's just IMHO ... SylvainArticle: 84563
"JoeG" <JoeG@yahoo.com> wrote in message news:1ifje.1131$mK.405@newssvr13.news.prodigy.com... > James A wrote: > > Hi, > > > > I'm trying to find out when exactly the XC9572XL recognizes a falling edge. > > It has a 3.3V supply, and the signal is a square wave between 0V and 5V > > (this Xilinx is 5V input compatible). At what voltage would a falling edge > > trigger? > > > > Digital logic IO typically have a SINGLE threshold point despite the > guaranteed values of Vil & Vih -- there is only one threshold point -- > for TTL logic this has been around 1.5Vdc -- there are some logic which > incorporates two threshold points for such as Schmitt Triggers called > hysteresis .... Thank you Joe. Would the supply being 3.3V (rather than 5V) have any bearing on the 1.5V value? - JamesArticle: 84564
"Eric Smith" <eric@brouhaha.com> wrote in message news:qhmzqptwx7.fsf@ruckus.brouhaha.com... > "Marco" <marcotoschi_no_spam@email.it> writes: > > Does it function with every distribution of Linux? > > No. It is supported on Red Hat Enterprise Linux 3. You *might* be > able to get it working on another distribution, but Xilinx won't help > you with it. > > I suspect that it would run on CentOS 3.x without too much hassle, > because that's a clone of RHEL3. > > I've been able to use ISE BaseX 7.1i on Fedora Core 3 with only some > minor annoyances. > > > There is a way to try the 64 bit version or I need to recompile everything > > by myself? > > Good luck recompiling ISE without the source code. > > Eric Ohhhhh.... what a stupid I am! When I written about recompiling I thought that Xilinx include also source into CDs... impossible thing... So, the simple way to use ISE is with Windows... what a pity!!!Article: 84565
"Gary Pace" <xxx@yyy.com> wrote in message
news:5Kvje.113165$AE6.112367@tornado.texas.rr.com...
> I never learned VHDL, and wonder if it's worth it.
>
> My take has been that I am designing hardware - configuring the LE's and
> interconnects and not writing algorithms. This seems to me to be mind-set
> that best fits what I'm doing.
>
> I notice that a lot of people here refer to "code" - suggesting they have
> an algorithmic mind-set
>
> What am I missing ? What would be some examples of something better done
> in VHDL ? Are there examples of stuff that cannot be done in schematic ?
I too used schematic entry exclusively until the company ran into a larger
project, and we got sent off on VHDL course. Now it's exclusively VHDL, not
because there's any functional difference in my mind, but because I'm lazy.
True, I too refer to the file as 'code', but it's only 'code' or
'behavioural description' until it's been through the synthesis tool, just
as 'schematic' is only a 'drawing of funny looking boxes' until the
synthesis tool breaks it down. Algorithmic mindset, no. For me that somehow
implies sequential execution, and hardware isn't. I'm a C programmer too,
and I tried reading VHDL from a sequential-execution mindset. It didn't
work.
As an example (because I've done this both in schematic and VHDL), consider
a shift/count register typically used for a reciprocal frequency counter. In
schematic I constructed a symbol with a FF that would either count or shift,
and made a schematic with 28 of those symbols. Draw wires, think it over,
did I do it right, okay. If I want to expand the register, I need to draw
more.
When writing VHDL my mindset is still "I need a register, when not gated
open it should be a shift register, when gated open it should be a
synchronous counter. It should be clocked from refclock."
if rising_edge(refclk) then
if (gate='1') then
fcount<=fcount+1;
else
if (shiftpip='1') then
fcount<=fcount(fcount'LEFT-1 downto 0) & '0';
end if
end if;
end if;
Reading it goes like "There are some refclk-risingedge-clocked flipflops,
and there's a gate-controlled multiplexer in front of them. One input has
the output of an adder, the other the left shifted signals, and clock enable
is gate or shiftpip." And it's faster for me to read and convince myself
that it's right.
In my experience, once a schematic reaches the point where you think that
you 'really have a lot of wires on this page, and which ones end up where?'
VHDL entry handles the complexity better.
/Kasper
Article: 84566James A wrote: > "JoeG" <JoeG@yahoo.com> wrote in message > news:1ifje.1131$mK.405@newssvr13.news.prodigy.com... > >>James A wrote: >> >>>Hi, >>> >>>I'm trying to find out when exactly the XC9572XL recognizes a falling > > edge. > >>>It has a 3.3V supply, and the signal is a square wave between 0V and 5V >>>(this Xilinx is 5V input compatible). At what voltage would a falling > > edge > >>>trigger? >>> >> >>Digital logic IO typically have a SINGLE threshold point despite the >>guaranteed values of Vil & Vih -- there is only one threshold point -- >>for TTL logic this has been around 1.5Vdc -- there are some logic which >>incorporates two threshold points for such as Schmitt Triggers called >>hysteresis .... > > > Thank you Joe. Would the supply being 3.3V (rather than 5V) have any bearing > on the 1.5V value? > > - James > > Not much - it's still around 1.5Vdc ...Article: 84567
Gary Pace wrote: > Hi Y'all : > > I have many years of experience with hardware design, software design & > implementation etc (i.e. I'm comfortable with C++, soldering or anything in > between) > > I'm using FPGA"s more and more. > > So far, I've used schematic capture exclusively. I use Altera's Megawizard, > so I know someone wrote some parameterizable VHDL behind this, but I still > think in hardware terms. > > I never learned VHDL, and wonder if it's worth it. > > My take has been that I am designing hardware - configuring the LE's and > interconnects and not writing algorithms. This seems to me to be mind-set > that best fits what I'm doing. > > I notice that a lot of people here refer to "code" - suggesting they have an > algorithmic mind-set > > What am I missing ? What would be some examples of something better done in > VHDL ? Are there examples of stuff that cannot be done in schematic ? > > Any comments will be appreciated. > > Gary > > As many writers have commented you need to know hardware before you code VHDL -- as certain syntax & grammar of VHDL will infer logic ... Your extensive background in gate-level design will serve you well in VHDL.Article: 84568
Geogle <georgevarughese@indiatimes.com> wrote: > Any idea why these special drivers are used ? > Even simple parallel port access won't work without windrvr I guess! > I was trying an old coolrunner board ( from the days of > philips coolrunners ) which apparently has a parallel port JTAG > interfae. Just trying to see if I could use that board. While the Xilinx hardware people are very attentive here, i never notice anybody from the programming department listening here... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 84569
Hi,ARRON, I am afraid in current releases of EDK tools, there is a bug for SDRAM IP. In EDK,open the system.ucf file, to see if the Bank_Addr[] io pins are included in the ucf,if not,then you should manually add these clauses to the ucf. Good luck. jeffsenArticle: 84570
"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.05.21.11.10.11.679537@PleaseDontSpamMEpolybus.com... > > > Ohhhhh.... what a stupid I am! When I written about recompiling I thought > > that Xilinx include also source into CDs... impossible thing... > > > > So, the simple way to use ISE is with Windows... what a pity!!! > > No you don't have to subject yourself to Windows. It works fine with > Fedora Core 3. There are a couple of trivial work arounds that you need to > do. You need to set an env variable, > > setenv LD_ASSUME_KERNEL 2.4.7 > > And you need to create a link > > ln -s /usr/lib/libcurl.so.3.0.0 /usr/local/lib/libcurl.so.2 > > Only those? In this case I will download it immediately. ThanksArticle: 84571
> Ohhhhh.... what a stupid I am! When I written about recompiling I thought > that Xilinx include also source into CDs... impossible thing... > > So, the simple way to use ISE is with Windows... what a pity!!! No you don't have to subject yourself to Windows. It works fine with Fedora Core 3. There are a couple of trivial work arounds that you need to do. You need to set an env variable, setenv LD_ASSUME_KERNEL 2.4.7 And you need to create a link ln -s /usr/lib/libcurl.so.3.0.0 /usr/local/lib/libcurl.so.2Article: 84572
"B. Joshua Rosen" <bjrosen@PleaseDontSpamMEpolybus.com> wrote in message news:pan.2005.05.21.11.10.11.679537@PleaseDontSpamMEpolybus.com... > > > Ohhhhh.... what a stupid I am! When I written about recompiling I thought > > that Xilinx include also source into CDs... impossible thing... > > > > So, the simple way to use ISE is with Windows... what a pity!!! > > No you don't have to subject yourself to Windows. It works fine with > Fedora Core 3. There are a couple of trivial work arounds that you need to > do. You need to set an env variable, > > setenv LD_ASSUME_KERNEL 2.4.7 > > And you need to create a link > > ln -s /usr/lib/libcurl.so.3.0.0 /usr/local/lib/libcurl.so.2 > > Even if I use a 32 bit ISE version, may I download fedora 64 bit version?Article: 84573
Everything that you do in schematics you can do in VHDL i.e. as complete set of instantiated components wired as you want. But that is a terrible waste. Where you really win is something like a state machine where you can describe fairly complex behaviour in a relatively small number of lines. I have designed state machines up to 32 thousand states. Yes I did say 32 thousand and that took me about 2 weeks to enter and debug - mostly typing. Try doing that in schematic and not making a mistake or even fixing mistakes. There are lots of other examples where description is quicker and more reliable than schematic. You are also not ruled from using schematics to view the design, or even to do critical bits in schematic, or even doing vhdl netlist form. If you are comfortable with C++ then you will find a lot similarities in VHDL. VHDL can be written as very abstract code or very simple staying with a small number of constructs like if/elsif, case etc. Personally I prefer the simple approach to VHDL but each to their own as the saying goes. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Gary Pace" <xxx@yyy.com> wrote in message news:5Kvje.113165$AE6.112367@tornado.texas.rr.com... > Hi Y'all : > > I have many years of experience with hardware design, software design & > implementation etc (i.e. I'm comfortable with C++, soldering or anything in > between) > > I'm using FPGA"s more and more. > > So far, I've used schematic capture exclusively. I use Altera's Megawizard, > so I know someone wrote some parameterizable VHDL behind this, but I still > think in hardware terms. > > I never learned VHDL, and wonder if it's worth it. > > My take has been that I am designing hardware - configuring the LE's and > interconnects and not writing algorithms. This seems to me to be mind-set > that best fits what I'm doing. > > I notice that a lot of people here refer to "code" - suggesting they have an > algorithmic mind-set > > What am I missing ? What would be some examples of something better done in > VHDL ? Are there examples of stuff that cannot be done in schematic ? > > Any comments will be appreciated. > > Gary > >Article: 84574
Gary Pace wrote: > Hi Y'all : > > I have many years of experience with hardware design, software design & > implementation etc (i.e. I'm comfortable with C++, soldering or anything in > between) > > I'm using FPGA"s more and more. > > So far, I've used schematic capture exclusively. I use Altera's Megawizard, > so I know someone wrote some parameterizable VHDL behind this, but I still > think in hardware terms. > > I never learned VHDL, and wonder if it's worth it. > > My take has been that I am designing hardware - configuring the LE's and > interconnects and not writing algorithms. This seems to me to be mind-set > that best fits what I'm doing. > > I notice that a lot of people here refer to "code" - suggesting they have an > algorithmic mind-set > > What am I missing ? What would be some examples of something better done in > VHDL ? Are there examples of stuff that cannot be done in schematic ? > > Any comments will be appreciated. > > Gary > > IMHO: Schematic entry has always been a transitional addition to Programmable Logic tools, representing a merging of the old and the new. Comparing Schematic entry to VHDL is like comparing Hotmetal, Frontpage or some other WYSIWYG website design utility to HTML/XML etc. It is a tool, enjoy. If you are considering learning VHDL (or Verilog), my advice is a resounding YES; Do it, learn it. FPGA's will soon exceed present physical production limitations and we will have budget giga, tera and even peta gate FPGAs. VHDL makes designing complex and/or large hardware very easy compared to schematic entry; however visual descriptions are always easier on the eye. Now the contentions stuff: IMHO, IMHO, IMHO: (flame on!) It is all code. VHDL and Verilog are Hardware Description Languages. Various 3rd Generation Languages (3GLs) like Pascal, C, Basic etc are Functional description languages. ALL LANGUAGES are behavioral in concept; they are supposed to define and/or describe a "system's" behavior. In development circles the words "code" and "coding" are abbreviations borrowed from the words "encode" and "encoding". They describe the process (coding) and results (code) of translating a behavioral design from the mental landscape into a textual format; At these levels "it is all code". Now let us be really outspoken: Synthesis is not Compilation, although compilation is a form of synthesis. When comparing the two, people generally consider the outputs: compilation results in further code, now translated into binary form. However, compilation is more like synthesis than translation. Does not the binary result of synthesis define how an FPGA/CPLD/PLD should react to stimuli. Doesn't a compiled program do the same for a microprocessor? GIGO, Input, Process, Output. Who cares!! The argument is a philosophical one and thus one of opinion anyway. Here is a passing thought: If ADA never existed, what format would VHDL have. VHDL's designers WERE influenced. If C never existed, what form would Verilog or SystemC have. Their designers are influenced. If chicken never existed, what would everything else taste like!?! Nme. God Bless. P.S. IMHO: We will always have Schematic entry, humans like pictures, CAD, CAM, UML, SSADM, websites; we love diagrams and images, easier to digest.
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