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Hiya, > Hello: > does anyone have a positive experience with Quartus /Linux using a JTAG > interface ? I'm using a Byteblaster II (using parallel port) and it works fine. > What is the price of the hardware? A standalone cable costs $150, but mine came for free in a NIOS II devkit. There's also cheap clones on the market. BenArticle: 84651
On Mon, 23 May 2005 23:42:54 GMT, "Jansyn" <jansynf@worldnet.att.net> wrote: >"Gary Pace" <xxx@yyy.com> wrote in message >news:5Kvje.113165$AE6.112367@tornado.texas.rr.com... > >> What am I missing ? What would be some examples of something better done >> in VHDL ? Are there examples of stuff that cannot be done in schematic ? > >Hello, > >I have never used a HDL, but I have an opinion anyway, this is usenet. > >What I miss most is the ability to compare the file I am looking at to >last weeks version, or the version that Joe modified. I have not found >a way to do that with schematics. I have gotten very used to this for >firmware. > >If there are any software types looking for a project, I would pay for >a tool to do this. > >Ben 1) Print out the two schematics onto the thinnest (lightest) paper you can. 2) Place one page on top of the other, and align carefully. 3) Hold up to the light. 4) You owe me $0.02 PhilipArticle: 84652
Yes it works well, we have simulated it in modelsim.Article: 84653
Hi Jonathan, Thank you very much for your reply! Your information is very useful to me.Article: 84654
Hello All, I am looking at the reconfiguration capabilities of Virtex 4 devices. I have following questions related to Xilinx Virtex 4 configuration frames (frames here refer to the smallest addressable units in Virtex devices that can be reconfigured): a). What is the shape and size of a frame in Virtex 4 device? I know that in Virtex 2, each frame is one vertical column of the device. I also know that in Virtex 4 each frame contains fixed 41 words of data. But I could not find any information related to its shape in Virtex 4. b). How many CLBs does one frame include or vice versa? c). I have seen somewhere that Virtex 4 is a tile based device. Does it mean that each configuration frame is completely contained in one tile? If yes, how many frames/CLBs does one tile contain? d). Can we use the Xilinx JBits SDK to configure a Virtex 4 frame? The documentation for JBits 3.0 does not refer to Virtex 4 and only seems to support Virtex 2. If it doesn't support Virtex 4, what is the equivalent toolkit for Virtex 4 devices? Thanks in advance, Love SinghalArticle: 84655
Antti Lukats wrote: > Hi all, > > FPGA are fun to work with ... when the tools work. > New versions of the tools come out, then serice packs, but there is no light ... > > At the very present moment I am really in not good mood as I need to verify > some designs VERY URGENTLY and the tools just fail there where I need them. > > Antti I have some suggestions to Xilinx about the ise7.1 regarging the intaller etc. Since they are mostly not bugs, I thought may be I will just keep them under the page http://www.geocities.com/eda4linux/ise/Q2xlx.txt Mostly started with the frustrating experiance I had downloading the tool. I had tried 48Kbps, 28Kpbs speeds and gave up because of the restrictions the cafes have ( since I don't access from a company - I am not working for any currently), then I went downloading at around 7Kbps and it tooks around 18 hours to get the file. I heard that there are times when people had to lock up their phones for days to get the files!. I suppose there are others with same issues too!. I hope even the device support files can be made into seperate downloads. Final comment is about the performance issues I had. It starts with opening gui stuff. Anyways please have a look at the text and please comment. Thanks, GeorgeArticle: 84656
I am new to varification field. i have just written small test benches but for the first time i have to write a big. The equirement is like this. The main test bench should run from ModelSim. The selection of the UUT will be through VHDL. Once invoked, the code will pause and query the user for the stimulus file name and output file name. Compare the generated and the expected results and should disply the warnings and error. Also should generate a output file for this. Can anyone guide me. Thanking you.Article: 84657
Hi there, I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using Microblaze soft-core. My intention is to save packets recieved from the network in SDRAM for later process. I have been thinking of using a SDRAM FIFO to be able to process the packets after been saved in memory. As I am working with EDK 6.3 I was thinking of using a FIFO IP core to be used in SDRAM. Can this be done this way? EDK doesn't include any FIFO IP core on the predesigned cores. I also have thought of creating a FIFO with Xilinx COREGEN and then including the FIFO in my EDK project but I can'f figure the way of exporting the .vhd files created by COREGEN into my EDK project. Has anyone ever used a FIFO in external memory with positive results? Which is the best way to do this? Any advice will be appreciated since I am quite a newbie with FPGA's. Thanks in advance. Adrian Mora.Article: 84658
Methi,
Can you post the error message from Map?
Aurash
methi wrote:
>Hi..
>I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I
>tried adding some extra inputs and outputs to the top level entity and
>hence made the corresponding changes to the UCF file.
>But when I try implementing the design, it shows errors in the Map
>process as follows:
>1) The extra inputs I added in the UCF file are shown as invalid
>
>I have just used the format
>
>for example:
>
>NET "my_input_name" LOC = "P34" ;
>
>2)Should I also add INST?
>
>If so how should I do that and is it for all the component
>instantiations?
>
>3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ?
>
>I then removed the unused inputs and outputs but it still shows the
>same error...
>
>Any suggestions are welcome..
>
>Thanks in advance,
>
>Methi
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84659Yes, a Fifo in SDRAM is commonly done. Not sure about how you're approaching it? You'll need an "SDRAM controller" of some sort to interface to the external memory. That can be quite simple if you're going around the SDRAM pretty quickly, as the accesses will negate the need for refresh cycles, especially if your data is video or audio and can tolerate occasional bit errors in the worst case. Then you'll need some on-chip Fifos to buffer up a block of data for DMA burst into or out of SDRAM. You'll then need to create some controlling logic to sequence the DMA bursts, track your write and read pointers etc. Depending on your level of experience it's anything from a few hours work to a couple of weeks. I'm not sure if there's freeware out there that does it all for you? Could be, but in my experience it can often take as long to get on top of a piece of freeware as it does to design it from scratch for oneself. adrian wrote: > Hi there, > > I'm working on a packet analyzer on a Virtex2Pro xc2vp7 FPGA using > Microblaze soft-core. > My intention is to save packets recieved from the network in SDRAM for > later process. > I have been thinking of using a SDRAM FIFO to be able to process the > packets after been saved in memory. > As I am working with EDK 6.3 I was thinking of using a FIFO IP core to > be used in SDRAM. > Can this be done this way? EDK doesn't include any FIFO IP core on the > predesigned cores. > I also have thought of creating a FIFO with Xilinx COREGEN and then > including the FIFO in my EDK project but I can'f figure the way of > exporting the .vhd files created by COREGEN into my EDK project. > Has anyone ever used a FIFO in external memory with positive results? > Which is the best way to do this? > Any advice will be appreciated since I am quite a newbie with FPGA's. > > Thanks in advance. > > Adrian Mora.Article: 84660
Hi, Or you can build your own ByteblasterMV (using paralel port), it is cheaper than buying. You only need cable, 25pin male header connector, resistors and a 74HC244. Get the reference, titled ByteBlasterMV Parallel Port Download Cable, from Altera website. Regards, -arvanArticle: 84661
gralsto wrote: > Welp, > I ended up implementing a process that uses explicit if/elsif > statements to cover all cases and it appears to be working. Only > thing I could think of is that Xilinx's synthesis tool was doing > something odd that made it go into a random state, even though all > states should have been covered. Not sure if I really like the > solution, but if it works I guess I'll take it. Howdy Jesse, While the synthesis tool may have been doing something "odd" (where odd means something *you* weren't expecting), I suspect that chances are very slim that it was doing anything that was wrong or illegal. More than likely, it implemented the circuit in a way you didn't envision. Were you using the GBUF for your clock? Was DIN synchronized to CLK before feeding into the state machine? Have fun, MarcArticle: 84662
Hi has anyone succeeded to find Answer Record 21127 on Xilinx website? there are lots of references to it, but the Answer itself seems to unavailable :( AnttiArticle: 84663
Tom wrote: > I remember a few years ago we would have to run ISE PAR several times > in order to meet timing. One we had a decent layout, we would lock it > down because of the chance of never being able to reproduce it. Howdy Tom, > Does ISE still suffer nondeterministic placement? I wouldn't call it nondeterministic. To me, non-deterministic means that if you give a single version the EXACT same input two times in a row, you might get a different output. I don't believe that has been the case for a while now. What DOES happen is that if you change even the slightest thing, the synthesis tools (and therefore MAP and PAR) can take a VERY different "path" to implementing, mapping, and placing the design. Each is dependant on the previous step - so I think of it like the butterfly effect - a small (almost insignificant) change at the input can make huge changes at the output. That behavior most definitely does still exist - but the only suffering going on is on the part of you and I :-) > Also, how much has ISE PAR improved since 5.1/6.1? I'll take a stab since noone else has. The last huge improvement that I noticed was the -timing option for MAP, which I thought was introduced (or at least revamped) in 6.x. Other than that, I'm sure their algorithms have improved in general, but I've heard WAY too many cases, both on c.a.f and outside, of people re-running with newer versions tools and getting considerably different results (either it not fitting, or timing being off by a mile, or new errors, or in our case, the default I/O bank type changed). Even on dot releases, like between 6.1 and 6.3. Lastly, higher speed and/or density designs in the older families (Virtex, Virtex-E, Spartan-II and Spartan-IIE), 6.3 is probably what you want: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21382 MarcArticle: 84664
Antti Lukats wrote: > Hi > > has anyone succeeded to find Answer Record 21127 on Xilinx website? > there are lots of references to it, but the Answer itself seems to > unavailable :( Howdy Antti, I typed 21127 into the search engine on their top level site and it works fine for me... give it another try. I have run into a problem before where I had to exit my browser and get back in before the Xilinx site would work properly, so you might try that as well (as non-technical as it sounds). Have fun, MarcArticle: 84665
Right here http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=21127&iLanguageID=1 NicoArticle: 84666
Yes I got it on this link http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21127 . John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Antti Lukats" <antti@openchip.org> wrote in message news:d6v6te$g3k$01$1@news.t-online.com... > Hi > > has anyone succeeded to find Answer Record 21127 on Xilinx website? > there are lots of references to it, but the Answer itself seems to > unavailable :( > > Antti > >Article: 84667
Philip Freidin wrote: > On Mon, 23 May 2005 23:42:54 GMT, "Jansyn" <jansynf@worldnet.att.net> wrote: > >"Gary Pace" <xxx@yyy.com> wrote in message > >news:5Kvje.113165$AE6.112367@tornado.texas.rr.com... > > > >> What am I missing ? What would be some examples of something better done > >> in VHDL ? Are there examples of stuff that cannot be done in schematic ? > > > >Hello, > > > >I have never used a HDL, but I have an opinion anyway, this is usenet. > > > >What I miss most is the ability to compare the file I am looking at to > >last weeks version, or the version that Joe modified. I have not found > >a way to do that with schematics. I have gotten very used to this for > >firmware. > > > >If there are any software types looking for a project, I would pay for > >a tool to do this. > > > >Ben > > 1) Print out the two schematics onto the thinnest (lightest) paper you can. > 2) Place one page on top of the other, and align carefully. > 3) Hold up to the light. > 4) You owe me $0.02 > > Philip I like it! It's simple and elegant. You can also try the screen-based version of this method. Bring up the two schematics in two windows or buffers. View both at the same zoom level and position on your screen. Then quickly switch back and forth between the two views and look for something "flashing". I do this to compare graphics and sometimes text files as well.Article: 84668
pasacco wrote: > Hi > > I have a problem with using "IBUFG" and "RAMB16_S9" in Project > Navigator (ISE 6,3), when implementing. > > In VHDL, BRAM and IBUFG were just instantiated. > When VHDL-simulating in modelsim, it was okay using UNISIM. > > When synthesizing with XST, no errors are found but following warning > messages are seen. > > ------------------------------------------- > WARNING:Xst:766 - c:/xilinx/work/TOP.vhd line 79: Generating a Black > Box for component <IBUFG>. > . > . > WARNING:Xst:790 - c:/xilinx/work/MODULE.vhd line 127: Index value(s) > does not match array range, simulation mismatch. > . > .WARNING:Xst:766 - c:/xilinx/work/BLOCK.vhd line 81: Generating a Black > Box for component <RAM16X1D>. > . > . > WARNING:Xst:753 - c:/xilinx/work/RAM.vhd line 176: Unconnected output > port 'DOP' of component 'RAMB16_S9' > . > . > ------------------------------------------- > > Finally MAPPING errors are found as follows > > ------------------------------------------- > ERROR:Pack:1234 - F5 mux symbol > "AA_Mmux_data_inst_mux_f5_26111" drives more than one F6 mux > symbol, including symbol "BB_Mmux__n0024_inst_mux_f6_10". An F5 > mux may drive at most one F6. Please correct the design. > > ----- > INFO:LIT:95 - All of the external outputs in this design are using slew > rate > limited output drivers. The delay on speed critical outputs can be > dramatically reduced by designating them as fast outputs in the > schematic. > INFO:MapLib:562 - No environment variables are currently set. > INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted > to > Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to > constant 0: > BUFG symbol "CLK_bufg" (output signal=clk_int2) > ------------------------------------------- > > Can someone help me with this troubleshooting? > Thankyou in advance I would follow the hierarchy to the offending module. "AA" might be the instance name. It's unfortunate that the tools use underscore for hierarchy separators when most users also use the underscore within signal names... It almost looks like you've instantiated a black box that was built for a different architecture (part family). Do you have COREgen macros in your design? These may need to be refreshed or regenerated under new project settings. Good luck, GaborArticle: 84669
Hi all, I want to implement ethernet but I have no exprience about ethernet. Can you please recommend some thing. I can use precessor (M16C) or FPGA. I haven't got FPGA development board yet and maybe i can't buy because i have money problem. I think if I use FPGA I don't need ethernet controller If I can write it :). I have try some projects like as uart, I2C on the Nuhorizons CR2 Development board. What should i do? Thank to allArticle: 84670
Hello, I have a problem simulating a design made in Xilinx Platform Studio with EDK 6.3. The thing is, I cannot get compedklib to work. It cannot detect my ModelSim simulator, and therefore it will not compile the libraries I need for my simulation. I'm using the 6.3 EDK and ModelSim SE 6.0c. Does anyone know which environment variables I have to set for the compedklib to detect my installation of ModelSim? I have the following system variables: XILINX=c:\Xilinx XILINX_EDK=C:\edk MODELSIM=c:\modeltech_6.0c\modelsim.ini LMC_HOME=C:\Xilinx\smartmodel\nt\installed_nt LM_LICENSE_FILE=<..bunch of IP adresses..> all the paths above are correct. Does anyone else experience this same problem? Or does anyone using a similar config have a working system? Your help is appreciated. Thanks in advance, Jim TuilmanArticle: 84671
Peter Alfke wrote: > Just to confirm and expand on John_H's posting: > At the end of configuration, Xilinx applies an asynchronous (p)reset to > all flip-flops. That's the good news. > The bad news is that the trailing edge of this initialization signal, > even when it has been synchronized to the clock, has such a long > propagation delay, that it often straddles several incoming clock > periods. As a result, state machines can get half initiated and half > running. > The user is advised to augment the "free" initialization with > deliberate synchronous initialization of critical flip-flops. > Peter Alfke, Xilinx Applications. Thanks for the feed back John and Peter. Quick follow up question: I have a reset block which prolongs the reset and does a few other things. In addition to the Reset Button, I also take the lock output from the DPLL that generates the clock to the SoC. As long as there is no lock, I hold the system in reset, and even after a lock for some more cycles. So perhaps my reset should not be a problem after all ? If I assume that the lock signal of a DPLL would be asserted some time AFTER configuration ?! Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84672
Hi, we want to reprogram Spartan FPGAs via JTAG. We are not using Xilinx development tools so which programmer + cable do we have to buy ? Rgds Andr=E9Article: 84673
Hi Aurash, These are the error messages: ERROR:MapLib:681 - LOC constraint P53 on ref_27mhz is invalid: No such site on ERROR:MapLib:681 - LOC constraint P32 on sd_clk_en is invalid: No such site on ERROR:MapLib:681 - LOC constraint P28 on sdram_wr is invalid: No such site on ERROR:MapLib:681 - LOC constraint p78 on probe is invalid: No such site on the ERROR: MAP failed Thankyou, Methi Aurelian Lazarut wrote: > Methi, > Can you post the error message from Map? > Aurash > methi wrote: >Article: 84674
I am surprised you are not using Xilinx p&r tools. Anyway rather than invert the wheel again you can download from Xilinx, for free, a version of webpack tools for programming only. You can use any of the recent Xilinx cables or look-alikes with this software. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <ALuPin@web.de> wrote in message news:1116942071.998189.134920@o13g2000cwo.googlegroups.com... Hi, we want to reprogram Spartan FPGAs via JTAG. We are not using Xilinx development tools so which programmer + cable do we have to buy ? Rgds André
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