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I'm not sure about the 5v stuff because I have tested the fpga with a 5volt source and it hasn't harmed it yet, it could in the future and I believe it will if i keep doing it for a while but don't think that is the big thing. My program is designed to loop and continually update and display the status register via led's. As soon as I inverted the cs lines the 6.4 gb outputs started to make a whole lot more sense 1000 0000 -> 0101 0000 -> 0101 1000 -> 0101 0000 and after a while it then gives 0101 0001. So the error bit activates after I continually read the register. This sounds to me like its working now, and I have yet to test this drive again in the computer. Still the other drives won't respond though, strange. Big Boy wrote: > The problem is not really feeding the drive with 3.3V, it is more the > 5V that's comming back from the drive that can cause problem. You > should use level converters. > > I did desing an ATA interface in the past, but not with an FPGA, I > used a micro-controller (ATMEL). Make sure you set correct CS, > Address, and pulse DIOR. Also, take note that some of those signals > are inverted, make sure you use correct polarity, using inverter if > needed.Article: 85076
Hi Patrick, > I've got a big problem with a Altera Stratix Kit EP1S25. Is that the DSP kit or the NIOS kit? I've heard about problems with some of the newer DSP kits where the manufacturer stuck on different Flash chips than the old one. Best regards, BenArticle: 85077
Are you concerned about simultaneously switching outputs, ground bounce, and inductive crosstalk in BGA packages? Then join us this coming Tuesday or Wednesday for the second, even more detailed, technical seminar by Dr Howard Johnson. He is the foremost authority on signal integrity, and his book "High-Speed Digital Design, a Handbook of Black Magic" is on many designers' bookshelves (mine too). So, join the almost 1000 engineers who have already pre-registered for this informative hour. We intend to break all Xilinx (and TOL) attendance records. It is not "standing room only" because you just sit comfortably in front of your computer, and can enjoy a fast-paced, very informative, and even fun presentation. To join us on Tuesday, June 7 at 11 am Pacific Time, 2 pm East Coast time, 1900 in England, and 2000 in Central Europe (sorry, very early in Asia), register by clicking on http://seminar2.techonline.com/s/xilinx_jun0705 To join us for the same seminar, one day later and four hours earlier, on Wednesday, June 8 at 7 am Pacific Time, 10 am East Coast time, 1500 in England, and 1600 in Central Europe (sorry, even earlier in Asia), then register by clicking on http://seminar2.techonline.com/s/xilinx_jun0805 I'll just do the introduction, Howard presents all the interesting stuff. He is very good at that ! I guarantee that it will be an hour well spent, and well remembered. Peter Alfke, Xilinx ApplicationsArticle: 85078
dirk wrote: > For my latest Nios II DevKit I have received 2 additional Nios II 1.1 > Upgrades although the kit already came with this version. I haven't received > any copy of the 5.0 version so far. The most annyoing thing is that they > guarantee the updates for 1 year but never send any. I had another devkit > with the old Nios and never got the Nios II software or at least an > evaluation version of it. If they want us to download the new versions then > they should simply say so on their web site. From the information on the web > site I always get the impression that it's just an evaluation version and > not the real thing although with previous versions there was no difference > in the end. > > > "Jedi" <me@aol.com> wrote in message news:lFDne.179$YR2.156@read3.inet.fi... > >>So for how long is NIOS2 5.0 out? >> >>Just received today my NIOS2 1.1 upgrade... >>Unbelievable fast they are (o; >> Well...seems I getting an upgrade maybe...not sure if it also contains the NISO toolchain sources from the Linux CD as the Windows sources can be only compiled on Windows... But since I also develop FPGA hardware for local distributors here and do software porting for softcore platforms I am switching to Lattice and Actel since as a developer I get their full design software for free (o; rickArticle: 85079
If you can live wiith single-port operation, then you can easily split the BlockRAM. The easiest to understand is a BRAM with the same width for both ports. Then you just ground one (arbitrary) address bit for one port, and tie the same (!) address bit High for the other port. Both now have half the memory space, eachhas its own half. You can also partition differently, not just 50/50. And you can assign different width to the two ports, but you have to study the address assignments. You can figure all this out with the data sheet and the back of an envelope... Peter AlfkeArticle: 85080
I dont want to split into two pieces. I want to attach one BRAM block to the OPB bus, so it is visible from uBlaze. ZoleeArticle: 85081
That's what a dual-port RAM does naturally. Since you use different widths for the two ports, look at the mapping info in the data sheet. You can use both ports as read or write, even write simultaneously on both ports. Watch out for two things: When both ports use the same port, and one is writing, observe the clock edges, so you do not read at the moment of writing. When both write, make sure that the clock edges are not occuring at the same time, since that would give an undefined result. You cannot harm the hardware, but you might get corrupted data. When the two addresses are different, there are no precautions necessary. Peter AlfkeArticle: 85082
>
>
Follow Peter's suggestions for the actual circuit. In order to
implement it, you will need to instantiate the appropriate BRAM
primitive (RAMB16sxx_sxx or if V4 RAMB16) out of the unisim library, as
there are no synthesis tools that will infer it the way you want it.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85083Just a dumb question, but are you sure you selected the right package when compiling your code (not only the device family and size, but package too)? Make sure it's the same one that you used in ISE 6.3i.Article: 85084
Windows XP and Windows CE are targetted at *very specific* hardware. I.e., for example, Windows CE for a specific Palm PC have to be compiled with drivers specific for the hardware of that Palm PC. Moreover, that hardware (IO ports, screen, input pad, ...) have a specific memory address, or at least, have a specific way of determining their address (ex: over PCI bus protocol for a PC). Now, Windows is not only a core. It is a core with a lot of information on the device hardware (drivers, ...). So, you can not supply Windows CE for a bare FPGA CPU core. At least, if you design a specific SoC, with CPU, Memory, IO, Display, ..., that Windows CE will have to be customized for that specific arrangment. This meen writing a lot of drivers. Then, since each design is unique (with specific set of hardware, memory mapping, ...), all those drivers will need to be re-written each time someone would use the CPU core along with it's associated hardware. So, saying 'Windows for Nios2' would be the same as saying 'Windows for Pentium4' (here, speaking of the bare P4 chip without it's associated PC environment). I don't say that it's not possible to do the thing, but I seriously doubth Altera would release such OS (bare) with their cores. I also doubth that Microsoft would release their sacred OS source to anybody! However, if you desire to have an OS, you could check the Linux world... A lot are open-source, and you may even find ppl doing those sort of projects (Linux on FPGA board).Article: 85085
On Fri, 03 Jun 2005 15:24:00 +0700, Rudolf Usselmann <russelmann@hotmail.com> wrote: >Sorry to bring up this old topic again. > >Does anybody know how easy/hard it is to enforce IP Laws in >Taiwan ? Technically they are still part of China. But how >does reality look like ? Anybody has any experience with IP >Protection/enforcement in Taiwan ? > >Horror/success stories ? > >Thanks, >rudi I found the folloing article to be enlightening when I was thinking about this issue: http://www.edn.com/article/CA446987.html I find the PDF version a bt easier to read than the online version. The link is at the bottom of the page. Philip Philip Freidin FliptronicsArticle: 85086
savdeep@gmail.com wrote:
>hi,
> i am trying to do power estimation for xilinx fpga and decided use
>the xilinx xpower.i am not sure about how to fill in the toggle rate,
>the capacitive load,dc load during power analysis. i did look up the
>tutorials, but then i couldnt understand it clearly.can anyone explain
>to me how to go about?
>thanks
>dv
>
>
>
for toggle rate, you have to make an educated guess based on your
knowledge of your design. bit serial tends to have high toggle rates
50% or more. parallel arithmetic is quite a bit lower. For something
that is a parallel data path design with no time multiplexing, something
bewteen 10 and 20% is a fair shake.
For capacitances, you'll have to look at what you have connected to the
FPGA.
Keep in mind that the web calculator is little more than an educated
guess. I don't consider it more accurate than about +/-12dB. A huge
factor is the routing and number of pipeline stages between registers...
I've seen papers that claim as much as 30% power savings by going from
minimally pipelined to single level of logic between FF's, and that is
all just energy dissipated due to propagation of switching transients
thru the routing and fabric. Keep in mind that most of the FPGA is
routing resources, not logic, so trying to do a power analysis based
just on logic is going to incur a large margin of error.
The bottom line, is that the web tool is only an estimator. Given the
wide error margin, even that title is generous. That said, it still
appeases those who push for power estimates.
The full up xpower based on simulation vectors is far more accurate, but
even that is dependent on your simulation vectors being representative
of the real operation, and it still includes a healthy error allowance
for the statistical worst case part.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85087What core was being synthesized at the time of the crash? platgen reports the currently synthesized core in it's log. microblaze_0_wrapper (microblaze_0) - system.mhs:47 - Running XST synthesis mb_opb_wrapper (mb_opb) - system.mhs:69 - Running XST synthesis . . . You can cd into the synthesis directory and directly execute the synthesis project file. xst -ifn <inst_name>_wrapper.scr You'll see a <inst_name>_wrapper.srp file in the synthesis directory. Examine this file, the last line reported should give some indication as to what xst was doing before the crash. Ico wrote: > Hi, > > While taking my first steps with the EDK, I'm running into problems right away. > > - clean install of ISE 6.3i and EDK 6.3 > - start Platform studio > - Create a project for the 3L eval board with the wizard > - Create bitstream > > After a few minutes, the build breaks with the following message : > > FATAL_ERROR:HDLParsers:vhplib.c:466:$Id: vhplib.c,v 1.25 2003/05/22 00:46:02 > kumar Exp $:200 - INTERNAL ERROR... while parsing <no file> line 86. Contact > your hot line. Process will terminate. To resolve this error, please > consult the Answers Database and other online resources at > http://support.xilinx.com. If you need further assistance, please open a > Webcase by clicking on the "WebCase" link at http://support.xilinx.com > > The tricky part is probably "INTERNAL ERROR... while parsing <no file> line > 86". No references on google or on Xilinx support about 'vhplib.c', so no > idea where to start. > > Any ideas ? > > _Ico >Article: 85088
Falk Brunner wrote:
>I worked on this topic not too long ago, you CAN easyly detect multiple
>pressed keys withOUT having diodes in the matrix.
>All you need is a "walking one" scan.
>
>
That's fine for two key rollover, but not for more than 2 keys.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85089
The virtex2, virtex2p, etc. doesn't support byte-write enables
on bram blocks. Though v4 does.
In the Edk world, processor memories on v2-families use 4 bramblocks
to support the byte-write accesses.
Nonetheless, you can get around this requirement by modifying the
opb_bram_if_cntlr that interfaces to the bram_block. The controller
is a 32bit device so the datalanes match one for one. Read accesses
haven't changed from the original bram cntlr so they continue to be 3
clks. Write accesses have been extending so now the access time to
the bram to 3 clks. During a write access the cycles are as follows:
- 1st clk presents address to the bram
- 2nd clk reads data from the bram, decodes the BE signals, and muxes
the matching data
lanes. So the new data that contains a mix of orig. bram contents
and opb write data is
presented to the bram.
- 3rd clk writes the new mux'd data to the bram and acks the opb bus.
Hope this helps you get started. If you have V4, this would be alot
easier.
Zolee wrote:
> I want to share one BRAM block (RAMB16_S9_Sxx) between microblaze and
> my user logic. My user logic would use PortA (8 bits), microblaze could
> use PortB for 32 bit access.
> Microblaze is always using 4 BRAM block for 32 bit access, but I need
> only one BRAM block.
>
> How can I do this?
>
> Zolee
>
Article: 85090Also, you should also consider constructing your own bram_block that support 32-bit PORTA and 8-bit PORTB. Since you're still relying on platgen to enumerate the bram_block, platgen will only deliver uniform width PORTA and PORTB, so 32-bit on both interface ports. A modified bram_block that bypasses platgen enumeration that allows you to define 32-bit PORTA and 8-bit PORTB. In this flow, platgen does not generate a BMM for this modified bram_block. If you need info about tapping into the PORTB interface ports, read http://support.xilinx.com/techdocs/20353.htm Paulo Dutra wrote: > The virtex2, virtex2p, etc. doesn't support byte-write enables > on bram blocks. Though v4 does. > > In the Edk world, processor memories on v2-families use 4 bramblocks > to support the byte-write accesses. > > Nonetheless, you can get around this requirement by modifying the > opb_bram_if_cntlr that interfaces to the bram_block. The controller > is a 32bit device so the datalanes match one for one. Read accesses > haven't changed from the original bram cntlr so they continue to be 3 > clks. Write accesses have been extending so now the access time to > the bram to 3 clks. During a write access the cycles are as follows: > - 1st clk presents address to the bram > - 2nd clk reads data from the bram, decodes the BE signals, and muxes > the matching data > lanes. So the new data that contains a mix of orig. bram contents > and opb write data is > presented to the bram. > - 3rd clk writes the new mux'd data to the bram and acks the opb bus. > > Hope this helps you get started. If you have V4, this would be alot > easier. > > Zolee wrote: > >> I want to share one BRAM block (RAMB16_S9_Sxx) between microblaze and >> my user logic. My user logic would use PortA (8 bits), microblaze could >> use PortB for 32 bit access. >> Microblaze is always using 4 BRAM block for 32 bit access, but I need >> only one BRAM block. >> >> How can I do this? >> >> Zolee >>Article: 85091
Falk Brunner wrote: > <learnfpga@gmail.com> schrieb im Newsbeitrag > news:1117815955.528902.306240@g43g2000cwa.googlegroups.com... > >>Hi There, >>I have Orcad Express CIS 7.2 and I want to program Lattice ispLSI1016 >>using it. I already have the schematic for it in Orcad Express. Also I >>have the programmer for 44 pin isp1016. I was wondering if someone can >>guide me as to what steps I need to take after this. thanks > > > Go to www.latticesemi.com > Download the ispLever Software. > Install it. > Get a licence (its free) > Create a project. > Compile the schematics > Download the JEDEC file. > Njoy. > > Regards > Falk > > > Will ispLever work with something so old as 1016 ? I have also a couple of 2128's. Does it work with 2xxx also ?Article: 85092
I see three distinctly different purposes for a pre-design power analysis: 1. You want to estimate battery life and required battery size, cost, and weight. 2. You want to install the appropriate Vcc regulators, definitely not too small. 3. You want to estimate thermal conditions, especially junction temperature. #3 is the toughest, since it allows the least margin. If you have to design for 50 degr C ambient, and want to keep the junction temperature under the specified 85 degrees C, you are walking a fine line. Without a heatsink, you never get below 10 degrees/W, which means 3.5 W is your max limit. With a good heatsink and plenty of airflow, you can tolerate far more power, but with modern high-performance circuits you will always be close to the edge. Which means you estimator has to be accurate. An answer of "somewhere between 5 and 10 W" does'nt help you much, and "somewhere between 10 and 20 W" is even worse. Power consumption is a very important issue. You should forgive us for our relentless attacks on our competitor Altera. In many cases, the part with the guaranteed lower power consumption wins, and it is worthwile to explore all the advanced design methodologies in order to reduce power. Virtex-4 helps, if you are willing to use its power-saving options, like DSP slices, FIFOs etc. Modern FPGAs are not just seas of LUTs that you simply throw VHDL at. It pays to do some creative thinking and planning, if you want to avoid the power=heat crunch.. Peter Alfke, from home.Article: 85093
You should try this: <http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13810> Hope this helpArticle: 85094
And nobody saw my response explaining the fallacy of multiple-key encoding: Imagine a 2 by 2 matrix with all four switches closed. Then open one of them: No detectable difference. Ray already wrote: 2-key rollover is ok, multiple switches not. Peter Alfke, from homeArticle: 85095
Hi , When I tried to use Chipscope Pro Analyzer for programming the V2Pro fpga . I was able to succesfully connect the cables from PC to board. But when I tried to do add a bit stream file created using jtagclk as start clk, I got the following error message. ERROR: Wrong configuration stream for device INFO: Found 0 Core Units in the JTAG device Chain. Please suggest me the solution for the same. Regards, KishoreArticle: 85096
> Will ispLever work with something so old as 1016 ? ispLever 4.2 still supports the 2k series. Regards FalkArticle: 85097
<nkishorebabu123@rediffmail.com> schrieb im Newsbeitrag news:1117868292.521726.208680@g14g2000cwa.googlegroups.com... > Hi , > > > When I tried to use Chipscope Pro Analyzer for programming the V2Pro > fpga . I was able to succesfully connect the cables from PC to board. > > But when I tried to do add a bit stream file created using jtagclk as > start clk, I got the following error message. > > ERROR: Wrong configuration stream for device > INFO: Found 0 Core Units in the JTAG device Chain. > > Please suggest me the solution for the same. > > Regards, > Kishore > well it is exactly what the message says, you have bitstream for an device that doesnt match the device that you are trying to configure... you can download with impact and then connect with analzyzer, do you see the core then? anttiArticle: 85098
>> >> FATAL_ERROR:HDLParsers:vhplib.c:466:$Id: vhplib.c,v 1.25 2003/05/22 00:46:02 >> kumar Exp $:200 - INTERNAL ERROR... while parsing <no file> line 86. Contact >> your hot line. Process will terminate. To resolve this error, please >> consult the Answers Database and other online resources at >> http://support.xilinx.com. If you need further assistance, please open a >> Webcase by clicking on the "WebCase" link at http://support.xilinx.com >> >> The tricky part is probably "INTERNAL ERROR... while parsing <no file> line >> 86". No references on google or on Xilinx support about 'vhplib.c', so no >> idea where to start. I Solved it; my project was located under 'documents and settings', and spaces in the pathname to the project seems to cause strange result. _icoArticle: 85099
Hi I am new to FPGA and wanted to try out the ISE Webpack from Xilinx, I have registered at the site but when I try to download the file, I am asked for a login when I enter my login info the same as my registration info, it clears the fields and asks again. After 3 times the browser reports an error and it terminates the process. I have written to the software registration and European support but havent got a reply from them as yet. could someone tell me what is the mistake I am making ? Thanks in advance Indroneel
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