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I designed two related cards (not a PCI plug in unit) that had 2 PCIX 133/64 busses, amongst a lot of other things. My implementation (and it worked) as to assume a 'zero length' motherboard for one of the devices, and set the routing rules appropriately. That part was close up against the bridge. The other part was a significant distance away, so I kept the differential rules between groups and set the routing rules based on maximum track lengths (8 inches for PCIX 133, according to the device manufacturer) and that worked fine as well. I will say it took me as long to set up the rules as it did to draw the schematic :) The tolerances are somewhat looser than Falk notes. The clock track, for example, if memory serves, was 2.5 inch +/- 0.1 inch on the expansion (plugin) board. As I noted though, the exact specs are available, and that is what should be used if you want to make a PCI implementation that will work properly. Cheers PeteSArticle: 85101
Hi I have used Coregnerator FIR filter in my desing. Initially i have used fixed coefficients, which is stored in BRAM area. and the design is working fine Now i want to have the flexiility to change the filter coefficient in the BRAM dynamically, but how do i write to that BRAM used by that particular FIR filter ? (i have one more FIR running in parllalel with fixed coefficients loaded to another BRAM area) Thanks bijoyArticle: 85102
Hi Rudolf and Prasannakumar, Thanks for your reply. Let me put my question like this. In my USB core i have so many interfacing signals which are interfacing with the ARM Processor and the external world (D+ and D- etc...). What i would like to know is how to handle all these interfacing signals with AMBA AHB/APB, and is there any reference document which describes the timing issues between the USB core and AHB Bus signals according to AMBA Specification 2.0. Regards... Joe Rudolf Usselmann wrote: > Joe wrote: > > > Hi Folks, > > > > Any inputs regarding interfacing USB1.1 with ARM Core(7TDMI) > > using AMBA AHB/APB 2.0 Specification?? Your help will be greatly > > appreciated. > > Please take a look at our USB IP Cores as well (www.asics.ws), > we have USB 1.1 and USB 2.0 Device and OTG IP Cores. All of our > IPs support AHB, OPB, AVALON, PLB, OCP, WISHBONE and many custom > buses as well. > > Best Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85103
Jan Pech wrote: > Hello all, > > Currently we use Windows and 32 bit Linux versions of ISE. We are > looking for a way how to increase speed of design implementation. Has > someone done any real-world comparison of implementeation (synthesis + > map + p&r) run times between 32-bit and 64-bit ISE for Linux? Will > upgrading to 64 bit Linux machines bring any shortening of design > implementation run time? And if so, how much? At least some rough > estimation, please. > > I would welcome something like... design implementation runtime on > Athlon XP 3000+, 2GB RAM was 30 minutes, after upgrading to Athlon A64 > 3000+, 2GB RAM the same design took just 20 minutes to implement;) > > Thanks for all replies, > Jan It took me a very long time to install ISE 64 bit. I did not have RHEL, and it would not install on Fedora Core 3 x86_64. I was only able to install the 32 bit version. Finally I have downloaded CentOS, which is equivalent to RHEL, but built by some group from the sources and than freely distributed. I went a bough a separate drive for this process, as I really did not want to screw up a perfectly working setup. I installed CentOS on the new drive, than ISE 64 bit, and the latest patch 7.1.02i ... (btw, centos made my dual opteron system slower than my 750 MHZ lab notebook - I winder if RHEL is the same way). Anyway after the installation, I rebooted in Fedora Core 3, mounted the new drive, and copied the newly installed ISE 7.1 64 bit to my usual tools location. After installation, ISE 64 seems to works just fine under Fedora Core 3. So, was it all worth the effort ? Here are two test results. I have scripts where I can switch the actual version of ISE and EDK that I use. I did two trial runs: ISE 7.1 32 bit ============== Virtex 4 lx60 (15% full) Elapsed time: 13:27 virtex 2-1000 (66% full) Elapsed time: 10:36 ISE 7.1 32 bit ============== Virtex 4 lx60 (15% full) Elapsed time: 13:39 Virtex 2-1000 (66% full) Elapsed time: 11:24 So speed wise, there was virtually no difference at all. Since I only have 2G of memory, using the 64 bit version did not add any other advantages as well. I did not have the time to see if I can now use chip scope and program devices directly from the compute server. That might be the only advantage, to have native 64 bit modules which are required if you want to use you Parallel Cable under linux. Now I hope Altera can send me a copy of Quartus for Linux x86_64, so I can try that out as well ! Hope this helps, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85104
Hello I have 'Virtex II pro FF1152 board, Rev.3' made by Memec design. I read the document 'Getting Started with EDK and Montavista Linux'. http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf And I followed the directives in the document. but I had a trouble. In the document, I should generate ACE file in the XPS like below $ xmd -tcl genace.tcl -jprog -board ml300 -hw implementation/download.bit -elf ../linux/arch/ppc/boot/images/zImage.embedded -ace top.ace But, I don't have System ACE module. Only what i have is 4MByte ATMEL AT45DB321B flash memory. To download something in this flash memory, I should have '*.mcs' file made by iMPACT. Could tell me how could I make *.mcs file instead of *.ace file. Of course, I know how to make *.mcs file from download.bit file using iMPACT. But I want to know how can I make *.mcs file including both download.bit and zImage.embedded files. Thank you ahead. Beomseok Lee from South KoreaArticle: 85105
beomseok,lee <aw2310@hanmail.net> wrote: > But I want to know how can I make *.mcs file including both > download.bit and zImage.embedded files. hint: try the tool "SRecord". A powerfull tool set for manipulating and join eprom/flash images: <http://srecord.sourceforge.net/> man srec_cat For manipulating & import object files like platform specific ELFs take look on objcopy - it is part of the GNU binutils. Can produce a memory dump of (selected) contents of the input object file. <http://www.gnu.org/software/binutils/> man objcopy WD --Article: 85106
Falk Brunner wrote: >>Will ispLever work with something so old as 1016 ? > > > ispLever 4.2 still supports the 2k series. > ispLever 5.0 also has 1k and 2k support..not for the oldest one though...but I could use the 1016E LC44 type for generating a JEDEC file for my old ispLSI1016 PLCC CPLD's (o; rickArticle: 85107
Hello, there is a method described as part of the UltraController-II Reference Design see http://www.xilinx.com/bvdocs/ipcenter/data_sheet/uc2_quickstart_tutorial_prom.pdf a similar method in application note xapp694 Holger "beomseok,lee" <aw2310@hanmail.net> wrote in message news:1117882072.4d3713f13c94bbca92baf237a66b3943@teranews... > > > > Hello > > I have 'Virtex II pro FF1152 board, Rev.3' made by Memec design. > > I read the document 'Getting Started with EDK and Montavista Linux'. > http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf > > And I followed the directives in the document. but I had a trouble. > > In the document, I should generate ACE file in the XPS like below > > $ xmd -tcl genace.tcl -jprog -board ml300 -hw implementation/download.bit > -elf ../linux/arch/ppc/boot/images/zImage.embedded -ace top.ace > > But, I don't have System ACE module. > Only what i have is 4MByte ATMEL AT45DB321B flash memory. > > To download something in this flash memory, I should have '*.mcs' file > made by iMPACT. > > Could tell me how could I make *.mcs file instead of *.ace file. > > Of course, I know how to make *.mcs file from download.bit file using > iMPACT. > > But I want to know how can I make *.mcs file including both > download.bit and zImage.embedded files. > > Thank you ahead. > > Beomseok Lee > from South Korea > >Article: 85108
Big Boy wrote:
> So, you can not supply Windows CE for a bare FPGA CPU core. At least,
> if you design a specific SoC, with CPU, Memory, IO, Display, ..., that
> Windows CE will have to be customized for that specific arrangment.
> This meen writing a lot of drivers.
That's obvious.
> I don't say that it's not possible to do the thing, but I seriously
> doubth Altera would release such OS (bare) with their cores.
I think we should terminate this thread, because I didn't know
that NIOS2 is not free. I've seen (and downloaded) a free version
of the NIOS2 Evaluation Package, but it seems it is very limited.
And since $1000 is way too much for amateur purposes, I
have just forgotten about NIOS...
> However, if you desire to have an OS
Currently I would like to have a free and efficient 32-bit CPU... ;-)
Best regards
Piotr Wyderski
Article: 85109Will Hua Zheng <Hua.Zheng@jpl.nasa.gov> writes: > And you are right, you can practice with simulation tools first (this > lets you see the inner-workings of your design, not just the output). Blinking leds and displaying stupid messages on the 7-segment things is more fun than reading pages of $monitor() outputs ! MB -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 85110
Joe wrote: > Hi Rudolf and Prasannakumar, > > Thanks for your reply. Let me put my question like this. In my USB > core i have so many interfacing signals which are interfacing with the > ARM Processor and the external world (D+ and D- etc...). What i would > like to know is how to handle all these interfacing signals with AMBA > AHB/APB, and is there any reference document which describes the timing > issues between the USB core and AHB Bus signals according to AMBA > Specification 2.0. > > Regards... > Joe There is no easy/simple answer for you question. It boils down to understand what all those signals do and how to drive them. For example it took us more than two man-years to design a fully verified and functional AHB USB controller. So please don't expect to solve this problem in a few emails to a news group ! Best solution for you would be to either purchase a USB IP Core or use an external device for USB interface. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85111
Brane2 <brane2@anonymous.com> ha scritto: >Will ispLever work with something so old as 1016 ? > >I have also a couple of 2128's. Does it work with 2xxx also ? Last summer I had to work with an old 1032 PLD for my thesis. Lattice sent to my university lab the ispLever software, but it did not have the support for that old device. So they sent me the so called "Obsolete package", which added the support for older devices. Then it was possibile to use the 1032 device. If you want I can send you that package. Bye -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email addressArticle: 85112
It might be a silly question, but I want to make sure somthing. I got a description about *.mcs file like below ---------------------------------------------------------------------- MCS-86 File An Intel PROM format (.mcs) file supported by the Xilinx tools. Its maximum address is 1,048,576. This format supports PROM files of up to (8 x 1,048, 576) = 8,388,608 bits. -------------------------------------------------------------------- Dose this description mean I can't make *.mcs file containing over 1MByte data? Thanks in advance!Article: 85113
yes that will be a great. will I still need isplever 5.0 or just the obselete package will be enough for ispLSI1016? ThanksArticle: 85114
Hi Peter, > Then join us this coming Tuesday or Wednesday for the second, even more > detailed, technical seminar by Dr Howard Johnson. He is the foremost > authority on signal integrity, and his book "High-Speed Digital Design, a > Handbook of Black Magic" is on many designers' bookshelves (mine too). Have book, will attend. Even though I'm in the opposite camp, I will definitely join the seminar on Wednesday. I've been to Dr Johnson's lectures before, and I've even found his material appliccable to designs running as low as 32MHz. Dr Johnson has a very entertaining way of presenting, so the only thing I can do is to second Peter, and thank Xilinx for the opportunity to get an update on my design skills. Best regards, BenArticle: 85115
"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message news:d7sjk2$acj$1@news.dialog.net.pl... > Big Boy wrote: > >> So, you can not supply Windows CE for a bare FPGA CPU core. At least, >> if you design a specific SoC, with CPU, Memory, IO, Display, ..., that >> Windows CE will have to be customized for that specific arrangment. This >> meen writing a lot of drivers. > > That's obvious. > >> I don't say that it's not possible to do the thing, but I seriously >> doubth Altera would release such OS (bare) with their cores. > > I think we should terminate this thread, because I didn't know > that NIOS2 is not free. I've seen (and downloaded) a free version > of the NIOS2 Evaluation Package, but it seems it is very limited. > And since $1000 is way too much for amateur purposes, I > have just forgotten about NIOS... > >> However, if you desire to have an OS > > Currently I would like to have a free and efficient 32-bit CPU... ;-) > > Best regards > Piotr Wyderski www.opencores.org Free , I don't know how efficient any of the cores are. I believe one of the openrisc cores has actually been fabbed. http://www.opencores.org/projects.cgi/web/or1k http://www.opencores.org/projects.cgi/web/or1k/overview has gnu toolchain http://emsys.denayer.wenk.be/?proj=empro&page=intro http://emsys.denayer.wenk.be/?project=empro&page=news&id=22 tutorial for openrisc with xilinx AlexArticle: 85116
Ben Twijnstra wrote: > Hi Peter, > > >>Then join us this coming Tuesday or Wednesday for the second, even more >>detailed, technical seminar by Dr Howard Johnson. He is the foremost >>authority on signal integrity, and his book "High-Speed Digital Design, a >>Handbook of Black Magic" is on many designers' bookshelves (mine too). > > > Have book, will attend. > > Even though I'm in the opposite camp, I will definitely join the seminar on > Wednesday. I've been to Dr Johnson's lectures before, and I've even found > his material appliccable to designs running as low as 32MHz. > > Dr Johnson has a very entertaining way of presenting, so the only thing I > can do is to second Peter, and thank Xilinx for the opportunity to get an > update on my design skills. > > Best regards, > > > Ben > > Howard's good but I prefer Rod Strange of Fast Edges Inc for SI ...Article: 85117
Peter Alfke wrote: > Are you concerned about simultaneously switching outputs, ground > bounce, and inductive crosstalk in BGA packages? Then join us this ... > Peter Alfke, Xilinx Applications Peter, do you know if there will be videos or CD/DVD available for those who can not attend in person ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85118
On Sun, 5 Jun 2005 05:38:42 +0900, "beomseok,lee" <aw2310@hanmail.net> wrote: >It might be a silly question, but I want to make sure somthing. > >I got a description about *.mcs file like below > >---------------------------------------------------------------------- > >MCS-86 File > >An Intel PROM format (.mcs) file supported by the Xilinx tools. Its maximum >address is 1,048,576. This format supports PROM files of up to (8 x 1,048, >576) = 8,388,608 bits. > > >-------------------------------------------------------------------- > >Dose this description mean I can't make *.mcs file containing over 1MByte >data? > >Thanks in advance! > > > Well, that depends on the implementation. The Intel file format specification supports 32 bit addresses (4GB), but many programmers don't bother to support the extended linear address record. See; http://www.microsym.com/intelhex.pdf ================================ Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.comArticle: 85119
TechOnLine provides web-based seminars over the internet. You have two choices: 1. You can participate in real time anywhere in the world, where you also can type in questions to the spaker, who will answer (most of) these questions in the final minutes of the webcast. And some of thee questions have, in the past, been very interesting, and the answers were very informative. 2. You can later listen to these TechOnLine seminars from their archives, at any time you pick. I will describe the procedure tomorrow, when I am back at work. 3. Xilinx is also creating CDs withthe content of these seminars. I will describe that, too. Peter Alfke, from home.Article: 85120
Correct. Synplify Proto's versions are all RTL (instead of gate level tuned for ASIC mapping) implementations so they can be efficiently mapped to FPGAs. Jon Beniston wrote: > I thought the deal with Proto was that it provides its own version of > lots of designware modules... Maybe I'm wrong. > > Cheers, > Jon >Article: 85121
Hello to all! Does anyone know of a design involving a TI TMS320 DSP as a soft-processor in FPGA? I found the model of the TI TMS320C6713 in FMF Model List! I would like to test this DSP with a VHDL model that I will design, but for now, I don't have a board with both an FPGA and the TMS320C6713! I do have a development board with an FPGA. With the TMS320C6713 as a soft-processor, I would test everything (C driver for the TMS320C6713 and my VHDL Peripheral). Is this possible? Thanks to all Best Regards BrunoArticle: 85122
Peter Alfke wrote: > And nobody saw my response explaining the fallacy of multiple-key > encoding: > Imagine a 2 by 2 matrix with all four switches closed. > Then open one of them: No detectable difference. > Ray already wrote: 2-key rollover is ok, multiple switches not. > Peter Alfke, from home > Unless Praveen has each of the 36 keys wired to a separate CPLD pins with common ground or pull-ups, it would make more sense to group the keys. I suggest grouping keys that will not be depressed together. If the keypad where hexidecimal with 18 additional control keys: you could group/encode the hexidecimal into a single nibble (4bits) and add 3x6bits (18bits) for the treatment of simultaneous control key depression. ------------------ Personally I would output an encoded 8bit byte for each row, at a maximum of 5 simultaneous keys per row. bits 0-4 (5bits) would hold 5 simultaneous key states, bits 5-7 (3bits) would denote which of the 8 rows (Row:0,1,2,3,4,5,6,7) the first bits 0-4 represented. Yes treatment is 40keys. Yes a full scan is 64bits wide. However the data is transfered in very common and manageable 8bit groups. Hey, I did say personally! Nme. God Bless.Article: 85123
Does anyone have experience with Orcad Express CIS 7.2? I am trying to creat an EDIF or EDN file that can be used in ispDS+ software so that it can create JEDEC file to burn Lattice 1016 44 pin. Some people suggested earlier that there may be other ways available but unfortunately I am stuck with this. I am pretty sure that I am doing something terribly wrong with ORCAD. Any help or suggestions are most welcome. ThanksArticle: 85124
"learnfpga@gmail.com" <learnfpga@gmail.com> ha scritto: >yes that will be a great. will I still need isplever 5.0 or just the >obselete package will be enough for ispLSI1016? The package is an add-on to ispLever, so you also need it. I don't remember the version of ispLever I used. I hope the Obs. package Ihave works also for your version of ispLever. Tomorrow I should be able to send you the file to your email. Bye -- Per rispondermi via email sostituisci il risultato dell'operazione (in lettere) dall'indirizzo -*- To reply via email write the correct sum (in letters) in the email address
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Compare FPGA features and resources
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