Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
> I used Synplify for many years but I haven't used it recently. I > switched to XST about a year ago when it got to the good enough > level. XST improves with each release, my gut says that it's pretty close > to Synplify's level at this point. Hi Josh, Thanks for the feedback. That's pretty much along the lines of my belief...and the high maintenance cost for Synplify is quite a deterrent to continuing using it IMO. I have one design that is running at 280MHz in a V2, and makes timing with Synplify, and a PCI-X core that makes 100MHz (I'd like to get it to make 133 though) with Synplify. I should benchmark these two and see how XST compares. Regards, AustinArticle: 85626
"Austin Franklin" <austin@dark99room.com> schrieb im Newsbeitrag news:911re.4452$Ub4.3176@fe06.lga... > > I used Synplify for many years but I haven't used it recently. I > > switched to XST about a year ago when it got to the good enough > > level. XST improves with each release, my gut says that it's pretty close > > to Synplify's level at this point. Recently, I had a design, not really a big deal. Running at 36 and 72 MHz. XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 LUTs to ~ 1200 LUTs). Speed was not the problem, both implementation where fast enough. But Synplify was more area efficient. We are using XST only, this was just a test with a real case. Regards FalkArticle: 85627
Hello all, I want to thank you for your comments. I should have said that in 90% of the work that is done is my shop will always come back to the shop for upgrades, or will be passed onto another engineers for testing. In most cases the original engineer is around to answer any questions, but in a hypothetical case if that design engineer left the job position and he/she did not document their work (either in their code or schematics) or decided not to follow a communication interface standard then the new engineer must take additional time to figure that out. I work for the government and when I see this happen I get upset because this extra time costs the taxpayers money. Furthermore, I have taken a few Systems Engineering courses and what I most remember is to document your work and that most engineering problems occur at the interface. I get frustrated when I see my co-worker not following these suggestions and don't set a good example to the newer engineers. Seems to be if one follows some of the things in a Systems Engineering course, or a Risk Management course, or an Interoperability course you actually save the tax payers money for the total cost of the design. Thanks again and if you find any good web resources on best practiced please let me know. joe jjlindula@hotmail.comArticle: 85628
Hi Falk, > Recently, I had a design, not really a big deal. Running at 36 and 72 MHz. > XST was not able to squeeze it into a XC2S50E, but Synplify was. (~1600 LUTs > to ~ 1200 LUTs). Speed was not the problem, both implementation where fast > enough. But Synplify was more area efficient. Interesting. What versions of the tools were you running? I'll check the area use on the current designs I have and see how they compare. Regards, AustinArticle: 85629
Sylvain Munaut wrote: > So I'd say yes, you can easily beat the P4 for such a dedicated task. > The problem as you stated is to get the data in and out. 50Mpixels par > second at 24bits color is over the PCI peak rate (133Mbyte/s and it's > never reached). True for PCI 32/33, but don't forget about PCI 32/64, PCI-X and PCI-E. You'll only find PCI-X on server grade motherboards, but at 64/133MHz, you get a good GByte/s odd (not all of which you will get, but still fairly high). You can get PCI-E on newer motherboards as well, with theoretical bandwidths of 2.5Gbit per lane (312MByte/s per lane). I'm not too clear on what you can practically achieve with PCI-E - the technology is still fairly new to me. PCI-E is available on non-server grade motherboards too - I'm figuring that the possibility of using a standard PCI-* interface is probably easier than trying to integrate the device as closely as the northbridge :) JeremyArticle: 85630
Hi Berty, "Berty" <wooster.berty@gmail.com> wrote in message news:1118422196.919890.240980@g44g2000cwa.googlegroups.com... > More over sometime gated clock is the only way as clock enable will not > stop the power consumption. > If not all than most of the cellular phone in the market and similar > product which you want to work for long time but have limited power > supply work with gated clock. > So you CAN have RELIABLE gated clock design. > Saying so obviously this should not be the normal route but the > exception one. > Have fun. Of course you can have reliable gated clock designs...but FPGAs are not conducive to them. I believe most all if not all the chips used in cell phones are custom chips and not FPGAs. Do you know of any current production level cell phones with FPGAs in them? Regards, AustinArticle: 85631
Hello, I came in contact with FPGAs at the university and have done some designs. Now I decided to start with FPGAs in private because I'm really fascinated by their capabilities. I think designing a PCB for an FPGA is not simple so I decided to buy a board for my first (home) steps, but I've some requirement to that board, because flashing LEDs isn't really interesting... :) It should be a Spartan3 1000 or above with a bootflash for a stand alone powerup and maaaany free pins to connect a lot of things. Things like clock oscillator and power supply are included on any board I think. The next point is external RAM. I'd like testing microblaze with uC linux but I never worked with linux, especially not with the uC version so I don't know how much external RAM is neccessary. Any suggestions? I've searched the web and only found a single board that has most of my requirements and can be paid by a student: http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 Sorry, can't find the page in english. It has a Spartan3 1000 with Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point I'm missing is the external RAM. So my question is, do you have any alterntive boards in mind that fits my requirements and can be paid? What do you think by the board above? Is it ok? Thanks, MichaelArticle: 85632
Hi But for timing simulation if i add the signals of my internal modules, i am not able to make out the signals i used in the design and the signals it shows in the wave window don't know how to interpret the signals shown in the wave window to signals i defined in my design regards bijoyArticle: 85633
There is a huge list of boards with FPGAs listed here: http://www.fpga-faq.org/FPGA_Boards.shtml On Mon, 13 Jun 2005 01:52:42 GMT, michaeldre@gmx.de (Michael Dreschmann) wrote: >Hello, > >I came in contact with FPGAs at the university and have done some >designs. Now I decided to start with FPGAs in private because I'm >really fascinated by their capabilities. >I think designing a PCB for an FPGA is not simple so I decided to buy >a board for my first (home) steps, but I've some requirement to that >board, because flashing LEDs isn't really interesting... :) > >It should be a Spartan3 1000 or above with a bootflash for a stand >alone powerup and maaaany free pins to connect a lot of things. >Things like clock oscillator and power supply are included on any >board I think. >The next point is external RAM. I'd like testing microblaze with uC >linux but I never worked with linux, especially not with the uC >version so I don't know how much external RAM is neccessary. >Any suggestions? >I've searched the web and only found a single board that has most of >my requirements and can be paid by a student: >http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 >Sorry, can't find the page in english. It has a Spartan3 1000 with >Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point >I'm missing is the external RAM. >So my question is, do you have any alterntive boards in mind that fits >my requirements and can be paid? What do you think by the board above? >Is it ok? > >Thanks, > Michael =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 85634
Hi Gabor ,
Thanks for the reply. My EEPROM is write protected i will only be
reading the first 128 bytes, is this flow diagram all right.
1-bit 8-bits 1-bit
Start from master --->> EEPROM Slave address("10100001") -->> ACK
from eeprom --->>
8-bits 1-bit
8-bits 1-bit
Write register address "00000000" --->> ACk from EEPROM --->> Data[0]
from EEPROM --->> ACK from master
8-bits 1-bit
................. --->>Data[127] from EEPROM --->> STOP from master
I will generate the STOP condition after receiving 128 bytes.
Any comments on this.
Regards,
Praveen
Gabor wrote:
> praveen.kantharajapura@gmail.com wrote:
> > Hi all,
> >
> > I am implementing a SPD interface in an FPGA. The DDR SDRAM is from
> > MICRON.
> > Now to redd the EEPROM content(first 128 bytes) , first i will send the
> > slave addres of EEPROM over I2C(with r/w='1' , which indicates a
> > read).Now my question is will the EEPROM send all the bytes serially at
> > one shot, OR should i address which byte i want to read explicitly ??
> >
> >
> > Regards,
> > Praveen
>
> I2C EEPROMs come in more than one flavor. The simplest with up to 256
> bytes use a single byte address. Larger ones need more address bytes.
> To access the data starting at zero, you must write zero to the EEPROM
> address register, if not you can get data starting at some random
> address.
>
> For the small EEPROMs (which are big enough to store SPD for most
> applications) you would write zero (one byte) then read any number
> of bytes. The address increments after each read, whether or not
> you send them within one start-stop sequence. This is why you need
> to reset the address before you start reading.
>
> You don't need to use a repeated start sequence to read the EEPROM.
> You can just do a simple write (one byte of address for small EEPROMs
> two or more for larger ones) followed by simple reads. Beware that
> writing too many bytes to the EEPROM can cause data to be written
> if the device is not write protected. i.e. if you have a 24C02 and
> send two bytes of zero, you'll clear the first byte in the EEPROM.
> Also if you write too many bytes you'll start reading after the byte
> written (byte 1 in the example just mentioned).
>
> So to sum it briefly. Writing multiple bytes starts with the address
> register and continues with data. If the address register is one byte,
> only the first byte after the I2C address cycle goes to the address
> register and subsequent bytes go into the EEPROM starting at the
> address
> just written and incrementing with each byte. After the writes are
> done,
> the address register keeps its value which will point to the location
> after the last one written (or to the address written if no bytes were
> written to the EEPROM). Reading always starts from the location in
> the address register, which increments after each byte. You must write
> to force the address register to a known value before you start to
> read.
>
> Regards,
> Gabor
Article: 85635Michael Dreschmann schrieb: > I've searched the web and only found a single board that has most of > my requirements and can be paid by a student: > http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 > Sorry, can't find the page in english. It has a Spartan3 1000 with > Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point > I'm missing is the external RAM. There is a Memory (and other things) extension for that board available: http://shop.trenz-electronic.de/catalog/product_info.php?products_id=49 Kolja SulimmaArticle: 85636
"Kolja Sulimma" <news@sulimma.de> schrieb im Newsbeitrag news:42ad2275$0$1125$9b4e6d93@newsread4.arcor-online.net... > Michael Dreschmann schrieb: > > I've searched the web and only found a single board that has most of > > my requirements and can be paid by a student: > > http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_27&products_id=63 > > Sorry, can't find the page in english. It has a Spartan3 1000 with > > Xilinx Plattform-Flash XCF04 and USB 2.0 transceiver. The only point > > I'm missing is the external RAM. > > There is a Memory (and other things) extension for that board available: > http://shop.trenz-electronic.de/catalog/product_info.php?products_id=49 > > Kolja Sulimma the OP wanted a board with UC linux capability, what you suggest has too small memory to hold linux :( AnttiArticle: 85637
I have done this for a microblaze system and this is what I've found for the
linker script:
FOOAREA (W): ORIGIN = 0x80000000, LENGTH = 0x200
. = ALIGN(8);
.fooregs : {
*(.fooregs)
} > FOOAREA
In the software you can use this as follows:
static __foo_regs__ UINT foo_registers[64];
static volatile UINT * const foo_register = (UINT *) foo_registers;
The fooarea is not initialised at startup, but AFAIK it must be possible to
do this (you have to define this in the linkerfile where the area is
declared). The align keyword will indicate at what boundary variables in
this area are laid (here at 8 bytes aligned addresses).
Frank
<kittyawake@gmail.com> wrote in message
news:1118419423.339828.290570@g44g2000cwa.googlegroups.com...
> hi all,
> i am trying to collect some data and store in the memory.I want this
> data to be continuous.Can i write my own section like
> (.text,.sdata,.bss,etc..) in the linker script??and then assign a
> pointer which points to this section and store the data using this
> pointer???I have never written a linker script before.Please give me
> some suggestions if i want to write such a section in linker
> script.What does ALIGN(8) or ALIGN(4) mean?
> thanx
>
Article: 85638Hi, I had problems implementing an IPCore "Dual Port Memory" in a new block of my code. It seems that the instanciation of the memory influences the functioning of the blocks feeding the memory input.I'd like to know if there are some particolar precautions to take to use an IPCore and more specially the Dual Port Memory. ThanksArticle: 85639
we have used a external power supply: 5 V DC , 10 A. The "random stop" for the processor still continue anyway. Can I conclude that it is not a power supply problem ? Ben Popoola a =E9crit : >=20 > What about the current consumption, especially of Vccio?Article: 85640
On Mon, 13 Jun 2005 11:40:20 +1200, Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com> wrote: >Sylvain Munaut wrote: >> So I'd say yes, you can easily beat the P4 for such a dedicated task. >> The problem as you stated is to get the data in and out. 50Mpixels par >> second at 24bits color is over the PCI peak rate (133Mbyte/s and it's >> never reached). > >True for PCI 32/33, but don't forget about PCI 32/64, PCI-X and PCI-E. >You'll only find PCI-X on server grade motherboards, but at 64/133MHz, >you get a good GByte/s odd (not all of which you will get, but still >fairly high). You can get PCI-E on newer motherboards as well, with >theoretical bandwidths of 2.5Gbit per lane (312MByte/s per lane). Actually the 2.5 Gb/s is with electrical bit rate which results by encoding using the 8b10 code so it is not available as data rate at all. The best logical bit rate is 2 Gb/s on top of which you put all the framing, packetization etc. so actual utilization is still lower than that.Article: 85641
Hallo, ich bin auf der Suche nach einem g=FCnstigen FPGA-Prototyping Board. es sollte auf einem Altera Cyclone bzw. CycloneII Baustein basieren. (oder einen der von der QurtusII Web edition unterst=FCtzt wird) w=FCnschenswerte features: RS232 2xUSB (1.1 oder 2.0 target und host) Ethernet SDRAM audio interface mit codec VGA IRDA LCD (4x40) Bedienfeld (Tastatur) wenn also jemand was passendes hat, bitte melden! hariArticle: 85642
Rob wrote: > Hello! > > Does anyone know where I can get the symbol for an XC2VP30-FF896 part? I > use OrCAD. > > Many thanks, > Robert The reason that ORCAD users seem to ask this question more often than most is because this bit of the tool is poorly documented. You can easily copy/paste from EXCEL. 1) Get the pinout into two columns in excel, pin number and description. You can play with the fitter ouput to get this for your design or use the excel files that Xilinx provide. However the generic xilinx tries to document every IO possibility on each pin. 2) Select the pins in a column and ctl C 3) Place a pin array onto a symbol with the number of pins that you need, of type IO. 4) Select the pins and ctrl E. 5) Select the column you want to paste into and shift insert. Change the pins that aren't IO into whatever. ColinArticle: 85643
At the date :2005-06-10 06:37:51 I sendt out a message with the subject: A lot of trouble when trying to debug c code on MicroBlaze. I am really stucked there and I have not fixed the problems yet nor got any help, so in relation to that problem I will ask some more questions. A short description on my problem first: If I use XMD - Software debugger or debugging by SDK the debugger seams to go out of scope when I am about to enter a function, but this happends quite randomly. It is not all the time at a particular function. An other problem I have is with the UartLite low level driver. Q1. If I use the function XUartLite_RecvByte in the function main it seams to work, but if I use it in a subfunction it does not work. I know it is easy to "look blind" at c-code some times so I cant comment on that, other that I have tried many times in various ways. Have anyone experienced that kind of problem before? How did you solve it? Q2. After reseiving the right commandbyte I have a forloop with 1024 iterations where I send a pulse on one GPIO and read 16 bit data from GPIO. (The data is taken from a fifo outside the MicroBlaze but inside the chip.) When that is done I try to send 2048 bytes of data on the UartLite, but not a single byte is sendt. Again, It is easy to "look blind" on c-code but here is no kind of while loops, only for loops. This means that if I put a breakpoint after the functions the debugger should sooner or later stop at the breakpoint but it does not. It goes out of scope. Have anyone had simmilar problems before? What did you do to fix it? Q3. The debugger seams unstable. If I go through the (most of the) code once and later tries to run to a breakpoint through code that is finnish debugged, the debugger goes out of scope. If I step through safe earlier debugged code it might get out of scope at a function. The functions generally contains GPIO only and no loops. Is the GPIOs or debugger unstable? does anyone have had problems with that? I use opb_gpio version 3.01.b I use version 7.1 XPS. RaymondArticle: 85644
Hi, I want to implement a SCSI Ultra-160 or SCSI Ultra-320 host on a VirtexII-Pro FPGA. My goal is to connect the FPGA to an array of SCSI disks. This is proprietary link so I don't need full adherence to the specifications. My questions are: 1- Is Xilinx LVDS I/O compatible to the SCSI LVD standard? 2- Is it possible to implement a LVD Multidrop SCSI bus with a VirtexII-Pro FPGA? Thanks!Article: 85645
Well I found out what the error was and thought of sharing it anyway :) http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=18626&BV_SessionID=@@@@2078588891.1118659968@@@@&BV_EngineID=ccccaddelghkdlicefeceihdffhdfjf.0 Joey "Joey" <johnsons@kaiserslautern.de> schrieb im Newsbeitrag news:d8c9sd$kni$1@news.uni-kl.de... > Hi, > > Recently I was trying to implement a plb peripheral. I made a plb peripheral > device using the "Create/Import Peripheral" utility and edited the > user_logic.vhd file according to what I needed. I didn't forget to Import > the peripheral after editing. > Now here is the problem. When I used this peripheral in XPS and generated > the netlist, it gave me the following error and exited. > > > XST synthesis > plb_decoder_0_wrapper (plb_decoder_0) - > E:\Test\xps_decoder\try01\system.mhs:63 > - Running XST synthesis > ERROR:Xst:813 - > E:/Test/xps_decoder/try01/pcores/plb_decoder_v1_00_a/hdl/vhdl/user_logic.vhd > line 53: Body of function UNSIGNED_NUM_BITS not found. > ERROR:MDT - HDL synthesis failed! > INFO:MDT - Refer to > E:\Test\xps_decoder\try01\synthesis\plb_decoder_0_wrapper_xst.srp for > details > ERROR:MDT - platgen failed with errors! > make: *** [implementation/reset_block_wrapper.ngc] Error 2 > Done. > > The plb_decoder_0_wrapper_xst.srp fiel doesn't say much either. It just > exits where it enters the user_logic.vhd file after the library > declarations. I am also giving a part of the .pao file where all my files > listed can be seen: > > lib plb_decoder_v1_00_a support_4M_pk > lib plb_decoder_v1_00_a parameter_4M_pk > lib plb_decoder_v1_00_a derived_param_4M_pk > lib plb_decoder_v1_00_a types_4M_pk > lib plb_decoder_v1_00_a Bit_Node <== UNSIGNED_NUM_BITS is in this file > lib plb_decoder_v1_00_a Shuffle_controller > lib plb_decoder_v1_00_a barrel_shift > lib plb_decoder_v1_00_a decoder_4M_top > lib plb_decoder_v1_00_a generic_dual_port_ram > lib plb_decoder_v1_00_a serialnode > lib plb_decoder_v1_00_a top_interface > lib plb_decoder_v1_00_a user_logic > lib plb_decoder_v1_00_a plb_decoder > > I have the above mentioned function in my Bit_Node (.vhd) file which also > accesses all those 4 packages already mentioned in the first 4 lines. Can > anybody help me ? > > Joey > >Article: 85646
Well I found out what the error was and thought of sharing it anyway :) http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?getPagePath=18626&BV_SessionID=@@@@2078588891.1118659968@@@@&BV_EngineID=ccccaddelghkdlicefeceihdffhdfjf.0 Joey "digi" <digitreaco@yahoo-dot-de.no-spam.invalid> schrieb im Newsbeitrag news:SfOdnUmCl8oD9jXfRVn_vg@giganews.com... > Do you have choose .prj file in Wizard? >Article: 85647
Hallo, I have made some searches with google, but I don't have found anything. There is someone who could tell me about a state machine to read/write into ram with chip enable and write enable in VHDL? Some web link would be very appreciated. Many Thanks MarcoArticle: 85648
A small Quiz, for C programmers
****** c code starts here *****
temp = docrc(temp2);
xil_printf("CRC: %08X\r",temp);
temp = docrc(temp2+1);
xil_printf("CRC: %08X\r",temp);
xil_printf("\r\n-- 1");
temp = docrc(temp2);
xil_printf("CRC: %08X\r",temp);
xil_printf("\r\n-- 2");
temp = docrc(temp2+1);
xil_printf("CRC: %08X\r",temp);
xil_printf("\r\n-- 3");
****** c code ends here *****
the above c program should print "CRC: " how many times?
did you guess 4?
wrong! Correct answer is 3 if the code is compiled with microblaze GCC
provided by Xilinx, here is the terminal log:
****** terminal log starts here *****
CRC: 53EE6CD2
-- 1CRC: 1142FDE5
-- 2CRC: 53EE6CD2
-- 3
****** terminal log ends here *****
the first printout is defenetly missing. I am not dreaming, another person
did verify the c code and terminal print.
This is exactly the same kind of problem I had with mb gcc llooooong time
ago, then I also was forced to add
call_donothing_bullshit();
in some places of my code! thoes where really dummy call's but without them
the code did not work.
I did expect this kind of problem not to exist any more. But now I dont
wonder any more why John Williams can not use EDK 7.1 GCC for uClinux
compiling, if such type of bugs exist I would be real surprised if the
compiled linux kernel would work
Antti
PS I will ZIP the full project archive and send to some Xilinx personel if
they are interested, but I am not opening a webcase. Even if the webcase
management takes only 30 minutes of my time. I dont have that time right now
(to be wasted).
Article: 85649
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag
news:d8jrvf$7nv$00$1@news.t-online.com...
> A small Quiz, for C programmers
>
> ****** c code starts here *****
> temp = docrc(temp2);
> xil_printf("CRC: %08X\r",temp);
> temp = docrc(temp2+1);
> xil_printf("CRC: %08X\r",temp);
>
> xil_printf("\r\n-- 1");
> temp = docrc(temp2);
> xil_printf("CRC: %08X\r",temp);
> xil_printf("\r\n-- 2");
> temp = docrc(temp2+1);
> xil_printf("CRC: %08X\r",temp);
> xil_printf("\r\n-- 3");
>
> ****** c code ends here *****
>
> the above c program should print "CRC: " how many times?
> did you guess 4?
>
> wrong! Correct answer is 3 if the code is compiled with microblaze GCC
> provided by Xilinx, here is the terminal log:
>
> ****** terminal log starts here *****
> CRC: 53EE6CD2
> -- 1CRC: 1142FDE5
> -- 2CRC: 53EE6CD2
> -- 3
> ****** terminal log ends here *****
>
> the first printout is defenetly missing. I am not dreaming, another person
> did verify the c code and terminal print.
>
> This is exactly the same kind of problem I had with mb gcc llooooong time
> ago, then I also was forced to add
>
> call_donothing_bullshit();
>
> in some places of my code! thoes where really dummy call's but without
them
> the code did not work.
>
> I did expect this kind of problem not to exist any more. But now I dont
> wonder any more why John Williams can not use EDK 7.1 GCC for uClinux
> compiling, if such type of bugs exist I would be real surprised if the
> compiled linux kernel would work
>
> Antti
> PS I will ZIP the full project archive and send to some Xilinx personel if
> they are interested, but I am not opening a webcase. Even if the webcase
> management takes only 30 minutes of my time. I dont have that time right
now
> (to be wasted).
>
SORRY - I was about to start a new thread so I picked up a random news hit
reply and forgot to change subject properly so my news appeared as followup.
this was un intentianal.
but the posting I happened to reply was also about problems with microblaze
and debug.
just before seeing this 'missing' print I also noticed some weird behaviour
in simulator, but I was testing SDRAM so maybe this was something with the
caches, dont know, but i did get different readings from cached sdram area
until it was all reading 00000, but initially it was filled with xilinx
memory tesst and I only did reads in XMD
antti
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z