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Messages from 88925

Article: 88925
Subject: Re: Fine grain vs. Coarse Grain Architectures
From: Martin Ellis <me_ncl@hotmail.com>
Date: Wed, 31 Aug 2005 18:14:39 +0100
Links: << >>  << T >>  << A >>
Alissobn Brito wrote:
> I would like to choose a strategy to implement a dynamic partially
> reconfigurable architecture, but I think that the first thing to decide
> is, what granularity it should have.

I don't think this is the first thing to decide on at all.

I suggest going back thinking about why you want to do dynamic
reconfiguation....

Which applications do you think you can improve by the technique?

Are your computations suited to coarse-grained logic (in which case,
you might be better off with a general purpose processor) or
is it something like multimedia or crypto, or other operations that aren't
particularly efficient on general purpose processors?

To what extent do you need to reconfigure your system?
Is it just specialising your logic for particular values,
or do you need to to change the purpose of the logic at each
reconfiguration?  Also, how much compute power do you have to manage
reconfiguration?

As 'cool' as partial dynamic reconfiguration might be, it's hard
to do something that's actually useful.  The clearer you are on the
specifics of what you are *trying* to do, the easier it will be to make
something useful.
It's probably better for you to have something that works very well
on one particular application, than something that's not very good
on a wide variety of applications.

For example, consider the work they did at Glasgow Univ. on the topic.
As far as I remember, they were very specific in terms of the optimisations
they were trying.

Martin

Article: 88926
Subject: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 31 Aug 2005 10:49:17 -0700
Links: << >>  << T >>  << A >>
Brian C. Van Essen wrote:

> Well, I have tried to find the reset_trigger_process in all of the 
> libraries vhdl files, but was unable to. 

Was there source code at:
C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd
?
> I am guessing that it is part 
> of a library like unisim (which is commented to be a Xilinx library).  
> If that is the case, then I am not sure how to correct it if the library 
> is already compiled.

If you don't have the source, you
can't debug it, only the owner can:
http://www.xilinx.com/support/techsup/tappinfo.htm

Or if you have a Mentor Modelsim license
open a case with them.

> Again, any more feedback would be wonderful.

If you need IP by others, buy the source code.


         -- Mike Treseler

Article: 88927
Subject: Re: Hello A newbie to FPGA
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 31 Aug 2005 11:07:42 -0700
Links: << >>  << T >>  << A >>
Please,

You need to join the university support forum:

http://www.xilinx.com/univ/profsupport.htm

This page is for university and school students, and their questions.

It is a separate and complete support system.

http://toolbox.xilinx.com/cgi-bin/forum

is a list of useful forums we sponsor, and newsgroups that might be 
helpful.  Although it mentions comp.arch.fpga, I suspect you will get 
better help from one of the targeted forums which match your interests.

Austin

davelye wrote:

> Currently doing a project in school relating to FPGA. Will try to
> explore more here and hope to interact with the members here.
> regards
> 

Article: 88928
Subject: Re: Hi-Z input
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 31 Aug 2005 11:43:22 -0700
Links: << >>  << T >>  << A >>
Z is for data bus drivers.  I don't think
you can use it at an input and have it make any sense.

You should probably pull down or pull up your input
pins in PACE.  I don't know if there is a way to sense
that the device has outputed Zs and therefore has gone
into powerdown.

Brad Smallridge
b r a d @ a i v i s i o n . c o m



Article: 88929
Subject: Re: Hi-Z input
From: "Marco" <marcotoschi@nospam.it>
Date: Wed, 31 Aug 2005 20:48:55 +0200
Links: << >>  << T >>  << A >>

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:11hbuit7s8ddf1c@corp.supernews.com...
>Z is for data bus drivers.  I don't think
> you can use it at an input and have it make any sense.
>
> You should probably pull down or pull up your input
> pins in PACE.  I don't know if there is a way to sense
> that the device has outputed Zs and therefore has gone
> into powerdown.
>
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m
>
>

I have seen I can chhose pull up or pull down into PACE, but could you 
explain what does it means pull up, or pull down, please?

Thanks
Marco 



Article: 88930
Subject: Re: Fine grain vs. Coarse Grain Architectures
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 31 Aug 2005 11:59:07 -0700
Links: << >>  << T >>  << A >>
Alissobn Brito wrote:
> What are the main advantages of Fine Grain
easier to fit

versus Coarse Grain
easier to route

       -- Mike Treseler

Article: 88931
Subject: Spartan-3 LVDS driving TFT LCD panel..?
From: Mike Harrison <mike@whitewing.co.uk>
Date: Wed, 31 Aug 2005 19:04:24 GMT
Links: << >>  << T >>  << A >>
Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link
I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention
recently about using the DDR registers to reduce the data rate but couldn't immediately see any
Xilinx appnotes when I had a quick look.
 
Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v,
what happens if you lie to the software about the supply - will it work to any useful degree
(interested in lvds output only)?

Article: 88932
Subject: Re: Hi-Z input
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 31 Aug 2005 12:05:51 -0700
Links: << >>  << T >>  << A >>
Marco wrote:
> Hallo,
>  have connected an external signal to my spartan 3. When the external
> peripheral goes into power down mode, the signal goes into Hi-Z state.
>
> I have made a process sensitive to the external signal.
>
> if (ext_signal = 'Z') then
>   ...
>
> Using this syntax the fpga doesn't "see" the high impdance state and
> considerthe signal 0 or 1.
>
> What could I do?

I'd be very surprised if the synthesis tool (I presume XST?) didn't
complain or error out on that (ext_signal = 'Z') comparison.  There's
no way for the FPGA logic to detect that a signal is undriven, which is
what happens when a driver is tristated.

About all you can do is to figure out some way for your peripheral to
signal that it's powered up.  I don't know the details of your
peripheral, so that's something you'll have to figure out.

-a


Article: 88933
Subject: Re: Hi-Z input
From: "Eric" <ericjohnholland@hotmail.com>
Date: 31 Aug 2005 12:13:25 -0700
Links: << >>  << T >>  << A >>
http://en.wikipedia.org/wiki/Pull-up_resistor

I suggest you read the datasheet for your A2D. I have a "funny" feeling
your approach to this problem is wrong.

Eric


Article: 88934
Subject: Re: Low Power RTL Design
From: Ray Andraka <ray@andraka.com>
Date: Wed, 31 Aug 2005 16:59:32 -0400
Links: << >>  << T >>  << A >>

>
>  
>
you can greatly reduce power at the expense of performance by operating 
the FPGA at a reduced voltage. Austin Lesea can tell you more about it.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 88935
Subject: Re: Hi-Z input
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 31 Aug 2005 14:28:20 -0700
Links: << >>  << T >>  << A >>
> I have seen I can chhose pull up or pull down into PACE, but could you 
> explain what does it means pull up, or pull down, please?

These relate to the internal resistors that you can attach to input pins. A 
pull up
resistor connects from the input pin to the supply voltage and leaves you 
with
a logical '1' if the input is unconnected on your board or connected to 
something
that is in the high Z state, like your peripheral.  Pull down is the same 
concept
accept that the resistor goes to ground leaving you with a logical '0' at 
the input
for unconnected or non-driven inputs.  It's a good idea to have a pullup or
pulldown on any input that may be left unconnected.  These resistors are 
suppose
to be marginal so that there effect can be easily overdriven by any active 
source.

You will also see a choice called a keeper, which tends to drive an 
unconnected
or undriven pin to its last state, that is to supply voltage or to ground. 
Not sure
what that is used for, except, perhaps to save power.

What are you doing that requires you to see the powerdown state?  Perhaps 
the
data from this peripheral has some unused data sequences, like all 1's or 
all 0's
that can be used to signal that powerdown state.

Brad Smallridge
b r a d @ a i v i s i o n . c o m







Article: 88936
Subject: Re: Spartan-3 LVDS driving TFT LCD panel..?
From: Sylvain Munaut <com.246tNt@tnt>
Date: Thu, 01 Sep 2005 00:32:32 +0200
Links: << >>  << T >>  << A >>
Mike Harrison wrote:
> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link
> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention
> recently about using the DDR registers to reduce the data rate but couldn't immediately see any
> Xilinx appnotes when I had a quick look.

Look at
http://www.xilinx.com/bvdocs/appnotes/xapp298.pdf

It's not for TFT panels but for their TX side, they serialize 10 bits by
using a 5x clock and DDR flips flops with a differential output.


> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v,
> what happens if you lie to the software about the supply - will it work to any useful degree
> (interested in lvds output only)?

Well, on lower end board, the trace might not be routed as differential
anyway. The Avnet spartan 3 board (the PCI one) I have has 4 LVDS pairs
connected on 2.5v rail.

That's definitly something I'd like to do. I might try it soon with an
old laptop scree if I find the doc for it.



	Sylvain

Article: 88937
Subject: Spartan 3 Serdes
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Wed, 31 Aug 2005 15:52:32 -0700
Links: << >>  << T >>  << A >>
Currently I am transfering 9 bits of data from one
Spartan 3 to another using  9 LVCMOS25 lines.
A 30 MHz clock supplies a source clock or "data strobe"
which I have brough into a DCM for signal alignment.

I would like to serialize this to free up some of the 9 lines
for other uses. Some of the Xilinx App notes seem a little
too high end.  What can I do with just flops and muxes?
What sort of bandwidth can I get? I would like to keep
my BRAMs free.

Brad Smallridge
b r a d @ a i v i s i o n . c o m




Article: 88938
Subject: New PCI Express Group
From: "Mark" <msmith3@gmail.com>
Date: 31 Aug 2005 16:40:01 -0700
Links: << >>  << T >>  << A >>
Folks,

A new group specifically for PCI Express has been started at:
http://groups.google.com/group/PCI-Express

This group is NOT officially linked to the PCI-SIG (although they did
send us their best wishes for this group, when I asked permission), but
is designed to be an open forum for ANYONE involved with PCI Express
from end users through to folks involved with defining the future
specifications.

Feel free to drop by, join up and ask/answer some questions or just
post your feelings about this pervasive protocol.

Hopefully, we can all learn something.

Please note: This group is NOT intended to be a black-market forum for
illegal exchanges of the protocol or other Intellectual Property. The
specifications can be ordered by non-members of the PCI-SIG by using
the orderform ont he PCI-SIG website (www.pcisig.com)

Best regards

Mark


Article: 88939
Subject: Re: Spartan 3 Serdes
From: "Mark" <msmith3@gmail.com>
Date: 31 Aug 2005 16:44:31 -0700
Links: << >>  << T >>  << A >>
Brad,

You mean you want to build a SERDES out of flops & muxes?

That's difficult to do well, but if you just want to serialize the data
and you can still send the clock over a separate line, then it's not a
problem.

The Clock and Data Recovery (CDR) in a SERDES is tough to do in regular
FPGA resources.

Mark


Article: 88940
Subject: Re: Spartan 3 Serdes
From: Hiding in Plain Sight <hidinginplainsight@earthlink.net>
Date: Wed, 31 Aug 2005 20:37:35 -0400
Links: << >>  << T >>  << A >>
On Wed, 31 Aug 2005 15:52:32 -0700, Brad Smallridge wrote:

> Currently I am transfering 9 bits of data from one
> Spartan 3 to another using  9 LVCMOS25 lines.
> A 30 MHz clock supplies a source clock or "data strobe"
> which I have brough into a DCM for signal alignment.
> 
> I would like to serialize this to free up some of the 9 lines
> for other uses. Some of the Xilinx App notes seem a little
> too high end.  What can I do with just flops and muxes?
> What sort of bandwidth can I get? I would like to keep
> my BRAMs free.
> 
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m

You can use LVDS do transfer data at a much higher rate. I'm running a
4 bit double data rate bus between two Spartan3s at 133MHz DDR
(266Mnibbles/second), the bus runs over a ribbon cable and uses a source
synchronous clock on each direction. You do do something similar with a
narrower bus.


Article: 88941
Subject: Re: Welcome back Mr. Knapp
From: Eric Smith <eric@brouhaha.com>
Date: 31 Aug 2005 18:00:15 -0700
Links: << >>  << T >>  << A >>
Steve Knapp of Xilinx wrote:
> However, for a variety of reasons, distributors do not like to stock
> engineering samples so they generally will show some amount of lead
> time and place the order with Xilinx.

The Xilinx Online Store doesn't seem to like to stock parts (either
production or ES).  As of August 31, all Spartan-3 parts are listed
as "out of stock" or "shipping in 3-4 weeks".

Still, I'm glad that there is an easy-to-use low-volume purchasing
option, even if I do have to wait a month.  I hope you're successful
at getting some Spartan-3e parts into the online store.

Eric

Article: 88942
Subject: Re: FPGA Development Board Wish List
From: Eric Smith <eric@brouhaha.com>
Date: 31 Aug 2005 18:07:44 -0700
Links: << >>  << T >>  << A >>
John_H wrote:
> I think it's the Texas Instruments TFP501 and TFP510 (Rx and Tx) that are
> popular TMDS choices.  These came up with similar parts using a keyword
> search on DVI on the TI website.

Sylvain Munaut wrote:
> Would you happen to know where to find theses for experimenting ?

I'm not sure about the 500 series, which have HDCP, but Digikey and Newark
seem to stock the TFP410PAP transmitter, and the TFP401APZP receiver.

Others will argue, but my general rule-of-thumb for sourcing parts for
prototypes or low-volume production is that if you can't get it from
Digikey, Mouser, or Newark, it doesn't really exist.

Eric

Article: 88943
Subject: Re: xilinx or digilent
From: Eric Smith <eric@brouhaha.com>
Date: 31 Aug 2005 18:10:03 -0700
Links: << >>  << T >>  << A >>
"CMOS" <manusha@millenniumit.com> writes:
> is there a difference in buying spartan 3 starter board through
> digilent or xilinx?

If you buy it from Xilinx you get a time-limited EDK trial with it.
I bought mine before they started including that.  :-(

If you buy it from Digilent, you can pay a little extra to get an
XC3S400 or XC3S1000 instead of the XC3S200.  (They seem to be out of
stock of the XC3S1000 version at the moment.)

Eric

Article: 88944
Subject: Re: Spartan 3 Serdes
From: "Rob" <robnstef@frontiernet.net>
Date: Thu, 01 Sep 2005 01:16:12 GMT
Links: << >>  << T >>  << A >>
I just built a SERDES interface (Cyclone) out of logic.  It is comprised of 
a PLL, DDIO (gives you the choice to sample on the falling or rising edge of 
the fast clock), shift register, and an output flop.  The key is to be 
cognizant of internal FPGA delays, that is, if you're not using an FPGA that 
has fast perimeter silicon.  Care has to be taken of where to place the 
various elements of the design.  You may have to massage the design after 
the fitter is done.  This can be a tricky task if your FPGA design is using 
alot of LE's.

My data was being serialized at 266MHz (3.76nsec); so the data can easily 
get misaligned if you're not careful.  Cyclone doesn't have any fast SERDES 
silicon so I was forced to do this with regular FPGA resources. 
Furthermore, my design wasn't doing anything much beyond derserializing data 
and sending it out in parallel form; which made it easier to control routing 
paths and prop delays.

Board trace lengths are important, too.  Any skew between the data and the 
clock could pose a problem.

Take care,
Rob


"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:11hcd60gglj0se2@corp.supernews.com...
> Currently I am transfering 9 bits of data from one
> Spartan 3 to another using  9 LVCMOS25 lines.
> A 30 MHz clock supplies a source clock or "data strobe"
> which I have brough into a DCM for signal alignment.
>
> I would like to serialize this to free up some of the 9 lines
> for other uses. Some of the Xilinx App notes seem a little
> too high end.  What can I do with just flops and muxes?
> What sort of bandwidth can I get? I would like to keep
> my BRAMs free.
>
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m
>
>
> 



Article: 88945
Subject: Re: Spartan 3 Serdes
From: "Mark" <msmith3@gmail.com>
Date: 31 Aug 2005 19:46:11 -0700
Links: << >>  << T >>  << A >>
Yes, I should have been more explicit in my answer - a single frequency
SERDES can be done if you take Rob's advice, however, you also have to
be cognizant of jitter, of error correction (how are you going to deal
with a 35MHz noise burst in the middle of your data?) etc.
If you can, I'd still advise you to use a source synchronous clock.


Article: 88946
Subject: Re: usb and xc95
From: "Marc Reinig" <nospam@nospam.com>
Date: Thu, 01 Sep 2005 02:59:17 GMT
Links: << >>  << T >>  << A >>
I've never done it in a CPLD, just FPGA's, but one of the bigger ones might 
handle it for a low/full speed device.  Don't know about a high speed 
device.

Marc Reinig
System Solutions

"iml" <nospamiml@wp.pl> wrote in message 
news:df2oa2$b7h$1@nemesis.news.tpi.pl...
>
> It's possible to implement usb core
> on xilinx xc95 family devices?



Article: 88947
Subject: FS: Lot of 60 XCV1000 FPGAs
From: Ram <r_fpga_dev@yahoo.com>
Date: Thu, 01 Sep 2005 03:42:26 GMT
Links: << >>  << T >>  << A >>
Hi.

I have a sealed, un-opened, 60-pack of XCV1000-4BG560C FPGAs for sale.  They
are in the original Xilinx packaging, seal date of 31-OCT-02.

Here is a datasheet: http://direct.xilinx.com/bvdocs/publications/ds031.pdf

I am *not* a chip broker, but an independent EE trying to recover some
losses on these.  These were purchased for a project, but the customer
screwed me on the project and gave me these as part of payment.

DigiKey lists the XCV1000-4BG560C at $1462/chip, min-order of 12, total cost
for 12 @ $17,544.00.

See here:
http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?Ref=355865&Row=532143&Site=US

Please make me an offer on the entire lot. I DO NOT want to eBay these, so
please do not low-ball me.

Please e-mail me:

r_fpga_dev@yahoo.com

Ram.











Article: 88948
Subject: Re: Spartan 3 Serdes
From: "Marc Randolph" <mrand@my-deja.com>
Date: 31 Aug 2005 21:12:11 -0700
Links: << >>  << T >>  << A >>

Mark wrote:
> Yes, I should have been more explicit in my answer - a single frequency
> SERDES can be done if you take Rob's advice, however, you also have to
> be cognizant of jitter, of error correction (how are you going to deal
> with a 35MHz noise burst in the middle of your data?) etc.
> If you can, I'd still advise you to use a source synchronous clock.

Howdy Mark,

Where would the 35 MHz noise burst in the middle of the data come from,
and why?  What do you think it would look like?

Brad, you didn't mention exactly how the clocks are fed to/between the
two FPGA's, nor how far apart the devices are.  Considering you are
talking about 9 bits x 30 MHz, it sounds like you're needing to
transfer at max, 270 Mbits/sec.  As long as your traces are nice and
short, you should be able to cut this down to a single LVCMOS25 net (or
single LVDS diff pair if you want some added security and if you have a
diff pair set up between the two devices).

You may want to compare the effort and complexity of a bit aligner in
the receiver as opposed to chewing up one more pin for a bit alignment
sync pulse.

Have fun,

   Marc


Article: 88949
Subject: Re: Spartan-3 LVDS driving TFT LCD panel..?
From: Andrew Dyer <amdyer@gmail.com>
Date: Wed, 31 Aug 2005 23:49:24 -0500
Links: << >>  << T >>  << A >>
On Wed, 31 Aug 2005 19:04:24 +0000, Mike Harrison wrote:

> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link
> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention
> recently about using the DDR registers to reduce the data rate but couldn't immediately see any
> Xilinx appnotes when I had a quick look.
>  
> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs 2.5v,
> what happens if you lie to the software about the supply - will it work to any useful degree
> (interested in lvds output only)?

Funny you should mention this - I am working on exactly this at
work right now.

It's not working right now, but the basics are in place.  clock
runs and I see data coming out of the fpga, but I think I might
be shifting bits in the wrong place.  Panel stuff is annoying in
that the data streams are organized in 7-bit chunks which means
you have to do some trickery to do shifting via the DDR registers.

The DDR trick is nice, otherwise you end up doing a fair bit
of monkeying with RLOC attributes if you want to run an s3 -4
speed grade part at 200+ Mhz.

Our board has a selectable 2.5V/3.3V bank for doing either LVTTL
or LVDS panel stuff.

I assume you know about the TTL to LVDS chips made for this from
National and others?



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