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Frank van Eijkelenburg wrote: > Does anyone have experience with running the plb bus at 125 MHz and > using the ipif interface? > > TIA, > Frank The speed of the PLB bus is highly dependent on the number of devices attached to it. I have a V2P50 -5 with a PLB SDRAM, PLB EMAC, PLB to OPB Bridge and a PLB IPIF. I have extensively floorplanned with PlanAhead and I can just barely run at 100MHz. --- Joe Samson (jsamson@) Pixel Velocity http://www.pixel-velocity.comArticle: 89901
Hi, I would like to kown if is possible to instatiates a N number of a
specific component using a struture as "for generate" or another one.
What I'm looking for is a code with a generic number of a especific
component. I want to write a peace of a repetitive text using a
structure like "for loop" or "for generate" and use the number of ' N '
as an parameter to the compiler.
Supose the signals and the component above:
...
clkin,input : std_logic_vector(N-1 DOWNTO 0);
clkout,output : std_logic_vector(N-1 DOWNTO 0);
...
component fifo
port( ckwrite,din : in std_logic;
ckread,dout : out std_logic);
end component;
...
There is a way to instantiate 'N' VHDL components using a repetitive
strutucture like this?
...
for i range 0 to N-1generate
fifo_inst(i) : fifo
port( ckwrite => clkin(i),
din => input(i),
ckread => clkout(i),
dout => output(i));
end generate;
...
Thanks
Ivan
Article: 89902ivan wrote: > Hi, I would like to kown if is possible to instatiates a N number of > a specific component using a struture as "for generate" or another > one. Umm, yeah, pretty much exactly like you've done it (snipped)! :O Regards, MarkArticle: 89903
>From its datasheet, Spartan3 DCM can double clock rate up to 334MHz, ie, CLKIN can be up to 167MHz. Hence I hope that I can produce a clock rate of 311MHz from my 155.5MHz CLKIN. The experiment result is not the case. I measure a CLK2X/8 which should be 38.88MHz, but it is actually half of that and the locked pin is not active. Then I reduce the CLKIN rate, clock doubling seems to be fine if CLK2X is less than 280MHz. This pattern repeats on several EV boards. Can anybody comment on this issue? How does this occur? Poor PCB designed, eg, power decoupling, 2-Layer PCB, poor trace, overstated specification or chip error (Revision A)!!! Good day, WanchArticle: 89904
wanch wrote: >>From its datasheet, Spartan3 DCM can double clock rate up to 334MHz, > ie, CLKIN can be up to 167MHz. Hence I hope that I can produce a clock > rate of 311MHz from my 155.5MHz CLKIN. The experiment result is not > the case. I measure a CLK2X/8 which should be 38.88MHz, but it is > actually half of that and the locked pin is not active. Then I reduce > the CLKIN rate, clock doubling seems to be fine if CLK2X is less than > 280MHz. This pattern repeats on several EV boards. > > Can anybody comment on this issue? How does this occur? Poor PCB > designed, eg, power decoupling, 2-Layer PCB, poor trace, overstated > specification or chip error (Revision A)!!! > > Good day, > Wanch > 1. You should use the DCM in High frequency mode 2. Test if you have a Silicon revision subject to the problems listed as Spartan 3 errata by XilinxArticle: 89905
Hi Ivan, as you already showed, generate does the trick of multiple instantiations of a given component. To do this N times you can specify a generic in your entity like this: entity fifo_chain generic( N : integer := 8); -- 8 as a default (not neccessary) port ..... end entity; Please have a look for the correct syntax. It is not neccessary always to edit the default in the entity. There are smarter ways. During Simulation you can change N from the configuration. Or it can be changed from the disign that instantiates the fifo_chain as a component. Maybe it is also possible to define N as a constant in a package. That could be useful if you want to create variants of a certan design. Then each variant would be syntesized with its own package and that's all to edit. Have a nice synthesis Eilert ivan schrieb: > Hi, I would like to kown if is possible to instatiates a N number of a > specific component using a struture as "for generate" or another one. > What I'm looking for is a code with a generic number of a especific > component. I want to write a peace of a repetitive text using a > structure like "for loop" or "for generate" and use the number of ' N ' > as an parameter to the compiler. > --snipArticle: 89906
Subhasri krishnan schrieb: > Hi, > I have to initialise an SDRAM with an LUT (48MB). I have the LUT in > .dat format. Is there anyway I can do this with the Xilinx ISE tool? I > can do writes continuously but I'd like to know how to access the file > in the first place. I read somewhere that I need a different IDE for > it..that too only for RAM blocks. what does that mean? > > I am new to this field so if this question has been asked before please > do point me in the right direction (I've done a good search already). > > Thanks > Hi, I see two possible solutions to your problem: 1) if the Data can be calculated (e.g. a sine-table) then the algorithm can be placed in the fpga and calculate the SDRAM contents once before the rest of the system starts. 2)Use a Flash memory (on board, or SD-Card, MMC-Card etc.) where your data is stored. Transfer this data to the SDRAM by some FPGA_logic before the rest of your system starts. It is most unlikely to put this ammount of data into a bitfile, but like Stephen Craven posted before, there is a system ACE chip that supports the second solution, so your own effort will be minimized. This chip is intended as a booting solution for operating systems (e.g. to load a linux kernel after FPGA-configuration) have a nice synthesis EilertArticle: 89907
hai,
i need to know how to display different colour bars in vga monitor
by interfacing with cpld . i need to use vhdl code for this.
Article: 89908Hi c.a.f. it looks that i cant stay away (e.g. be silent). I do own an explanation (for my last/previous posting) I know but that has to wait. AnttiArticle: 89909
"wanch" <wpora@hotmail.com> schrieb im Newsbeitrag news:1128055160.359619.244930@f14g2000cwb.googlegroups.com... > >From its datasheet, Spartan3 DCM can double clock rate up to 334MHz, > ie, CLKIN can be up to 167MHz. Hence I hope that I can produce a clock > rate of 311MHz from my 155.5MHz CLKIN. The experiment result is not > the case. I measure a CLK2X/8 which should be 38.88MHz, but it is > actually half of that and the locked pin is not active. Then I reduce > the CLKIN rate, clock doubling seems to be fine if CLK2X is less than > 280MHz. This pattern repeats on several EV boards. > > Can anybody comment on this issue? How does this occur? Poor PCB > designed, eg, power decoupling, 2-Layer PCB, poor trace, overstated > specification or chip error (Revision A)!!! > > Good day, > Wanch we can only confirm that we have never seen higher than 275MHz from DCM output in S3. that correlates with your measurements. I dont think the PCB is the issue. issue is in silicon. AnttiArticle: 89910
"peri" <periyanayaki@gmail.com> schrieb im Newsbeitrag news:1128062598.371280.136240@g49g2000cwa.googlegroups.com... > hai, > > > i need to know how to display different colour bars in vga monitor > by interfacing with cpld . i need to use vhdl code for this. > google for trenz electronics search there it is there eg there is ready project that does what you need AnttiArticle: 89911
Brandon wrote: > We typically create a new repository for different projects so that > only certain individuals have access to certain projects, since someone > could very well delete files from a head revision. We also have a > 'sandbox' repository that everyone has access to for testing and such. > > We use http. Our SVN server is installed on a dedicated linux box, > although it was originally installed on an coworker's workstation when > we first started out. I also know it's possible with http to setup a > vpn connection to a SVN server, but we've yet to convince our uptight > IT ppl that it would not be a security compromise. > I have been thinking along the same lines. For the most part, all our developers will have access to everything (we are a small group) - if someone deletes something by mistake, it can always be "undeleted" (that's part of the point of a revision control system!). I also plan to allow https access from certain home machines (saves any need for a vpn), and maybe even occasional customers for colabaration projects. Do you find that subversion works well for binary files too (obviously without differencing and merging), like object code or pcb design files? mvh., DavidArticle: 89912
Hi the standard SPI flash devices are cheap so all FPGA vendors are adding support for them, either directly in the FPGA or by using external PLD helper. Xilinx has an app note about using SPI flash (that uses an small PLD) I have tried that solution (it is implemented on some Memec boards) and well its not so nice and easy solution. lots of conversion steps required etc.. for a few days I succesfully tested a solution that is really simple. The answer is: use smallest Lattice EC device as SPI bootloader !! Lattice EC family supports SPI flash for its own configuration, to add more devices into config chain it is sufficent to wire Xilinx CCLK and DIN to SPI pins of the EC (CS tie low). then use DOS command copy /b lattice.bit+xilinx.bit board.bit and then program the serial flash using lattice provided ispVMsystem (that support spi flash indirect programming) power cycle and voila both lattice and xilinx FPGAs are happily configured from the serial flash. I am using this method on XydraXC 'high end eval board' that is developed for camera+display applications. the heeb board Xilinx design uses an PicoBlaze as I2C init machine to configure the Chrontel 7301 and Agielent mobile camera SoC. just a few minutes ago I did first time power up the board with working camera application (eg first time without the use of jtag cable). the EASINESS of the Lattice SPI approuch made me to write this post. --- I have spent days and days trouble shooting the Xilinx SPI on the memec V4 board, never got it working. AnttiArticle: 89913
"abhi" <akashya@gmail.com> schrieb im Newsbeitrag news:1128002921.558736.158800@o13g2000cwo.googlegroups.com... > Hi Group, > > I need to edit a program loaded in a CPLD.I can read a JDEC file from > the CPLD.How can I convert that file into a readable program which I > can edit? > > Thanks > assuming you have an succesful readback of non protected chip the conversion *IS* possible. if it reasonable that depends. for small GAL jed2eqn from Opal Jr (free download can be found with google) does the job For Xilinx XPLA3 we have a ready solution http://shop.openchip.org/shop/product_info.php?cPath=2_27&products_id=37 For any other devices I think there are no existing solution at the moment AnttiArticle: 89914
"Hans" <hans64@ht-lab.com> schrieb im Newsbeitrag news:QPT_e.3572$9l4.1789@newsfe4-win.ntli.net... > Hi Alan, > > I believe there is a generic Nios clone called Manik (see > http://www.niktech.com), just contact them to see if they can synthesis it > to a ProASIC. Other cores with good support (gcc/Linux) are the excellent > Leon2/3 core and the OR1200 from Opencores. If you really want 16 bits you > can look at my 8088 core > (http://www.ht-lab.com/hardware/APABoard/APABoard.html). It requires as a > minimum an APA450 and runs at about 16MHz. You can also wait until Actel > releases the ProASIC + ARM core :-) > > Hans > www.ht-lab.com Hi Hans, how NIOS is the manik? I wasnt aware that its a NIOS clone! I assume its NIOS II clone then. Hmm I guess Altera has not understood that as well. They have been not so happy about my NIOS II derivate. My understanding is/was that altera is tolerating NIOS compatible design but is trying to shoot anyone doing NIOS-II compatible ip cores. Antti PS too bad I only have APA075 board I would like to test your designArticle: 89915
"Waage" <chris@ednainc.com> schrieb im Newsbeitrag news:1127854785.586404.90630@g47g2000cwa.googlegroups.com... > I am looking at Avnet's Xilinx-4 LX Evaluation Kit. > Has anyone here worked with this board? > Is it worth the Money? Is there a better one out there with a similar > price? > > Does anyone know if you can configure the FPGA via the boards USB. > > Thanks, Chris > its worth the money: YES FPGA config over USB(on board): NO Antti PS if you can pay a little more then ML40x is better deal.Article: 89916
Welcome back Antti :-) Seems that you can't stay away from here :-)Article: 89917
Antti Lukats wrote: > Hi c.a.f. > > it looks that i cant stay away (e.g. be silent). > I do own an explanation (for my last/previous posting) I know but that has > to wait. Welcome back :) It was quieter around here... -jgArticle: 89918
Hi Altera used to make so much noise here, that I could not belive my eyes seing Stratix-II GX devices at Altera website, and no posting about Altera being the greatest at c.a.f. !!! I guess the S2-GX actualy isnt available so its a wise decision to not yell loud about it. I still wonder why the devices are listed on the web (without datasheets!) at all at this time. Sure its nice to see Altera claiming PCIe PIPE compliant serdes ! AnttiArticle: 89919
"nospam.eric@gmail.com" <nospam.eric@gmail.com> writes: > Hi, > > when using Xilinx par 7.1.03i and implementing some logic on a Xilinx > XC31000, I get a warning regarding the routing of my main clock that I > don't understand. Could someone give an explaination as well as a way > to avoid it? > > WARNING:Route - CLK Net:s_clk_120MHz > may have excessive skew because 5858 CLK pins > failed to route using a CLK template. > > Many thanks, Eric. > Somehow the software has decided that either * your clock net does not fit on a global net (have you used all of those up) * cannot use the CLK routing methods it has built-in for doing low-skew without using global resources. One way of getting this is to apply USE_LOWSKEWLINES or MAXSKEW= constraints to a net. If the SW can figure it's a clock, it's better off left to it's own devices. Either of those ideas help? Cheers, MArtin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 89920
Hi Antti, You are right, my apologies, I though you were the person behind Manik, Alan, please speak to Antti :-) Regards, Hans. www.ht-lab.com "Antti Lukats" <antti@openchip.org> wrote in message news:dhisp4$nb5$05$1@news.t-online.com... > "Hans" <hans64@ht-lab.com> schrieb im Newsbeitrag > news:QPT_e.3572$9l4.1789@newsfe4-win.ntli.net... >> Hi Alan, >> >> I believe there is a generic Nios clone called Manik (see >> http://www.niktech.com), just contact them to see if they can synthesis >> it >> to a ProASIC. Other cores with good support (gcc/Linux) are the excellent >> Leon2/3 core and the OR1200 from Opencores. If you really want 16 bits >> you >> can look at my 8088 core >> (http://www.ht-lab.com/hardware/APABoard/APABoard.html). It requires as a >> minimum an APA450 and runs at about 16MHz. You can also wait until Actel >> releases the ProASIC + ARM core :-) >> >> Hans >> www.ht-lab.com > > Hi Hans, > > how NIOS is the manik? I wasnt aware that its a NIOS clone! I assume its > NIOS II clone then. > Hmm I guess Altera has not understood that as well. > They have been not so happy about my NIOS II derivate. My understanding > is/was that altera is tolerating NIOS compatible design but is trying to > shoot anyone doing NIOS-II compatible ip cores. > > Antti > PS too bad I only have APA075 board I would like to test your design > > > >Article: 89921
Welcome back! Hadn't someone a bet running on how long you can resist? ;-) Thomas "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dhir2m$au3$03$1@news.t-online.com... > Hi c.a.f. > > it looks that i cant stay away (e.g. be silent). > I do own an explanation (for my last/previous posting) I know but that has > to wait. > > Antti > >Article: 89922
"Hans" <hans64@ht-lab.com> schrieb im Newsbeitrag news:Ll7%e.1033$0f3.187@newsfe1-win.ntli.net... > Hi Antti, > > You are right, my apologies, I though you were the person behind Manik, > Alan, please speak to Antti :-) > > Regards, > Hans. Hm I think manik is done by the c-nit author: http://web.archive.org/web/20040324042835/http://www.c-nit.net/ my personal taste, but the niktech website a really a place to go away from - when the c-nit was published in SOURCE code it could have a little interest. but the manik netlists ? no thanks never bothered checking those out all. Antti PS Altera did tell me that they are not happy 'through the flowers', I wonder if I can expect different talks now? I did comply to their wishes 100%Article: 89923
On 29 Sep 2005 08:15:37 -0700, "Stephen Craven" <scraven@vt.edu> wrote: >I know that Xilinx has a SystemACE format for tasks such as this, but >it may require you to use an embedded processor. It is impossible, >though, to convert your LUT data into a bitstream as the FPGA can't >store that much data. ..but the data could be combined into whatever storage device is supplying the FPGA bitstream, then accessed by the FPGA once configured. SystemAce or parallel flash would seem appropriate for this amount of data.Article: 89924
A slightly nicer way is to pass arrays around...
My personal favourite
the entity has something like ....
generic
max_chan_g: integer := 1 -- you can override this
then the ports
data_in: std_logic_vector(max_chan_g-1 downto 0)
then in the architecture
data_ff: for i in data_i'range generate
-- some code
end generate;
this way you get one reference.. and it cascades nicely and automatically
expands and contracts as required.
Normally I will have a
constant max_chan_c: integer := 4;
in a header file somewhere so when you place the component in a VHDL file
you simply put
max_chan_g => max_chan_c
in the generic section.
This method will allow portability without having to have allot of headers
Simon
"backhus" <nix@nirgends.xyz> wrote in message
news:dhik2p$jgo$1@hermes1.rz.hs-bremen.de...
> Hi Ivan,
> as you already showed, generate does the trick of multiple
> instantiations of a given component.
>
> To do this N times you can specify a generic in your entity like this:
>
> entity fifo_chain
> generic( N : integer := 8); -- 8 as a default (not neccessary)
> port .....
> end entity;
> Please have a look for the correct syntax.
>
> It is not neccessary always to edit the default in the entity. There are
> smarter ways.
> During Simulation you can change N from the configuration.
> Or it can be changed from the disign that instantiates the fifo_chain as
> a component.
> Maybe it is also possible to define N as a constant in a package. That
> could be useful if you want to create variants of a certan design. Then
> each variant would be syntesized with its own package and that's all to
> edit.
>
>
> Have a nice synthesis
> Eilert
>
>
> ivan schrieb:
> > Hi, I would like to kown if is possible to instatiates a N number of a
> > specific component using a struture as "for generate" or another one.
> > What I'm looking for is a code with a generic number of a especific
> > component. I want to write a peace of a repetitive text using a
> > structure like "for loop" or "for generate" and use the number of ' N '
> > as an parameter to the compiler.
> >
> --snip
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