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I believe that fe_shell is some synthesis scripting language for FPGA Express. Since FPGA Express does not come bundled with ISE Foundation anymore, I don't think that is something that you want to use. Xilinx Synthesis Tool (XST), which comes bundled with Webpack, has a method that allows command line invocation. Type xst -help from a command line prompt for more information. -NewmanArticle: 90251
Remis Norvilis wrote: > I wonder if there is a posibility to do Xilinx fpga synthesis and > implementation from command line on WindowsXP platform to speed up the > process. > Xilinx web site mentioned something, that it's only availabe for CPLDs. > XESS have an app note on how to use Make file to script and automate build > process. It needs fe_shell utility, but I don't think it comes with WebPack > edition. We have a more recent document that shows how to use makefiles with WebPACK or ISE. It does not need fe_shell. You can see it here: http://www.xess.com/appnotes/makefile.htmlArticle: 90252
"Symon" <symon_brewer@hotmail.com> wrote in message
news:43464b2d$0$49020$14726298@news.sunsite.dk...
> "Marco" <marcotoschi@nospam.it> wrote in message
> news:di5hbd$i0i$1@news.ngi.it...
>>
>>
>> Masterclock has a high fanout, about 100.
>> I have replicated 2 times the clock pulse at 1MHz and the state machines
>> to verify if it could low the fanout.
>
> Why do you want to lower the fanout? Have you connected the clock pulse at
> 1MHz to the clock input of any FFs? If you have, this is your mistake. It
> should only connect to the CE pins. The clock pins of *ALL* your FFs
> should connect to the 50MHz masterclock.
>
> Cheers, Syms.
>
Here the code:
clk_low_pulse is the pulse of freq. 1MHz and goes high for 20ns.
RX_REGISTER_SYNC_PROC: process ( clk_low_pulse, reset ) is
begin
if ( reset = '1' ) then
rx_state <= rx_state_1;
elsif ( clk_low_pulse'event and clk_low_pulse = '0') then
rx_state <= rx_next_state;
end if;
end process;
RX_REGISTER_OUTPUT_DECODE: process ( rx_state, clk_low_pulse ) is
begin
case ( rx_state ) is
when rx_state_1 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_2 =>
Slave_Select <= '1';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_3 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_4 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_5 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_6 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_7 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_8 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '0';
acq_ack <= '0';
when rx_state_9 =>
Slave_Select <= '0';
rx_shift_enable <= '1';
Rx_Status_En <= '1';
acq_ack <= '0';
when rx_state_10 =>
Slave_Select <= '0';
rx_shift_enable <= '0';
Rx_Status_En <= '1';
acq_ack <= clk_low_pulse;
when others =>
null;
end case;
end process;
RX_REGISTER_NEXT_STATE_DECODE: process ( rx_state, Rx_State_Machine,
rx_counter_tresh ) is
begin
rx_next_state <= rx_state; --default is to stay in current state
case ( rx_state ) is
when rx_state_1 =>
if ( Rx_State_Machine = '1' ) then
rx_next_state <= rx_state_2;
else
rx_next_state <= rx_state_1;
end if;
when rx_state_2 =>
rx_next_state <= rx_state_3;
when rx_state_3 =>
rx_next_state <= rx_state_4;
when rx_state_4 =>
rx_next_state <= rx_state_5;
when rx_state_5 =>
rx_next_state <= rx_state_6;
when rx_state_6 =>
rx_next_state <= rx_state_7;
when rx_state_7 =>
rx_next_state <= rx_state_8;
when rx_state_8 =>
rx_next_state <= rx_state_9;
when rx_state_9 =>
if ( rx_counter_tresh = '1' ) then
rx_next_state <= rx_state_10;
else
rx_next_state <= rx_state_9;
end if;
when rx_state_10 =>
rx_next_state <= rx_state_1;
when others =>
rx_next_state <= rx_state_1;
end case;
end process;
Article: 90253And then Newman wrote: > I believe that fe_shell is some synthesis scripting language for FPGA > Express. Since FPGA Express does not come bundled with ISE Foundation > anymore, I don't think that is something that you want to use. Xilinx > Synthesis Tool (XST), which comes bundled with Webpack, has a method > that allows command line invocation. Type xst -help from a command > line prompt for more information. > > -Newman Thanks for replys. Those of you that used command line built, is there a build speed improvement and how significant?Article: 90254
"Marco" <marcotoschi@nospam.it> wrote in message
news:di5pfo$kkm$1@news.ngi.it...
>
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:43464b2d$0$49020$14726298@news.sunsite.dk...
>> "Marco" <marcotoschi@nospam.it> wrote in message
>> news:di5hbd$i0i$1@news.ngi.it...
>>>
>>>
>>> Masterclock has a high fanout, about 100.
>>> I have replicated 2 times the clock pulse at 1MHz and the state machines
>>> to verify if it could low the fanout.
>>
>> Why do you want to lower the fanout? Have you connected the clock pulse
>> at 1MHz to the clock input of any FFs? If you have, this is your mistake.
>> It should only connect to the CE pins. The clock pins of *ALL* your FFs
>> should connect to the 50MHz masterclock.
>>
>> Cheers, Syms.
>>
>
> Here the code:
> clk_low_pulse is the pulse of freq. 1MHz and goes high for 20ns.
>
>
> RX_REGISTER_SYNC_PROC: process ( clk_low_pulse, reset ) is
> begin
>
> if ( reset = '1' ) then
> rx_state <= rx_state_1;
> elsif ( clk_low_pulse'event and clk_low_pulse = '0') then
> rx_state <= rx_next_state;
> end if;
>
> end process;
>
OK, now we're getting somewhere! So, you're using 'clk_low_pulse' as a
clock. This is bad. Do this instead:-
RX_REGISTER_SYNC_PROC: process ( clk_50MHz, reset ) is
begin
if ( reset = '1' ) then
rx_state <= rx_state_1;
elsif ( clk_50MHz'event and clk_50MHz= '1') then --NB rising edge!!
if clk_low_pulse = '1' then
rx_state <= rx_next_state;
end if;
end if;
end process;
Does that make it clear? Try drawing a timing diagram of that. You'll see
that the FFs are all clocked by the 50MHz masterclock. The signal
'clk_low_pulse' is used as a clock enable, so its delay and skew don't
matter, provided you meet the set up time of the FFs.
Cheers, Syms.
p.s. Instead of
elsif ( clk_50MHz'event and clk_50MHz= '1') then
use
elsif rising_edge(clk_50MHz) then
It's better for some reason I can't remember but you can find by Googling!
Article: 90255Thanks for the input everyone.The "101 device" problem has been fixed. It turned out that the voltage on the download cable is too low. should be 2.8v and above, the design was only 2.5v. Now it is 3.3v. But there is the error of "impact 583:the idcode read from device does not match idcode in bsdl file". We think that the TDO's voltage is too low (3.3v), while the TDO requires TTL > 4v. We are going to try this tomorrow. But can anyone here think of another reason? ThanksArticle: 90256
"Michael Chan" <mchan@itee.uq.edu.au> schrieb im Newsbeitrag news:newscache$tz0zni$bj6$1@lbox.itee.uq.edu.au... >I learnt at uni that two flip-flops is generally sufficient for >synchronising an asynchronous signal. But what if the phase of the >sampled signal isn't uniformly random? In particular, how would I deal >with synchronising two different clock domains where one clock is the >reference of a PLL, and the second clock is the output of that PLL, say >8 times faster. Also, the frequency of the input clock, and >consequently the output clock is FM modulated - although the frequency >variation is slight. The frequency of the fast clock is on the order >of GHz. I figure that since the two clocks are related, the chance of >metastability is drastically higher. I guess you are right. When I construct the case that a Fo FF is sampling the Fref and the actual phase is hitting the sampling window permanently giving metastable behaviour you get a analog circuit. You should investigate on the metastable behaviour of the FF's you are going to use. In CMOS a FF is made of transmission gates and a high gain +1 feedback amplifier (two inverters). http://www.play-hookey.com/digital/cmos_d_flip-flop.html Usually they don't stay long in a metastable case, but I never checked this myself. You should also be able to google for some coarse numbers. 74' TTL Technologies were reported to eventually stay very long in the metastable state. CMOS is reported not to stay long in such a metastable state. So if you are sure that the first FF can't stay longer in metastable state than Tperiod-Tsu, you are fine. In a CMOS FF you could avoid the hypothetical persisting metastable state by constructing the feedback (of the output stage) with a schmitt-trigger. Such a FF should never - by construction - stay in the metastable state, only the CK->Q time may be affected. But the construction of modern CMOS FF's maybe already giving a similar effect. The (analog) key is here the loop gain / phase of the two inverters in the output stage. Raymund HofmannArticle: 90257
Thank you, but I already tried. Now I found a way to solve the problem. I just created a new project and reimported my vhdl and sch files. The only thing I had to do is assign the pins again in Designer but everything was then ok. It took less time than continue to look after the mistake! Thank you for your help! See you next time on this group, MarieArticle: 90258
Recheck to see if the "Correct" BSDL file is associated with the device in question. I've seen after impact gets confused, one has to assign the BSDL file to the part, exit impact and restart. Consult Xilinx answer records for more information. -NewmanArticle: 90259
Trouble Solved! Many and many thanks! MarcoArticle: 90260
alan@nishioka.com wrote: > Eli Hughes wrote: > >>Has anyone actually gotten the master functionality in the PLB IPIF to >>work correctly? I have been making slave peripherals without a problem. > > > > I have not had much luck with the Xilinx tools for creating > peripherals. I tried and failed to use ipif to create a plb master. > > I would just read > http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/8BA965C773B2E0ED87256AB20082CC9F/$file/64bitPlbBus.pdf > (search for 64bitplbbus.pdf on www.ibm.com) > and write it by hand. This worked great for me. > > Alan Nishioka > Did you have to do anything special such that the module is detected in platform studio? I am assumming that I can just use all the signal names in the top-level module that the xilinx module provides when I use the wizard and PLatform studio will hook everything up. -EliArticle: 90261
Kiran,
please send me some design files that you can share, and I'll take a look
Aurash
kkumar@northernpower.com wrote:
>Hi,
>We are using Xilinx Spartan2E in our platform and so far functioning of
>every logical cores was looking good. Today, I saw some weird behaviour
>after addng additional logic, all of sudden I was missing some signals
>coming out of FPGA and some signals looks different. This additional
>logic does not interfer with the exisitng logic cores.
>I am reaching upper limit of FPGA resource but still I can fit in all
>the logic cores.
>
>So my question is, by utilizing the FPGA resource around 90%, does the
>behaviour of FPGA logics becomes unpredictible ?
>
>Any pointers or suggestions in this regard is much appreciated.
>
>Thank you in advance.
>
>-Kiran
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 90262d...@xess.com wrote: > We have a more recent document that shows how to use makefiles with > WebPACK or ISE. It does not need fe_shell. You can see it here: > > http://www.xess.com/appnotes/makefile.html Maybe that works with ISE 6.x with "projectfile.prj" as ascii file... any suggest to make it to run with ISE 7.x with "projectfile.ise" as binary unknown (for me) format file ? SandroArticle: 90263
"Sandro" <sdroamt@netscape.net> schrieb im Newsbeitrag news:1128690891.332598.134580@g14g2000cwa.googlegroups.com... > d...@xess.com wrote: > > We have a more recent document that shows how to use makefiles with > > WebPACK or ISE. It does not need fe_shell. You can see it here: > > > > http://www.xess.com/appnotes/makefile.html > > Maybe that works with ISE 6.x with "projectfile.prj" as ascii file... > > any suggest to make it to run with ISE 7.x with "projectfile.ise" as > binary unknown (for me) format file ? > > Sandro > NONO the .PRJ files are stil plain ascii, no problems with them at all, in 7.1 the .NPL files are no .ISE and binary there should be no problems running ise tools from commandline (but i havent used webpack for looooong time) anttiArticle: 90264
>Actually, ignore the 8 times multiplication Still synchronoues and sovable by static timing, as long as the jitter is not greater as the clock period. However, there are several methods to pass information between asynchroneous domains, which will also apply here, assuming not uniformly distributed asynchroneus domains: *dual ported rams *using metastability hardened ffs *trying to delay into a safe(r) region (if it is not uniformly distributed, there are safer regions and unsafer regions) - as I proposed earlier. Hubble.Article: 90265
On Fri, 07 Oct 2005 14:02:27 +0100, Aurelian Lazarut <aurash@xilinx.com> wrote: >Kiran, >please send me some design files that you can share, and I'll take a look > >Aurash > >kkumar@northernpower.com wrote: > >>Hi, >>We are using Xilinx Spartan2E in our platform and so far functioning of >>every logical cores was looking good. Today, I saw some weird behaviour >>after addng additional logic, all of sudden I was missing some signals >>coming out of FPGA and some signals looks different. This additional >>logic does not interfer with the exisitng logic cores. >>I am reaching upper limit of FPGA resource but still I can fit in all >>the logic cores. >> >>So my question is, by utilizing the FPGA resource around 90%, does the >>behaviour of FPGA logics becomes unpredictible ? >> >>Any pointers or suggestions in this regard is much appreciated. >> >>Thank you in advance. >> >>-Kiran The addition of the new logic may have caused increased routing delays.Article: 90266
jjohnson@cs.ucf.edu wrote: > (Sorry, I can't use the on-chip deserializers; > they max out at 10 bits, and I need 12.) How about 6-bit with additional user logic at 1/6 the input frequency to get to 12 bits? Kolja SulimmaArticle: 90267
Hello, Iam having trouble installing ISE 7.1i on brand new Dell PC. The PC just reboots midway through the installation. The Dell PC came with Windows XP Pro with Service Pack 2. Tried on 2 Dell PC's both reboot during installation. No similar issues are reported on Xilinx support site or on this group. Has anyone had similar experience? Iam trying to figure out if I should bug Xilinx or Dell ? Thanks BrijeshArticle: 90268
"Raymund Hofmann" <filter002@desinformation.de> wrote in message news:di5qj7$pvg$1@online.de... > > CMOS is reported not to stay long in such a metastable state. > So if you are sure that the first FF can't stay longer in metastable state > than Tperiod-Tsu, you are fine. > The whole point is that you can never be sure how long the first FF will stay metastable. The maximum time it can take to resolve is infinite. > > In a CMOS FF you could avoid the hypothetical persisting metastable state > by constructing the feedback (of the output stage) with a schmitt-trigger. > This doesn't help fix the problem. > > Such a FF should never - by construction - stay in the metastable state, > only the CK->Q time may be affected. > This is why the problem isn't fixed by the Schmitt idea. The CK->Q time can be anything up to infinite. So, Q can be changing just as the next stage of the circuit tries to sample it. A FF in a metastable state doesn't necessarily have to have a funny output voltage. It's in a state where it hasn't made up its mind what its output should be. > > But the construction of modern CMOS FF's maybe already giving a similar > effect. > The (analog) key is here the loop gain / phase of the two inverters in the > output stage. > > Raymund Hofmann May I suggest you take a look at this? http://www.fpga-faq.org/FAQ_Pages/0017_Tell_me_about_metastables.htm Cheers, Syms.Article: 90269
Don't know if it fits here or not, but since I'm using a fpga I guess it does. I've got a spartan-3 starter board and got tired of the 8color output from the standard vga connector. So I hooked up som E12 series resistors (570, 1200 and 2200) to get 9bits and 512 possible colors (not evenly spread, but cool anyway). It works pretty ok except for some strange distortions in the images. The brighter colors fades out beyond the image, leaving a kind of motion blur (although it's not moving). And having several white pixels in a row gets the first pixel white and the rest fades to grey. Also at the left hand side of the image all of the colors are darker than on the right hand side. As you might have guessed, I'm a newbie when it comes to this hw stuff. Bad image quality, but I think you can see what I mean from this shot: http://www.akatora.se/shmupstick/spr128x128.jpg Any help appreciated! ((miceArticle: 90270
Solved. Sorry for taking your time (becoming a habit...) Cut a monitor cable, forgot about grounding the shielding. Now it's stable. Looks pretty cool, doesn't it? :) http://www.akatora.se/shmupstick/spr128x128_2.jpg Cheers! ((miceArticle: 90271
To create a module in platform studio, you have to create a directory structure in the project subdirectory pcores/ This includes .pao, .mpd, files in data/ that describe connections. I copied and modified this from a core that had similar features to what I wanted. I was never able to get the wizard to do what I wanted, so I don't have much experience with it. Alan NishiokaArticle: 90272
Thanks Antti, for both replies. We've already got a board built and half-running with V4LX100-11's (ordered early, paid big bucks, got engineering samples). We had the design running at 360MHz in a V2Pro a few months ago (DCM, source-synchronous mode, no IDELAY, plus a few LOC constraints), but I'm still not sure I got the timing constraints right. SynplifyPro doesn't seem to support hold-time constraints, and Xilinx's UCF syntax boggles my mind. UCF doesn't seem to support multiple constraints on a port (like Synopsys does with set_input_delay -max|-min -add_delay); UCF appears to overwrite them. (Last one wins, plus some other priority rules they have...) The 500 MHz was slightly rounded up for clarity in illustration. We need 360MHz for the current 12-bit A/D converters, and 420/480 if we move up to 14/16-bit converters. We hope to put this in an ASIC someday, at which point I'll need complete timing constraints; it would be great if everybody supported the same constraint format (like Synopsys .SDC), or if I could find an English <-> UCF translator... Thanks again, mjArticle: 90273
Hello
Has anyone here had experience with interrupt latency in a PowerPC block
in a VirtexII Pro? I did a simple experiment where I setup a PowerPC
core where the critical interrupt input is always raised (just tied it
to net_vcc in the .mhs file). I then registered a very simple interrupt
handler:
void MyIrqA(void * arg)
{
i = MYIP; // read a generic register on the PLB Bus
}
with built Xilinx Functions:
XExc_RegisterHandler(XEXC_ID_CRITICAL_INT, (XExceptionHandler)MyIrqA,
(void *)0);
and then enabled the interrupt with:
XExc_mEnableExceptions(XEXC_CRITICAL);
I then monitor a bus read signal for my generic register to see how
often it occurrs. The PLB bus and PowerPC is being clocked at 100MHz on
a Digilent VirtexII Pro development board.
To my surprise, there is almost 10uS between reads! I know this isn't a
PLB bus issue, I can do multiple reads in the interrupt route and the
read pulses are within a few bus cycles of each other.
Is there anythign I can do to help this? What in the world is Xilinx
doing in their BSP to save context that takes 10uS with a 100MHz clock
period?
-Eli Hughes
Article: 90274T. Irmen <tirmen@gmx.net_NO_SPAM> wrote: > Hi, Hi! > currently we install the rh ws 3.0 into a separate directory ; chroot > to it and start the software, that works In general (32bit), ISE, XPS and so on work out of the box under Debian. I've tested it with Sarge, testing and unstable. There is no need for installing it under RedHat and later copying the files. Absolutely not. Make sure to have libXm.so.3 installed (apt-get install libmotif3). Debian comes with libcurl3, (iirc) the installation needs libcurl2. This is no problem, even without root privileges you can do: $ mkdir /tmp/mylibs $ ln -s /usr/lib/libcurl.so.3 /tmp/mylibs/libcurl.so.2 $ export LD_LIBRARY_PATH=/tmp/mylibs/:$LD_LIBRARY_PATH $ # run normal Xilinx setup routine If you have Acrobat Reader 7.0 for Unix, then life is even easier, just do: $ export LD_LIBRARY_PATH=/usr/lib/Adobe/Acrobat7.0/Reader/intellinux/lib $ # run normal Xiling setup routine as acroread comes with libcurl.so.2. (the path to libcurl.so.2 on your acroread installation my vary) I guess this little "trick" has to be done every time you install/upgrade the Xilinx tools. (Note: for cable stuff, the following URL might be interesting:) <http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm> ( Note: if you have root privileges you can get rid of LD_LIBRARY_PATH by doing "ln -s /usr/lib/libcurl.so.3 /usr/lib/libcurl.so.2 && ldconfig". (I recommend against this as you shouldn't interfear with the package management in /usr/lib, use /usr/local/lib/ instead (and add this path to /etc/ld.so.conf before running ldconfig)) In any way, the ABI of libcurl.so.3 may change in the future (Debian is changing the distribution compiler), so I suggest getting a real libcurl.so.2 instead (i.e.: use the one which comes with acroread7) ) > I think something with the X libraries doesn't work with current > amd 64 port of debian, ise produces a segmentation fault at startup. > does anyone have some ideas / suggestions? I suggest that you try like running OpenOffice under amd64: use a debian-32bit-chroot (not a RedHat one), i.e. install ia32-libs, dchroot and so on. For detailed instructions, see "The Debian GNU/Linux AMD64 HOW-TO". > BTW: I know that Xilinx says:RH WS3.0 is the ONLY supported distribution. > System is dual opteron (2600MHz), 8GB mem, SATA etc... I'd like to use > debian for a lot of reasons.... I agree. At least they don't check any RH-specific stuff at startup. If I were Xilinx, I would only support Debian as the most generic distribution (no proprietary quirks at all, FHS-compliant) and let other distributors adapt to it. I'd also remove all the cable-stuff from the installer as this is highly kernel-specific and I guess almost everyone not using RHWS3.0 has to compile the modules on his own. And by the way: X-cut'n'paste doesn't work inside the XPS-editor, so I use an external one. Fonts for busnames are unreadable small in the Add/Edit-cores-dialog. I think there is still a lot to be done for seamless integration under Linux. -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Die Lage war noch nie so ernst wie immer.
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