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Why do you need to know? In an FPGA, the LUTs and flip-flops are tiny. Most of the area is used for interconnects (routing) and their configuration storage. But without routing the LUTs are worthless... So, what are you really asking? Peter Alfke, XilinxApplicationsArticle: 90376
Hi...
I am using an 32MB SDRAM Unbuffered Module of Micron in my
project.It has 168 pins.
First i got a module having 18 Chips on it.So it was having one VDD
and one VSS for each Chip (So a total of 36 Pins).
So to Reduce number of Power and Ground pins i got another
SDRAM module having only Four Chips.But still it also have 36 Pins.
Confusion
Now i m a little Confused about that while
these pins (of VSS and VDD) are by internally connected in SDRAM
Module or i have to connect each one of them seperatly with VSS and
VDD.
[b:9287e51c88][color=brown:9287e51c88]Confusion Counter parts
[/color:9287e51c88] [/b:9287e51c88]It looks that as pins of are
seperatly present so i have to connect them seperatly in my
PCB...........On the other hand it looks that,,,as Pins are
internally connected in SDRAM module so to apply VDD and VSS on any
two pins is sufficient.... :x .....what you think :?
[color=brown:9287e51c88][b:9287e51c88]Why to Reduce Pins
[/b:9287e51c88] [/color:9287e51c88]
I want to Reduce Pins as i have to make PCB for its
Banq(Slot).
And to make my PCB simple and to make it possible on Single Layer (To
Reduce Cost :) ).and also its not possble to do it on a single sided
PCB with too much pins .
[b:9287e51c88][color=darkred:9287e51c88]
Required[/color:9287e51c88][/b:9287e51c88]
1-Plz Suggest about confusion using your experience , knowledge, logic
and Observation.
2-Plz suggest some other solution...
Thanks
Article: 90377hi all dears, i am new to altera stratix fpgas i want to know more about plls in the altera FPGA and how can i produce a clock for my program with plls? thanks byeArticle: 90378
Even if your design runs very slow, the SDRAM module has high current demands. Since all the VSS and VDD pins are connected, you still need to connect all the pins on the module. Would you consider it safe to ride in a hot-air balloon where the basket is attached by one small rope? It may be all that's "needed" but things will get nasty at the first stress on that rope. The many VSS and VDD pins are primarily 1) to avoid ground bounce where the large changes in current create a voltage differential between the ground on your board and the ground on your module, and 2) to keep the return currents close to the signals in order to keep crosstalk low - if you have poor return current paths, your signals will crosstalk significantly and your clocks will no longer be monotonic. Don't try for a single sided board. If you're working with pre-manufactured SDRAM modules that aren't designed for extremely slow slew rates, spend the money and do a *4-layer* board. If you want to design the SDRAMs onto your own board, you have a chance at operation with RIGOROUS design attention to reduce crosstalk and ground bounce effects. It sounds like you don't understand the problems you face so it would take a great deal of learning to start to apply that rigor. A 4 layer board that connects to a solid ground plane and (mostly) solid power planes will allow a reasonable design without the world falling apart. It's nice to have a board where all the signals are connected but it's even nicer if the board will work when clocked. Bite the bullet. Spend the money. - John_H (posting from google at the moment)Article: 90379
Stephan, There is something called a multi-cycle constraint that should help. Below is a link to help you get started in your search. http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=9416 -NewmanArticle: 90380
Our Virtex-4 FX20 10C-ES1 devices also exhibit this problem. We used ChipScope to look at the PLB bus and like one of the other posts the address on the bus after things go awry is 0x????0800, the upper 16-bits can vary a little. Our supplier has been fairly helpful since we also noticed the problem on Virtex-4 evaluation board we purchased from them. Xilinx was dismissive until recently. It has been suggested that we set the C_APU_CONTROL parameter in the MHS file to 0b0000_0000_0000_0001. I've tried it on one bad board and the problem has not happened since. It would be interesting to see if others have the same result.Article: 90381
Hi, I've been working with Xilinx CPLDs (mostly 95108) for quite some time now, and as my designs became more complex, the CPLDs became too small for me. Due to a research paper assignment, I've been working with a Spartan3 development board since July and I'm considering using Spartans for my home-made designs. The one problem is that the development board I've worked with so far has no startup ROM, so I have to re-program the FPGA after every power-up. I couldn't find any guides on that topic on the net - could someone please give me a few hints on how to implement a startup ROM (like sample circuits or chip types)? Thanks in advance, Immo BirnbaumArticle: 90382
Immo Birnbaum wrote: >Hi, > >I've been working with Xilinx CPLDs (mostly 95108) for quite some time >now, and as my designs became more complex, the CPLDs became too small >for me. Due to a research paper assignment, I've been working with a >Spartan3 development board since July and I'm considering using >Spartans for my home-made designs. The one problem is that the >development board I've worked with so far has no startup ROM, so I >have to re-program the FPGA after every power-up. I couldn't find any >guides on that topic on the net - could someone please give me a few >hints on how to implement a startup ROM (like sample circuits or chip >types)? > > It's all in the Xilinx documents for the Spartan chips. You can connect their own SPROM with a couple pull-up resistors and grounds on the M(x) config pins, and it takes it from there. I haven't used Spartan 3, but have done a lot with 5 V Spartan chips. I've been looking at how to use other maker's SPROMs that are a lot cheaper than Xilinx's SPROMS for the Spartan 2. One problem is some other maker's SPROMs are slower than the config clock provided by the Spartan 2. JonArticle: 90383
DerekSimmons@FrontierNet.net wrote: >He hasn't received a reply but he did find an answer to his question. I >was wondering what other people could recommend. > > If you don't need very fast response (most 12 V logic is not high speed, anyway) then opto-couplers can be a good solution, as long as you can get a couple mA from the 12 V logic. I have a commercial product using 5 V Spartan FPGAs where I use the output of an H11A817D optocoupler to drive the Spartan input, using the Spartan's internal pull-up as the load resistor. This should work fine on 3.3 V FPGAs, too. The same optocoupler can be used as an output, by having the FPGA output pull current through the opto's LED. JonArticle: 90384
use Xilinx platform flash proms. They can be prograammed by the impact SW. See http://direct.xilinx.com/bvdocs/publications/ds123.pdf Another option is to wait for Spartan 3E chips to become availlable. Then you can use normal SPI flash proms from Atmel,SSt,ST or others. They are cheap, e.g a M25P80 with 8Mbits from ST is about 2,5-4$ http://www.mouser.com/index.cfm?handler=displayproduct&lstdispproductid=699110 Try yourself at www.findchips.com I don't know if these SPI flashes are supported by xilinx impact. However, IMHO the Lattice tools should do that. MIKEArticle: 90385
Hi, I need to implement an 8x8 circular shifter module where I have 8 input ports (each 4 bits) that needs to be connected to 8 output ports (each 4 bits) shifted by shift times. I have an input port that tells the shift value. e.g: switch_block: for k in 0 to 7 generate s<= (k+shift) when (k+shift)< 7 else (k+shift)-7; switch_out(k+shift)<=switch_in(k); end generate switch_block; is there anyone who can tell me what is the best way of implementing this in FPGA. The obvious way is a shift register but in my design I need to perform this operation in one clk cycle. I will appreciate any suggestions, thoughts, or comments. Thanks,Article: 90386
The easiest way to do this is to use a Platform flash device such as the XCF01. They connect to the JTAG scan chain, so you will be able to program the bitstream via impact with the Xilinx download cable (such as the Parrallel cable IV). Upon system power-up, they will load a bitstream into the Spartan chip and will make your system stand-alone. Goto the Xilinx Homepage and click on configuration solutions to get more info. Don't use any of the older PROMs or try to hack your own configuration solution with an external microprocessor. For what you are doing, these devices are perfect. Just make the right connections to the FPGA and your done. The only downside is that it seems that all Xilinx chips are in short supply. I know Avnet is a distributor but it seemed like they didn't have any stock (lead time of 6weeks). -Eli Immo Birnbaum wrote: > Hi, > > I've been working with Xilinx CPLDs (mostly 95108) for quite some time > now, and as my designs became more complex, the CPLDs became too small > for me. Due to a research paper assignment, I've been working with a > Spartan3 development board since July and I'm considering using > Spartans for my home-made designs. The one problem is that the > development board I've worked with so far has no startup ROM, so I > have to re-program the FPGA after every power-up. I couldn't find any > guides on that topic on the net - could someone please give me a few > hints on how to implement a startup ROM (like sample circuits or chip > types)? > > Thanks in advance, > Immo Birnbaum >Article: 90387
"Enver" <ecavus@gmail.com> wrote in message news:1129061312.313084.204610@g47g2000cwa.googlegroups.com... > Hi, > > I need to implement an 8x8 circular shifter module where I have 8 input > ports (each 4 bits) that needs to be connected to 8 output ports (each > 4 bits) shifted by shift times. I have an input port that tells the > shift value. > > e.g: > switch_block: for k in 0 to 7 generate > s<= (k+shift) when (k+shift)< 7 else (k+shift)-7; > switch_out(k+shift)<=switch_in(k); > end generate switch_block; > > is there anyone who can tell me what is the best way of implementing > this in FPGA. The obvious way is a shift register but in my design I > need to perform this operation in one clk cycle. I will appreciate any > suggestions, thoughts, or comments. > > Thanks, > Use 8 X (8 channel 4 bit muxes) and drive the 3 bit addresses via a set of adders each offset by one, ignoring overflows. By inputting the number of shifts to the front end add, the correct shifts are applied to the remaining. Assuming your clock rate is <200MHz you should piss it in 1 clock cycle. SlurpArticle: 90388
Please open a case with the Xilinx hotline if you encounter an intermittent problem while booting the PowerPC after initial power-on in Virtex-4 FX FPGAs. The hotline engineers will assist you to identify the problem and once isolated provide you with an appropriate design parameter. - PeterArticle: 90389
Sandro wrote: > Sylvain Munaut wrote: > >>I'm looking for some example on how to use the USER1,2 functions in a >>spartan 3 (examples on virtex2/4 or others are welcomed). I know how to >>instanciate the component but that's about it. I searched xilinx site >>but didn't found any real example ... >>... > > > I think this TechXclusive can help You: > > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=krs_blockRAM > > Regards > Sandro > Yes, great ! Thank you. SylvainArticle: 90390
Because I have to estimate the area of different Functional Units, using the same parameter. For example,if I can choose from a FU that uses two 2:1 multiplexer and four FF and another FU that uses four 2:1 multiplexer and two FF, I'd like to prefer FU that occupies less area. Sry for the english ThanksArticle: 90391
Hi all, I'd like ask you for any hint in user library creation in Xilinx ISE 7.0 (XST). I want to build my own library but I am not able to compile it and include it in my design. The error message appears: Compiling vhdl file "D:/VHDL/Test/test.vhd" in Library my_lib. ERROR:HDLParsers:3016 - "D:/VHDL/Test/test.vhd" Library unit counter required for unit counter does not exist in library my_lib. ERROR:HDLParsers:3014 - "D:/VHDL/Test/test.vhd" Line 31. Library unit counter is not available in library my_lib. 1, I created modul (entity and architecture) of simple counter in d:\my_lib\counter.vhd 2, I created package (contents only component counter declaration) in d:\my_lib\my_package.vhd 3, I Mapped user library file in Synthesize - XST/Synthesis Options/HDL ini file. (Content of associated file points into library directory - my_lib=D:\my_lib). But I guess this link should be to compiled library, where is *.vho but I dont know how to compile library in ISE (XST). Any advice? 3, I created a test.vhd because I don't know other way how to compile before mentioned library files in ISE. in test.vhd is : library my_lib; use my_lib.my_package.all Regards XIPNArticle: 90392
Claudio wrote: > Because I have to estimate the area of different Functional Units, > using the same parameter. > For example,if I can choose from a FU that uses two 2:1 multiplexer and > four FF and another FU that uses four 2:1 multiplexer and two FF, I'd > like to prefer FU that occupies less area. Not sure what you mean by "using the same parameter". Usually with FPGAs you want to estimate a designs by: LUTS FFs RAM multipliers, PLLs, etc. Having a single scalar number (like gates) to measure how much of the FPGA a functional unit consumes is a bad idea. It's best to think of functional unit size as a vector such as: (LUTs, FFs, blockRAM, multipliers) You will run out of one resource before the others, depending on your design. You will typically run out of LUTs or RAM first, and FF's last. So in your example, the 2-LUT, 4-FF implementation is probably best. -JeffArticle: 90393
In article <62vnk1p4jk444qpdebh2gnjdq26r9fkass@4ax.com>, Immo Birnbaum <Immo.Birnbaum@t-online.de> wrote: >Hi, > >I've been working with Xilinx CPLDs (mostly 95108) for quite some time >now, and as my designs became more complex, the CPLDs became too small >for me. Due to a research paper assignment, I've been working with a >Spartan3 development board since July and I'm considering using >Spartans for my home-made designs. The one problem is that the >development board I've worked with so far has no startup ROM, so I >have to re-program the FPGA after every power-up. I couldn't find any >guides on that topic on the net - could someone please give me a few >hints on how to implement a startup ROM (like sample circuits or chip >types)? The model I've seen is to have a small CPLD connected to a standard flash memory (the board in front of me has a 9536 CPLD and an E28F320 Intel flash device); the CPLD is connected to the flash, the FPGA and a parallel-port cable, and can either program the flash from the parallel port, or program the FPGA from the flash. I _think_ the address and data buses from the flash are also connected to the FPGA. That seems a nice way to do it: the machine can't get into an unprogrammable state, it's very off-the-shelf components. TomArticle: 90394
codejk wrote:
>Hi, All.
>
>Nowdays I'm focusing on building some design for
>multiplication of matrices that each element is
>floating point number.
>
>What I want to do is -
>
>M(0,0), M(0,1), M(0,2)
>M(1,0), M(1,1), M(1,2)
>M(2,0), M(2,1), M(2,2)
>
>multiply by vector
>
>V(0,0)
>V(1,0)
>V(2,0)
>
>and when I got the result below,
>
>R(0,0)
>R(1,0)
>R(2,0)
>
>I want to divide R(0,0), R(1,0) by R(2,0)
>for normalization.
>
>Is this multiplication and division are possible
>using Spartan3 device with VHDL?
>Or should I convert each floating point numbers
>to integers and calculate all after that?
>
>I'm sure any advice helps me a lot.
>Thanks.
>
>
>
Sure is possible, and you've got plenty of real-estate if you are clever
about the design. Floating point multiplies don't require much more
than a fixed point multiply, so that isn't going to overload the
device. The floating point mutliplies, assuming normalized inputs only
require an adder for the exponent and a conditional one bit shift after
the multiplier to renormalize. The adds are a little more complicated
because they require a denormalize, a fixed point add, and a
renormalize. Your adds in a 3x3 matrix , you've essentially got a 3
input adder, so all three of the multiplier outputs have to be
denormalized to the same weight. This is for all intents a conversion
to fixed point where the common part of the exponent is stripped off and
retained for later. You just look at the individual products, shift
each right by the difference between its exponent and the largest
exponent in the row products and then add them together. The shift can
be envisioned as a 24x24 (assuming single precision here, you might very
likely need less) multiply of the previous multiplier product and
2^(24-shift). The denormalized row products are added together with a
pair fixed point adder (you might want a few extra lsbs), paying
attention to the signs and the sum is then left shifted to eliminate
leading zeros. The left shift is easiest with a layered barrel shift
because you get the leading one detection as part of the shifting. You
can use the embedded multipliers and run them at 125 MHz easily, in
which case you get 10 clocks per matrix multiply, pipelined. That means
you can use 4 embedded multipliers to make up a 24x24 multiply, and then
perform the 9 multiplications sequentially. A second 4 embedded
multipliers, or a barrel shifter made up of about 125 luts will do the
denormalize on the products. You'll need a delay queue (made up of
SRL16s) between the multiplier and the denormalizer to be able to detect
the maximum exponent in each row and then derive the shift distance.
The matrix multiply using floating point as described does not take up
much room.
The divide is actually easier as floating point, especially if you don't
need a lot of precision (you may not, since it is the last operation).
You've got 10 clocks for each divide, so for full single precision, you
only need to compute 3 new bits per clock. By having the inputs to the
divider normalized, you have a smaller range the divdider has to work over.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90395
Nial Stewart wrote:
>"Duane Clark" <dclark@junkmail.com> wrote in message
>news:knd%e.1804$Fi3.669@newssvr29.news.prodigy.net...
>
>
>>praveen.kantharajapura@gmail.com wrote:
>>
>>
>>>Hi all,
>>>
>>>I have a question on POR(Power on reset generation ) using FPGA.
>>>My FPGA does not have a external Power ON reset , i am planning to
>>>generate a Power ON reset in the FPGA only.Is it really feasible to
>>>do this in an FPGA, and use this as the reset for my logic.
>>>Any suggestions appreciated??
>>>
>>>
>>As Antti mentions, most FPGAs nowdays have an asynchronous power on reset built in. Assuming you
>>want an internal synchronous reset, just create a large counter which is will count down once
>>after an asynchronous reset. A synchronous reset would be held until the counter finishes (of
>>course, don't apply the synchronous reset to the countdown counter;)
>>
>>
>
>
>I'd suggest not using "1111...11"s or "000...0"s as the terminal count. If
>you've no external asynch reset to intiialise this counter you can't be
>sure what state it'll be configured to power up in. I'd suggest that
>all '1's or all '0's are the two most likely power up states.
>
>Use "101010...1010" as your termninal count and the odds are the flip-flops
>won't power up to match it.
>
>
>Nial
>
>
>-------------------------------------------------------------
>Nial Stewart Developments Ltd
>FPGA and High Speed Digital Design
>www.nialstewartdevelopments.co.uk
>
>
>
>
Actually, the power up state on most FPGAs is determined by the bit
stream. For Xilinx, flip-flops that have a set or preset input default
to '1' on power up, all others default to '0'. You can change
individual flip-flops by using the INIT attribute and generic. In any
event, the power up state is deterministic. And get this: If you have
an externally applied asynchronous reset, you can actually make that
non-deterministic if you are not careful to have the design come
synchronously out of reset. Consider the case where you have a
free-running binary counter that gets reset to all '1's by an async
reset. The next state of the counter is all zeros, however if you
release your async reset close to the active clock edge, some of the
counter bits will get thier reset released at that clock edge, and some
won't, and will therefore remain reset for one more clock cycle. The
result is your initial count is not consistently all '1's depending on
where the falling edge of reset occured with respect to the clock edge
and the differences in the routing delays and set-up times to the
individual flip-flops in the counter. An asynchronous reset is an
ansynchronous signal and must be properly synchronized by your design in
order to obtain consistent results. This is an alarmingly frequent
design error (and it is not due to metastability as some have
suggested). Generally speaking, asynchronous resets are a very bad idea
in FPGAs. Not only does this design error often trap the unwary, the
async reset also slows down the fabric of the FPGA because of the design
concessions that were made in the flip-flops to include the async reset.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90396"river064" <river064@gmail.com> wrote in message news:1128967594.460257.42820@f14g2000cwb.googlegroups.com... > Hi, all. > > I'm newbie in circuits, > and I have a silly question. > > Suppose that one FPGA device has about 100 Vcc pins > (including VCCINT, VCCO, VCCAUX) and 80 GND pins. > Then how many decoupling capacistors are needed > for this IC? How can I decide that quantity? > > And can I have any reference design about > Xilinx FPGA and its configuration PROM? > I already read datasheet and user guide about that > but it is rather difficult for me. > So I cannot sure my design is right or wrong. > > If there is any reference, let me know that please. > Thank you for interested with my post. > There are many techniques for decoupline - here is a summary of the way I do it - I do not claim it is the best but it seems to work well for me : 1. Use planes for all power supplies (at least locally to the device) 2. Put the planes on adjacent inner layers (I use VCCINT-GND-VCC as a minium) - at the very fastest pulse current demands, the parallel plat capacitance of the planes is very important 3. Place a large low ESR high reliability bulk capacitor near to the device on each supply (I use 100uF Sanyo POSCAP) - connect these to the planes through multiple vias (not thermally relieved) 4. Place 100nF 0603 capacitors on as many supplies as possible, using the obvious GND-VCCINT-VCCIO pairs that the vendor where possible. At least make a complete ring around the device, and if it is a BGA device, fan out the balls so that a "+" shapes of capacitors can be created on the back of the board under the device 5. Place a few larger ceramics as close to the device as possible 5. Use at least two vias (more if possible) to the planes for each connection and do not thermally relieve these vias 6. Capacitors that connect to the device without going through a via are much more useful Not very scientific, but I've decoupled >1GHz CPU's and >166MHz FPGA's this way without any problems. Another thing to consider is what creates the impulse current demands that make decoupling so critical. In this regard, consider making your design use non-simultaneous output switching, and use slow dV/dt and low drive strength output options where you can. Hope this helpsArticle: 90397
Try opening up the datasheet and look under the section about PLL's. You can also pick up some app notes from Altera's website. Altera has MegaWizard function for their PLL's, called altpll. Have fun. "ebi" <sambad_20@yahoo-dot-com.no-spam.invalid> wrote in message news:Or2dnfDUXLHXeNbeRVn_vQ@giganews.com... > hi all dears, > i am new to altera stratix fpgas > i want to know more about plls in the altera FPGA and how can i > produce a clock for my program with plls? > thanks > bye >Article: 90398
At work I use a linux cluster of dual processor Opterons (2.6GHz). They are really fast for simulation work. They completely dominate the Ultrasparc IIIs and the Xeons (memory bound apps go to the sparcs though). This may seem like a dumb answer, but it seems to me that you should be running all of your book keeping things on a separate machine. It doesn't take much horsepower to do that. Anything that doesn't require drivers should run on Windows x64 just like it did on Windows XP, though, so unless your backup software (or quickbooks) needs drivers, you should be ok. All this said...unless you're breaking the 4GB limit on memory, running in 32 bit mode might be the better idea. It's a bit more mature, the hardware is just as fast (if not faster) and it really doesn't present memory limitations. -ArlenArticle: 90399
doomeddave@yahoo.co.uk wrote:
>Ray/Allan,
>
>I am running a dual 3GHz P4 with 3GB RAM with XP x64. ISE 7.1.03i
>works no problem. As does Office etc.. Pretty much everything works
>but some things need a little persuasion. Also, Acrobat is not
>supported the last time I checked. Also, compatible virus scanners are
>limited (Avast is one however).
>
>I have been able to get Modelsim running under x64 using a USB dongle
>based license. Firstly, to install Modelsim, I needed to restart in
>diagnostic startup mode (start->run->msconfig to do this).
>
>The problem with the USB dongle is that Macrovision don;t seem to have
>got around to x64 yet. However:
>
>Based on the info at http://tinyurl.com/7dzpv, I got a USB wireless
>network adapter (http://tinyurl.com/cyots) and then used a driver
>directly from the chipset manufacturer (Ralink) which supports x64
>(that was the tricky part) to install it.
>http://www.planetamd64.com/index.php?showtopic=6301
>http://catalog.belkin.com/IWCatProductPage.process?Product_Id=179211
>
>For the driver:
>http://www.ralinktech.com/supp-1.htm
>
>Driver:
>11g-RT2500
>USB 2005/07/26 Drv2.0.3.0 XP x64
>
>Before installing, follow the instructions starting on p7 of:
><http://www.ralinktech.com.tw/drivers/Windows/Software%20Release%20Note%20RT2500USB%20STA%20072205.pdf>
>to add a line to the .inf file so that the Ralink section has a
>USB\VID_050D&PID_7050 entry:
>
>[Ralink.NTamd64]
>; DisplayName Section DeviceID
>; ----------- ------- --------
>%Ralink.DeviceDesc% = RALINK.ndi,
>USB\VID_148F&PID_2570
>%Ralink.DeviceDesc% = RALINK.ndi,
>USB\VID_050D&PID_7050
>
>I then got my Modelsim disti to rehost my license to the MAC of the USB
>network stick and hey presto I am in business and can move my license
>about...
>
>I like my system though - it flies and now everything works as it
>should.
>
>Cheers,
>
>Dave
>
>
>
Thanks guys. I think I've settled on an Athlon 64 X2 4800+ system. I
was considering building, but am so short on time these days that I'll
likely just buy one of the high end gaming systems such as the alienware
alx or voodoo omen.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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