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> From: sc@einstein.vcc.com (Steve Casselman)
> "rule of thumb" performance numbers for FPGAs. The number
> was how many 8-bit adders you can fit in an FPGA times the
> frequency at which they can be clocked. This came from me
> and the thought behind it was most operators in a high
> level languages are simular to adds: adds, subtracts, compares,
.
.
.
> 8-bit ops it can do. Although You can't get 100% utillization
> if you think about 50% utillization and then consider that
You want to normalize to silicon area (cost), as well.
Also, it is worth thinking about the conditions required to achieve
peak (or a given utilization level) in each of the architectures.
See <ftp://transit.ai.mit.edu/transit-notes/tn131.ps.Z> for my
(extended) take on this. ...or start with the shorter blurb
<http://www.ai.mit.edu/projects/transit/reconfig.com/rc_for_gp.html>, but
all the detailed metrics and discussion are in the long TR.
Andre'
Article: 3526This is a multi-part message in MIME format. ---------------------------------9385414512591 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii I have worked with the flex 8000 series components and these warning messages arevery similar to ones I have received. In the Flex 8000 parts, and also in the Flex 10k devices, the logic blocks contain carry chains that are used when counters and adders are synthesized. I typically get this error message at the beginning of the carry chain, ie. carry in. > >WARNING: Can not merge logic fed by CARRY primitive (an > instance name) into a single cell > >INFO: Ignored 16 superfluous non-implementable CARRY or > CASCADE primitives > >WARNING: CARRY primitive (an instance name) ignored > In this case, the carry chain is trying to drive more than one output. Carry chains can only output to the next logic block. >WARNING: CARRY primitive (an instance name) can not feed more > than one non-VARRY primitive > >WARNING: CASCADE primitive (an instance name) cannot feed > primitive (an instance name) because it already > feeds primitive (another instance name) > >WARNING: Multiple CARRY primitive feed (an instance name) > > What happens when you get one of these errors is typically that the Alter synthesizer throws in a logic block or two to buffer the inputs/outputs which typically results in lower overall performance. Hope that this helps. Note that I had a difficult time working through these issues with the Altera tools so good luck. Doug Dillon Eaton Corporation Milwaukee, WI ---------------------------------9385414512591 Content-Transfer-Encoding: 7bit Content-Type: text/plainArticle: 3527
Can anybody shed some light (pros and cons) on this subject? I see two companies (Orbit and Temic) advertising about it. What is the conomics of this conversion? Is it as good as it sounds?Article: 3528
In article <peter-1106961320340001@appsmac-1.xilinx.com>, Peter Alfke writes: > In article <4pi8ro$48hc@news-s01.ny.us.ibm.net>, 100410.763@compuserve.com > wrote: > > > I need to build a UART into an Actel 1010. [snip] > Or you make your choices up front and implement a UART with exactly your > desired features, e.g. 7 data bits, 1.5 stop bits, odd parity, etc and > forget all the unnecessary flexibility, because you don't relly need it. > That solution can be quite efficient. Can you elaborate a little? Can UART be reasonably implimented in large CPLDs? (the bigger Mach chips for example) How about performance? Has anyone done a fast (>115kbps) UART in an FPGA or CPLD? ---- "..very sad life. Probably have very sad death. But there's symetry" Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 3529
>Can anybody shed some light (pros and cons) on this subject? >I see two companies (Orbit and Temic) advertising about it. >What is the conomics of this conversion? Is it as good as it sounds? I have done this with one of the two firms above (cannot say which, sorry) and found they were only just developing the Xilinx -> their-own netlist conversion tools. So check this before you use any such firm. Make sure they can accept your FPGA netlist and your FPGA simulation vectors. Design some simple schematic, simulate it, then give them samples of both the netlist and the vectors, and get a confirmation they can read them, do a layout, and simulate with _your_ vectors. And you should expect to have to do some extra test vectors as well, to keep them happy with fault coverage. Check they have automatic test vector generation tools, these can save a lot of time. Otherwise, you can save yourself a lot of money, if the volume is high enough. I have had quotes from Xilinx for their hard-wired parts but they were only about 2x cheaper than the standard parts, in say 10k qtys. An ASIC can be 3x-5x cheaper. But you have to get your own quotes. Things are changing all the time. The other benefit of an ASIC is lower dynamic power consumption. You are not driving a long global clock line etc. You can get dynamic power savings of the order of 10x-20x. This may or may not be relevant.Article: 3530
Eric Edwards wrote: > > In article <peter-1106961320340001@appsmac-1.xilinx.com>, Peter Alfke writes: > (snip) >Has anyone done a fast (>115kbps) UART in an FPGA or CPLD? I've done a 4MBps UART with IrDA Modulator/Demodulator (up to 1.15MBps) in a little section of Xilinx XC3090. It's pretty easy if you don't include all the bells and whistles. Regards, ScottArticle: 3531
Have you tried outputting a TDF instead of an EDIF from Exemplar ? If not, try it; it may work!Article: 3532
Article: 3533
In article <z6qJy*Ya3@wolf359.exile.org>, eric@wolf359.exile.org (Eric Edwards) wrote: Can UART be reasonably implimented in large > CPLDs? (the bigger Mach chips for example) How about performance? Has > anyone done a fast (>115kbps) UART in an FPGA or CPLD? > Most subfunctions in a UART are simple transfers between registers, give or take some parity checking. Modern FPGAS can do that easily at data rates in the tens of MHz. 50 MHz might perhaps be a challenge, especially for half-bit functions, but we can now do asynchronous ( or synchronous ) FIFOs at that rate and we are heading for 100 MHz. Peter Alfke, Xilinx ApplicationsArticle: 3534
Having read the Xilinx data book, there could be a slight bug in the following program
from Scott Kroeger.
The Xilinx data book says that CCLK should be 'parked high' and should not be low for
more than 10 uS. Now if an interrupt were to occur while CCLK was low, you could violate
this.
I'd suggest putting a disable() enable() pair around the accesses to CCLK, as shown
below, to keep safe.
Thanx for the program Scott!
-- Charles
>
>Program follows (originally compiled with QuickC):
>
>/*
> A simple program to download intel hex format Xilinx bitmap files to
> Xilinx devices in slave serial mode from the PC parallel port (LPT1).
>
> Scott Kroeger Copyright 1989
>
> Wiring:
>
> LPT Port Pin Port Name Xilinx Pin
> 2 D0----------DIn
> 3 D1----------CClk
> 6 D4----|<----*Prog/Done
> 13 SelectIn----*Prog/Done
>
> Note: -|<- = Schottky diode.
>
>*/
>
>#include <stdio.h>
>#include <ctype.h>
>#include <fcntl.h>
>#include <conio.h>
>
>main(argc,argv)
>
>char *argv[];
>int argc;
>
>{
> FILE *in;
> int doReset;
>
> printf("Xilinx downloader version 1.0\n" );
>
> if (argc < 2) {
> printf("correct usage is: download infile\n");
> exit(1);
> }
>
> in = fopen (argv[argc-1],"rt");
> if(in == NULL){
> printf("can't open input file: %s\n",argv[argc-1]);
> exit (1);
> }
>
> doReset=1;
> if( strstr(argv[1],"-r") ) doReset = 0;
>
> download(in,doReset);
>
> fclose(in);
> return (0);
>}
>
>download(in,doReset)
>FILE *in;
>int doReset;
>{
> register int c,byteCount;
> outp(0x378,0x03); /* assert prog */
> if(doReset){
> printf("Reset the device and press a key when ready.\n");
> while (kbhit()==0);
> }
> outp(0x378,0x13); /* release prog */
> if (inp(0x379) & 0x10) {
> printf("Done did not stay low, loading stopped.\n");
> }
> getc(in); /* discard first record */
> while ((c=getc(in)) != EOF){
> if(c == ':') {
> if(byteCount = GetByte(in)){
> downloadRecord(byteCount,in);
> }
> }
> }
> if (inp(0x379) & 0x10)
> printf("Load Done.\n");
> else
> printf("Done did not go high, bad load.\n");
>}
>
>downloadRecord(byteCount,in)
>FILE *in;
>int byteCount;
>{
> int a;
> GetByte(in); /* discard load address and record type */
> GetByte(in);
> GetByte(in);
>
> for(;byteCount>0;byteCount--){
> SendByte(GetByte(in));
> }
>}
>
>GetByte(in)
>FILE *in;
>{
> int b,temp;
> temp = getc(in);
> b=toupper(temp)-'0';
> if (b > 9) b-=7;
> temp=b<<4;
>
> b = getc(in);
> b=toupper(b)-'0';
> if (b > 9) b-=7;
> b=b+temp;
> return(b);
>}
>
>SendByte(byte)
>int byte;
>{
> int bit;
>
> for (bit=0;bit<=7;bit++) {
disable(); /* <----------Interrupts off -------- */
> if(byte & 1) {
> outp(0x378,0x11); /* Data = 1, CClk = 0 */
> outp(0x378,0x11); /* waste time to avoid overruns */
> outp(0x378,0x13); /* Data = 1, CClk = 1 */
> outp(0x378,0x13);
> }
> else {
> outp(0x378,0x10); /* Data = 0, CClk = 0 */
> outp(0x378,0x10);
> outp(0x378,0x12); /* Data = 0, CClk = 1 */
> outp(0x378,0x12);
> }
enable(); /* <-----------Interrupts on --------- */
> byte = byte >> 1;
> }
>}
--
------------ When all else fails, find a scapegoat ----------------
Charles Manning manningc@southern.co.nz
Christchurch, New Zealand
-------------------------------------------------------------------
Article: 3535In article <31C38FD8.18C3@cinenet.net> Kayvon Irani <kirani@cinenet.net> wrote: > Have you tried outputting a TDF instead of an EDIF from Exemplar ? > > If not, try it; it may work! > Yes, I did. Those warning messages still appeared. By the way, I'd like to point out that I did not "flatten" the design hierarchy, instead I made Exemplar's Galileo synthesize each design entity and used Altera's MAX+PLUSII to merge them. Of course, flattening a hierarchy is not feasible for large designs. Basically TDF or EDIF makes no difference in the synthesized logic, right? To merge all netlist outputs from Galileo, in my experience, no matter with ALTERA's MAX+PLUSII or ACTEL's ACTMAP, we have to turn on the -vhdl_names=2.0 switch, otherwise there will be port name mismatch error among interconnected netlist files and the netlist merger fails to merge them together. Any other comments? In addition, have anyone found that Galileo has identical name for instances and nets in the outout netlist? It is unbelivable, because the output structural VHDL file (for post-synthesis or post-route simulation) can not pass the VHDL simulator's compiler check, at least for model-tech's V-system. Regards, Felix K.C. CHEN -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3536
Dear Jae-Weon Seo,
Although I am not an expert of design_analyzer either, I hope
I can be helpful.
You can try the following scripts in various combinations
and see how they work.
default_name_rules="sge_vhdl"
change_names -hierachy /* to remove backslash in naming */
vhdlout_write_components=FALSE /* or TRUE */
vhdlout_use_packages={IEEE.std_logic_1164 libname.componenets}
^
|
see youe target vendor's FTGS file for the package name
If you can feedback me with any conclusion, I will be appreciated.
Best wishes,
Felix K.C. CHEN
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw
Machines and tools are only as
good as the people who use it.
---------------------------------
--
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw
Machines and tools are only as
good as the people who use it.
---------------------------------
Article: 3537Hi, For a new design I want to use a Xilinx 4025 FPGA. Have anybody experience in using the XC4025? How is the utilization in pin locked design? How is the electrical behavior? LudgerArticle: 3538
Kalyan Gokhale wrote:
>
> Can anybody shed some light (pros and cons) on this subject?
> I see two companies (Orbit and Temic) advertising about it.
> What is the conomics of this conversion? Is it as good as it sounds?
We have a product that might help you out...It is a low cost
alternative if you are using Xilinx and want to keep your
foundry options open. Our tool, VBAK/SST converts a Xilinx
XNF netlist to a Synthesizable VHDL representation. You can
run the output through any synthesis tool and target whatever
foundry or other FPGA you would like. You can also use this
to merge XNFs together...
Regards,
Melissa Abato
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Melissa Abato Topdown Design Solutions, Inc. Phn: 603-888-8811
mla@topdown.com 71 Spit Brook Road, Suite 301 Fax: 603-888-7694
Manager, Advanced Dev. Nashua, NH 03033 USA http://www.topdown.com
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Makers of: VBAK/Vital, VBAK/SST, VHDL SelfStartKit, U-DRAM
===========================================================================
Article: 3539>Has anyone done a fast (>115kbps) UART in an FPGA or CPLD? This would be easy. The 115k "limit" comes from the limit of most RS232 driver/receiver chips, over a few metres of cheap cable. A UART needs a x1 clock to transmit (i.e. a 1MHz clock to transmit at 1mbit/sec) and a x16 (ideally) clock to receive, i.e. 16MHz to receive 1mbit/sec async data. These are easy in any FPGA. Peter.Article: 3540
Does anyone have the JTAG Boundary Scan Connector Pinout. Thanks Neville Miles ----------------------------------------------------------- Neville Miles Email:nevm@rd.scitec.com.au Hardware Engineer Ph: (02) 428 9516 Scitec Communications Ltd Fax (02) 428 9933 Mobile: (0411) 145 980 http://www.scitec.com.au Int: +(612) 428 9516 -----------------------------------------------------------Article: 3541
Hello Ludger, we used the XC4025 in a rapid prototyping project and had serious routing problems with this part. Depending on your design the utilization might not be better than 50%, because you have to use CLBs for routing. For regular structured designs this could be better. If routability is a problem, you might use the XC4025E, which has improved routing resources. ChristianArticle: 3542
Hi, I'm doing FPGA Design using a VHDL entry. That is I write the design, simulate it (V_System from ModelTechnology), synthesize (ASYL+ from IST-MINC) and then put it into Xilinx. Up to now we used the XACT software (I believe the update to 6.0 came last week). I would like to know more about the Xilinx Foundation series. I already looked at the Xilinx Webserver, but the offered information doesn't give me any clue about the supposed role of the package. Can somebody tell me what role the Foundation Series is supposed to play in the whole Xilinx design flow. Is it supposed to replace the XACT stuff? Or is it just an extention of the XACT stuff. If it is an alternative to the XACT stuff, how much sense does it make to switch? Or is it supposed to replace my whole design tool set (it includes simulation and VHDL synthesis - using the full VHDL standard). So, please tell me what you think. Thomas -- ------------------------------------------------------------------- | Thomas Hadlich hadlich@infaut.et.uni-magdeburg.de | | http://infaut.et.uni-magdeburg.de/~hadlich | -------------------------------------------------------------------Article: 3543
Charles Manning wrote: > > Having read the Xilinx data book, there could be a slight bug in the following program > from Scott Kroeger. > > The Xilinx data book says that CCLK should be 'parked high' and should not be low for > more than 10 uS. Now if an interrupt were to occur while CCLK was low, you could violate > this. > > I'd suggest putting a disable() enable() pair around the accesses to CCLK, as shown > below, to keep safe. > > Thanx for the program Scott! OOPS! Indeed you have found a bug. Thanks and you're welcome. ScottArticle: 3544
In article <4pmftc$bev@bertrand.ccs.carleton.ca> gbhullar@doe.carleton.ca (Gurpreet S. Bhullar) writes: >Hi, > I'm looking for information on types of faults that occur in >SRAM based FPGAs such as XC3K/4K and AT&T ORCA. The type of >information I'm looking for is 1. which resources fail most often ( >local lines/CLBs/IOBs/pips/switch matrices) 2. What faults are most >common (metal migration/ bridging etc). > It would be helpful if there was some info on how closely do >FPGA failures resemble those of PLAs or static RAMs. Pointers to books >/papers/data sheets etc would be appreciated. Thanks for your time. >regards, >Gurpreet. > At a guess (somewhat educated :-), I would say that the SRAM based FPGAs failure modes are most likely to be similar to CPU chips rather than PLDs or SRAMs. For the Altera 8000, 10000, Xilinx 2000, 3000, 4000, 5200, 6200, Atmel 6000 (concurrent), Plessey (defunct), Toshiba (still born), Motorola MPA, ATT 3000, 1C, 2C, and any others that I have forgotten, these devices all have the following characteristics (guesses): 1) Built in a 'logic process' (2 or more metal layers, 1 poly) 2) No SRAM structures (except for the Altera 10000) 3) Not doing anything really weird with the process technology. Item 2 is probably surprising to some. Here's why I say what I say: SRAMs are designed to be dense, fast, and addressable by word, with the remainder of the array just holding their value until addressed. In all of these architectures, ALL the configuration RAM cells are being read out continuously, and control their various parts of the chips in parallel, and continuously. Since addressing only takes place during configuration and maybe readback, the tradeoffs are very different. SRAMs typically use 4T (poly load) or 6T (lower power) cells. The FPGAs (or at least the Xilinx ones, according to page 2-107) use a 5T cell that is very low power and somewhat slow. Speed is not an issue as access time delays only occur during configuration. ( Yes I know something special must be happening in devices like the XC4000 and 4000E for its CLB RAM, but don't distract me now, I'm on a roll, and it turns out that the above is still more-or-less true). Since the cells are being continuously read out, there is no read or write cycling, (effectively) no addressing, and (effectively) no sense amps, bit lines or word lines (except for configuration, which I am trying to ignore here). So unlike SRAMs, the cells are individuals rather than a tight array, access time is a non issue, and power consumption is close to zero. So all the fault modes that are specific to SRAMs don't apply (including soft error rates, but that's another story). Local lines, long lines, pips, switch matrices, and CLBs are therefore just gates, flipflops, tristateable buffers, muxes and other stuff that you would find in high integration devices like peripheral chips and CPUs. (CPUs in a logic process. If there is a LOT of cache integrated with a CPU, then it might be built in an SRAM process. Depends on the manufacturer. If a CPU includes EPROM/EEPROM, then it must be built in an EPROM/EEPROM process. The only device that I know of that has SRAM type configuration and EEPROM in it is the ex Intel iFX780 and iFX740, now from Altera. Due to their architecture, I consider them to be CPLDs, and so can neatly sidestep the issue since this article is about FPGAs and their failure modes.) So the only thing I haven't talked about yet is the IOBs. These might be harder to model versus any other technology, because in FPGAs, every IOB can be configured so many different ways, it has more stuff in it than something like a CPU pin. I would guess (less informed than other guesses :-) that the IOBs failure rates would be similar to the bidirectional, tristateable, data bus pins of a CPU. Metal migration only occurs if the design was not done correctly. Bridging and opens would follow a CPU model (I guess). Oh, why didn't I say these devices are like PLDs? Because they tend to be either bipolar (fuse) or EPROM/EEPROM based, with fault modes that are all of the above, plus those related to fuse-growback, EPROM cell fading, and stresses due to the high voltages/currents that are needed to program them. The Altera 10000 products are the first devices to include dedicated blocks of SRAM (iFX780 was earlier, but it's not an FPGA). I would guess that although these SRAM blocks do have the density, addressability, and speed of SRAM, they represent too small a percentage of the chip to warant building the device in an SRAM type process, and so they are probably built in the same process as the Altera 8000 products. I hope the above is the type of info you wanted, otherwise I wasted a lot of peoples time reading all this. Philip Freidin.Article: 3545
Hi,
I'm doing some modelling work on FPGA's and for this I would like to know
the actual size of a Xilinx CLB (for all the different families, if
possible).
Is there anyone out there who could give me some info on this?
--
Thanks in advance,
Jo Depreitere
====================================================================
So much to know, so little brain capacity.
(me)
====================================================================
e-mail : jdp@elis.rug.ac.be
URL : http://www.elis.rug.ac.be/ELISgroups/paris/staff/jdp.html
Phone : ++32+9/264 34 09
Fax : ++32+9/264 35 94
Address: University of Ghent
Electronics and Information Systems Dept.
Sint-Pietersnieuwstraat 41
B-9000 Ghent
Belgium
====================================================================
Article: 3546After spending a week using viewdraw-office to enter schematics, I discovered that my new schematics were incompatible with current ORCA FPGA software. This came as quite a shock since I had been teased into believing that it was safe to use the new Viewdraw since it worked on the old schematics that I tested. I called Viewlogic support and they blamed Lucent (the FPGA company formerly known as AT&T but now represented by an unpronouncable big-red-O). I called Lucent and they blamed Viewlogic. It's clear that the fault is Viewlogic's - they released a product that, for no apparent reason and without warning, changes the schematic license so that legitimate products (ORCA wir2ngd) detect a license violation. After getting a bit harsher with viewlogic, they finally came up with some suggestions that didn't work. Meanwhile, I came up with a solution on my own that will fix the problem (details below). The best cure, of course, is prevention: Dont' use viewdraw-office. Solution: Each schematic, symbol, and .wir file has a key in it. The key is usually the 3rd line of the file and has the form: K <license-number> <file-name> The <license-number> is checked against the <file-name>, and the <file-name> must be the same as the file's actual name. When viewdraw-office creates a new file, it gives it a license number that makes it incompatible with older software (including older versions of viewdraw). To fix a file that was broken by viewdraw-office, do the following: In a fresh directory, use an old version of Viewdraw (DOS or Pro-series) to create a completely new schematic with the same name as the broken file. Save and close the file. Edit the file with a text editor and copy the key line onto your clipboard. Open the broken file with your text editor and replace its key line with the one on your clipboard. The file should now work with any licensed tool. The Key line is the same for symbols, schematics, and .wir files. Alternate Solution: Use the netlist flattener that I wrote to flatten the netlist and tack on a valid Key line. This is available as freeware from ftp://eseserver1.fnal.gov/pub/docs/xilinx/vflat.zip and is described in another article on comp.arch.fpgaArticle: 3547
I wrote this because ORCA software currently has no control over mapping in a heirarchichal design. This reads a Viewlogic design and flattens it to a single .wir file. It allows the Xilinx HBLKNM= attribute to be used for ORCA designs. The HBLKNM attribute gives control over mapping in heirarchichal designs. The flattener also solves the bug introduced by the clever folks at Viewlogic that makes workview-office schematics incompatible with existing tools. (See related article on this newsgroup). The flattener is available as freeware from ftp://eseserver1.fnal.gov/pub/docs/xilinx/vflat.zip The manual page follows: =================================================================== VFLAT.EXE Usage: vflat <design> ! Do not include extension. Will flatten a viewlogic .wir file heirarchy using <design> as the top level schematic. It writes the flattened design to a file named wir/flattend.1 Example: check -p framstat ! Make sure all .wir files are up to date vflat framstat ! Flatten into wir/flattend.1 wir2ngd flattend framstat.ngo ! Process with normal FPGA design flow VFLAT processes the following attributes correctly: LABEL: Adds component path name to label HBLKNM: Adds component path name and converts to BLKNM All other attributes get passed without modification. Files: viewdraw.ini Contains a list of libraries wir/ Top-level design files. wir/flattend.1 Output design file vflat.exe Executable vflat.awk Source code vlat.man This file Reliability: This has been used with ORCA Foundry on three designs. It produces exactly the same results as wir2ngd except where HBLKNM attributes are used. (ORCA Foundry does not handle HBLKNM correctly.) This has not been tested with Xilinx designs.Article: 3548
See <ftp://transit.ai.mit.edu/transit-notes/tn131.ps.Z> (Table 12, page 29) Andre'Article: 3549
I am currently working on a project that will require the usage of a large number of CLB's available in an XC3042pc84 Xilinx Chip. Each CLB has a truth table represented by a group of about 10-15 AND and OR gates. XNFMAP generally groups all of these logic gates in CLBs in the way that I desire it too, but occasionally it splits up these logic gates into two CLBs when I want them all to be associated with the same CLB. Does anyone know if there is a way that I can assign a group of logic gates to a particuler CLB without assigning the CLB to reside in a specific location in the Xilinx chip? Thanks Ed
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