Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
One of the largest problems with ASIC’s and FPGA’s are the delays
through gates or in the routing resources.
My solution is a new gate technology. Premonition Gates!
The premonition gate is a very simple logic element where the
output changes state before the input. The premonition gate
could be used to make up for lost time in a critical circuit.
The premonition gate is also available as a predictOR gate.
The premonition gate is simple to model in Verilog by using
negative values in your '#' terms.
// simple premonition flip flop in Verilog
always @(negedge reset or posedge clock)
if (!reset)
output = # -1 1’b0 ;
else
output = # -1 input ;
My first application for this new technology is to connect
up a few billion premonition gates in series to the digital feed
from the Stock Exchange. This device would enable you to get a
jump on the hot trades for the day.
I also have another new gate technology which would be very useful
in government work. The igNOR gate. No matter what the state of
the inputs to this gate will never changes its output. Very useful
for the digital feed for the telephone support line.
The present synthesis tools will not model these new devices at all.
I propose a new language PropheC developed to for this new gate
technology.
Thanks
Bill Seiler
ccwest@ix.netcom.com
Article: 5976
The 5th Annual IEEE Symposium on
Field-Programmable Custom Computing Machines
Marriott at Napa Valley, Napa, California
April 16 - April 18, 1997
Preliminary Program
http://www.fccm.org
Tuesday, April 15, 1997
7:00 - 9:00 PM Registration and Reception
Wednesday, April 16, 1997
7:30 AM Registration Opens
8:30 - 10:00 AM Session 1
10:00 - 11:00 AM Break and Poster Session 1
11:00 - 12:00 PM Session 2
12:00 - 1:30 PM Lunch
1:30 - 3:00 PM Session 3
3:00 - 4:00 PM Break and Poster Session 2
4:00 - 5:00 PM Session 4
5:00 - 6:00 PM Open
6:00 - 9:00 PM Demonstrations and Reception
Thursday, April 17, 1997
8:00 AM Registration opens
8:15 - 8:30 AM Administrative updates
8:30 - 10:00 AM Session 5
10:00 - 11:00 AM Break and Poster Session 3
11:00 - 12:00 PM Session 6
12:00 - 1:30 PM Lunch
1:30 - 3:00 PM Session 7
3:00 - 4:00 PM Break and Poster Session 4
4:00 - 5:00 PM Session 8
5:00 - 7:00 PM Open
7:00 - 10:00 PM Banquet
Friday, April 18, 1997
8:00 AM Registration opens
8:15 - 8:30 AM Administrative updates
8:30 - 10:00 AM Session 9
10:00 - 11:00 AM Break and Poster Session 5
11:00 - 12:00 PM Session 10
12:00 - 12:30 PM Closing Remarks & Feedback for next year
Wednesday, April 18, 1997 (Day 1)
Session 1: Device Architecture
Title: An FPGA Architecture for DRAM-based Systolic Computations
Authors: N. Margolus
Organizations: Boston University and Massachusetts Institute of Technology
Title: Garp: A MIPS Processor with a Reconfigurable Coprocessor
Authors: J. Hauser, J. Wawrzynek
Organization: University of California, Berkeley
Title: A Time-Multiplexed FPGA
Authors: S. Trimberger, D. Carberry, A. Johnson, J. Wong
Organizations: Xilinx, Inc.
Poster Session 1
Session 2: Communication Applications
Title: An FPGA-Based Coprocessor for ATM Firewalls
Authors: J. McHenry, P. Dowd, T. Carrozzi, F. Pellegrino, W. Cocks
Organization: National Security Agency and University of Maryland
Title: A Wireless LAN Demodulator in a Pamette: Design and Experience
Authors: T. McDermott, P. Ryan, M. Shand, D. Skellern,
T. Percival, N. Weste
Organization: Macquarie University, CSIRO, and Digital Equipment Corp.
LUNCH
Session 3: Run Time Reconfiguration
Title: Incremental Reconfiguration for Pipelined Applications
Authors: H. Schmit
Organization: Carnegie Mellon University
Title: Compilation Tools for Run-Time Reconfigurable Designs
Authors: W. Luk, N. Shirazi, P. Cheung
Organization: Imperial College
Title: A Dynamic Reconfiguration Run-Time System
Authors: J. Burns, A. Donlin, J. Hogg, S. Singh, M. de Wit
Organization: University of Glasgow
Poster Session 2
Session 4: Architectures for Run Time Reconfiguration
Title: The Swappable Logic Unit: A Paradigm for Virtual Hardware
Authors: G. Brebner
Organization: University of Edinburgh
Title: The Chimaera Reconfigurable Functional Unit
Authors: S. Hauck, T. Fry, M. Hosler, J. Kao
Organization: Northwestern University
Thursday, April 17, 1997 (Day 2)
Session 5: Architecture
Title: Computing Kernels Implemented with a Wormhole RTR CCM
Authors: R. Bittner and P. Athanas
Organization: Virginia Polytechnic Institute
Title: Mapping Applications to the RaPiD Configurable Architecture
Authors: C. Ebeling, D. Cronquist, P. Franklin, J. Secosky, S. Berg
Organization: University of Washington
Title: Defect Tolerance on the Teramac Custom Computer
Authors: B. Culbertson, R. Amerson, R. Carter, P. Kuekes, G. Snider
Organizations: Hewlett-Packard Laboratories
Poster Session 3
Session 6: Performance
Title: Systems Performance Measurement on PCI Pamette
Authors: L. Moll, M. Shand
Organizations: Pole Universitaire Leonard de Vinci and
Digital Equipment Corp.
Title: The RAW Benchmark Suite: Computation Structures
for General Purpose Computing
Authors: J. Babb, M. Frank, E. Waingold, R. Barua, M. Taylor,
J. Kim, S. Devabhaktuni, P. Finch, A. Agarwal
Organization: Massachusetts Institute of Technology
LUNCH
Session 7: Software Tools
Title: Automated Field-Programmable Compute Accelerator Design Using
Partial Evaluation
Authors: Q. Wang, D. Lewis
Organization: University of Toronto
Title: FPGA Synthesis on the XC6200 using IRIS and Hades
Authors: R. Woods, S. Ludwig, J. Heron, D. Trainor, S. Gehring
Organization: The Queen's University of Belfast and ETH Zurich
Title: High Level Compilation for Fine Grained FPGAs
Authors: M. Gokhale, E. Gomersall
Organization: David Sarnoff Research Center and National Semiconductor
Poster Session 4
Session 8: CAD Applications
Title: Acceleration of an FPGA Router
Authors: P. Chan, M. Schlag
Organization: University of California, Santa Cruz
Title: Fault Simulation on Reconfigurable Hardware
Authors: M. Abramovici, P. Menon
Organization: Lucent Technologies and University of Massachusetts
Friday, April 18, 1997 (Day 3)
Session 9: Image Processing Applications
Title: Automated Target Recognition on Splash 2
Authors: M. Rencher, B. Hutchings
Organization: Brigham Young University
Title: Real-Time Stereo Vision on the PARTS Reconfigurable Computer
Authors: J. Woodfill, B. Von Herzen
Organization: Interval Research Corp. and Rapid Prototypes, Inc.
Title: Increased FPGA Capacity Enables Scalable, Flexible CCMs:
An Example from Image Processing
Authors: J. Greenbaum, M. Baxter
Organization: Ricoh California Research Center
Poster Session 5
Session 10: Arithmetic Applications
Title: Comparison of Arithmetic Architectures for Reed-Solomon
Decoders in Reconfigurable Hardware
Authors: C. Paar, M. Rosner
Organization: Worcester Polytechnic Institute
Title: Implementation of Single Precision Floating Point
Square Root on FPGAs
Authors: Y. Li, W. Chu
Organization: University of Aizu
--
Jeffrey M. Arnold jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace Tel: 619-547-9257
San Diego, CA 92131 Fax: 619-547-9010
USA
Article: 5977I am sure you will not fit a 8051 into any 4x series FPGA, by a very big margin. The 8048 is a lot smaller but I doubt even that will fit in a 4k. >Did enyone knows where I can find 8051/8032 romless core for xilinx >FPGA XC40xx family? Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5978
Hi!
My name is Saung-mun Park, and my nationality is Korea.
Now, I live in Seoul, the capital of Korea.
and I am running the company, Park's Business.
Park's Business is providing the business aid & service.
If you want to do the business in Korea, please contact us, and we will help you to make your business best.
And if you need some products which are produced in Korea, please contact us.
We will give you the information about those products such as the price ,quality and advantage.
And if you want to buy those products with that price, we will buy and send those products to you.
we are dealing with computer parts and semiconductors.
If you want the computer parts and semiconductors which are produced in Korea, please send us the mail or the fax.
And then we will gather and send the information that you need to you.
as you know, Korea's semiconductors are best quality and the price is lower than any other countries.
Because in these days, Korea's money value is bring lower than in any other days, you can buy these products with advantage price.
If you are interested in our suggestion, please contact us.
Written by Saung-mun Park
Park's Business
fax 82 - 2 - 889 - 8959
e-mail saungmun@soback.kornet.nm.kr
Article: 5979
Hi!
My name is Saung-mun Park, and my nationality is Korea.
Now, I live in Seoul, the capital of Korea.
and I am running the company, Park's Business.
Park's Business is providing the business aid & service.
If you want to do the business in Korea, please contact us, and we will help you to make your business best.
And if you need some products which are produced in Korea, please contact us.
We will give you the information about those products such as the price ,quality and advantage.
And if you want to buy those products with that price, we will buy and send those products to you.
we are dealing with computer parts and semiconductors.
If you want the computer parts and semiconductors which are produced in Korea, please send us the mail or the fax.
And then we will gather and send the information that you need to you.
as you know, Korea's semiconductors are best quality and the price is lower than any other countries.
Because in these days, Korea's money value is bring lower than in any other days, you can buy these products with advantage price.
If you are interested in our suggestion, please contact us.
Written by Saung-mun Park
Park's Business
fax 82 - 2 - 889 - 8959
e-mail saungmun@soback.kornet.nm.kr
Article: 5980
Hi!
My name is Saung-mun Park, and my nationality is Korea.
Now, I live in Seoul, the capital of Korea.
and I am running the company, Park's Business.
Park's Business is providing the business aid & service.
If you want to do the business in Korea, please contact us, and we will help you to make your business best.
And if you need some products which are produced in Korea, please contact us.
We will give you the information about those products such as the price ,quality and advantage.
And if you want to buy those products with that price, we will buy and send those products to you.
we are dealing with computer parts and semiconductors.
If you want the computer parts and semiconductors which are produced in Korea, please send us the mail or the fax.
And then we will gather and send the information that you need to you.
as you know, Korea's semiconductors are best quality and the price is lower than any other countries.
Because in these days, Korea's money value is bring lower than in any other days, you can buy these products with advantage price.
If you are interested in our suggestion, please contact us.
Written by Saung-mun Park
Park's Business
fax 82 - 2 - 889 - 8959
e-mail saungmun@soback.kornet.nm.kr
Article: 5981Just another reminder to everyone, especially those new to USENET and the web: I have been compiling a semiconductor manufacturer website listing (and making it available to other engineers on the web) for about 2 years now. I used to post it to sci.electronics every so often in the past, but it got way too big for that. There are about 380 companies on the list currently. These are chipmakers, so if you can't find the data sheet that you need because you don't know the manufacturer's website, try my listing. Bookmark it and tell your co-workers. I try to keep it the most up-to-date and useful listing anywhere on the web (by constantly searching for new URLs before most others find them) and it is now widely used by a lot of people. The following categories exist among my "engineering" subpages. - Semiconductor URLs (Brief listing) - Semiconductor URLs (Verbose listing; includes product categories) - New Semiconductor URLs - Missing Semiconductor URLs - Motivations - 25 Best Semiconductor Websites - 25 Worst Semiconductor Websites - Engineering Humor try it out, I think you'll find it to be quite useful. -- +---------------------------------------------+ | Gray Creager | | http://www.scruznet.com/~gcreager | +---------------------------------------------+ | "If you're not part of the solution, you're | | part of the precipitate." - Steven Wright | +---------------------------------------------+Article: 5982
Peter Alfke wrote:
>this power limitation is new to most of us.
It certainly is to me. While we're here, is there any way to measure the
temperature of the silicon, to see if I'm overdoing things? Perhaps a
little 2-clb ring oscillator tucked away, with frequency being a
function of temperature, calibrated by heating up an otherwise empty
chip ?
Is the temperature over the die more-or-less constant, or would one need
an array of these little beasties? (and would they self-heat to the
point of futility, anyway). The device I'm slightly worried about is a
3190A-3-PC84, in a socket, which certainly gets hot to the touch,
although not painfully. (that's the resolution to which my thermal
measurements are currently working....)
Cheers,
Steve
Article: 5983The Gray Pages are a great resource folks ... and that come's from another list compiler >:) Bookmark us BOTH ! -- Electronics Resource Page at http://homepage.dave-world.net/~donw1948/index.html Gray Creager <gcreager@scruznet.com> wrote in article <33420795.3216@scruznet.com>... > Just another reminder to everyone, especially those new to USENET and > the web: ... snipped ... > try it out, I think you'll find it to be quite useful. > > -- > +---------------------------------------------+ > | Gray Creager | > | http://www.scruznet.com/~gcreager | > +---------------------------------------------+ > | "If you're not part of the solution, you're | > | part of the precipitate." - Steven Wright | > +---------------------------------------------+ >Article: 5984
Vitit Kantabutra wrote: > > Andrew Papageorgiou wrote: > > > > In article <33362D36.474D@nocrc.abb.no>, Johannes Soelhusvik > > <jso@nocrc.abb.no> writes > > >Tom Burgess wrote: > > > > ...... > > > > >First of all, thanks very much for responding to my query. > > >I confirm that I just want the integer portion of the division. And your > > >suggested solution is nice and simple, but I do not have time to go > > >through as many as 255 clock cycles (worst case). What can I do to > > >reduce this to say 32 ? > > I have a new algorithm for division that retires 2-3 bits per iteration, > yet is much simpler than Radix-4 SRT because it uses no lookup table. > It only needs 2-bit comparisons plus a little simple logic. The article > is in the proceedings of ICCD '96. > > Maybe my algorithm is suitable for FPGA implementation. (I don't see why > not.) > > Let me know if you are interested. > > Vitit Kantabutra > http://www.isu.edu/~kantviti > vkantabu@howland.isu.edu I am very interested in your paper. Could you tell me how I can get hold of it ? -- Johannes Sølhusvik ABB Corporate Research Electronic Systems Dept. P.O. Box 90 N-1361 Billingstad Norway Tel: +47 66 84 34 28 Fax: +47 66 84 35 41 Email: jso@nocrc.abb.noArticle: 5985
You can find XESS on the Programmable Logic Jump Station under the boards section at 'http://www.netcom.com/~optmagic/boards.html'. Their specific address is 'http://www.xess.com/FPGA/homepage.html'. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic mike turner <Mike_Turner@Kemet.com> wrote in article <33416720.6A0C@Kemet.com>... | There was a company in business last year called Xess that was selling a | pcb with an 8051 and an FPGA on board. Did they fold or can anyone tell | me how to get in touch with them? Thanks. |Article: 5986
I don't see it on their web site but I would ask VAutomation if they have such a thing. You can find them at 'http://www.vautomation.com'. ARM Semiconductor also supposedly has a ROM-less 8051 core but I don't know if it is targeted for the Xilinx XC40XX family. They don't seem to have a web site but here are their contact details: ARM Semiconductor, Ltd. 1094 E. Duane Ave., Suite 211 Sunnyvale, CA 94086 USA Phone: 408-733-3344 Fax: 408-733-9922 E-mail: armsemi@netcom.com -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Utente Occasionale <guest@exor.it> wrote in article <5hrb6f$12b0@urano.inet.it>... | Did enyone knows where I can find 8051/8032 romless core for xilinx | FPGA XC40xx family? | | Davor Kovacec | SITEK s.r.l. | | |Article: 5987
Try http://www.xess.com/FPGA/compinfo.html Good luck ! Bernd StoehrArticle: 5988
Utente Occasionale wrote: > > Did enyone knows where I can find 8051/8032 romless core for xilinx > FPGA XC40xx family? > > Davor Kovacec > SITEK s.r.l. Sure you can do that if you want the typical 8051 speeds of yester-year. Last week someone posted a site that had 3rd party cores on it and several had ported them to FPGAs. I remember seeing an 8051 or two. Do a search for FPGA or Cores and you should find the site. good luck TomT... -- +-----------------------------------------------------------------------+ : ttessier@talcian.com | Phone: (303)665-6402 : : Thomas Tessier | FAX: (303)665-6431 : +------------------------Have a nice Day--------------------------------+Article: 5989
I am with Human Resources for the Small Internetworks Business Unit (formerly Grand Junction) at Cisco Systems. We develop switches, routers, and hubs that focus on small and medium-sized companies. Revenue-wise we are the fastest growing Business Unit at Cisco Systems with 30+% growth over the last five quarters. We are currently looking for senior and intermediate ASIC Engineers (digital) as well as senior and intermediate Systems Engineers (embedded CPU, FPGA) to join our team. We are located in San Jose, California. If you, or anyone you know is interested, please contact me or send me your resume. I will be happy to talk with you further about the positions. To send your resume: fax: 408-527-8048 or email: lshevock@cisco.com No agencies please -- To send your resume: fax: 527-0180 or email: lshevock@cisco.com No agencies pleaseArticle: 5990
Bill Seiler wrote: > > One of the largest problems with ASIC’s and FPGA’s are the delays > through gates or in the routing resources. > > My solution is a new gate technology. Premonition Gates! > The premonition gate is a very simple logic element where the > output changes state before the input. The premonition gate > could be used to make up for lost time in a critical circuit. > The premonition gate is also available as a predictOR gate. > The premonition gate is simple to model in Verilog by using > negative values in your '#' terms. > > // simple premonition flip flop in Verilog > always @(negedge reset or posedge clock) > if (!reset) > output = # -1 1’b0 ; > else > output = # -1 input ; > > My first application for this new technology is to connect > up a few billion premonition gates in series to the digital feed > from the Stock Exchange. This device would enable you to get a > jump on the hot trades for the day. > > I also have another new gate technology which would be very useful > in government work. The igNOR gate. No matter what the state of > the inputs to this gate will never changes its output. Very useful > for the digital feed for the telephone support line. > > The present synthesis tools will not model these new devices at all. > I propose a new language PropheC developed to for this new gate > technology. > > Thanks > Bill Seiler > ccwest@ix.netcom.com There are lots of wanna be comedians in this world. Keep your day job.Article: 5991
I have a customer who wishes to perform 16 QAM mod/demodulation at 1-4 Megabaud. The transmission media is RF. How effective can this be done in FPGA? Is there any public domain application material for this? Can the job be partitioned into a DSP/FPGA solution? How much DSP grunt would be required if a general purpose DSP was chosen? Thanks -Andrew Metcalfe, ACD AustraliaArticle: 5992
Bill Seiler wrote: > > One of the largest problems with ASIC’s and FPGA’s are the delays > through gates or in the routing resources. > > My solution is a new gate technology. Premonition Gates! You will need a dovetail waveform generator to test these things... > > I also have another new gate technology which would be very useful > in government work. The igNOR gate. No matter what the state of > the inputs to this gate will never changes its output. Very useful > for the digital feed for the telephone support line. This work is already being used in the WRITE ONLY MEMORY - ideal for those super high security projects, or those on such tight time lines that no testing is possible > > The present synthesis tools will not model these new devices at all. > I propose a new language PropheC developed to for this new gate > technology. > > Thanks > Bill Seiler > ccwest@ix.netcom.com jim granville.Article: 5993
In message <5hpa1q$pb4@news2.Belgium.EU.net>
win@netwise.be (Wim Vanderstraeten) writes:
> I recently purchased a second hand 486 and found a larg( network?)ISA
> card in it.On the biggest chip is inscribed XILINX xc2018-50.Can
> somenone tell me what it is and what it is worth?
> Wim
This is the larger member of Xilinx original Logic Cell Array family
probably released 10 or 12 years ago. It is only about 1k gates and
probably not used in any new designs these days. I doubt if it is
worth five dollars unless it has antique value now :-).
Geoff Bostock
--
************************************************************************
* FPGA Design Consultant and Bed and Breakfast in Wiltshire (UK) *
* Powernet International independant distributor *
* See http://www.users.zetnet.co.uk/gbostock *
************************************************************************
Article: 5994In article <33421769.2D30@sj.co.uk>, Steve Wiseman <steve@sj.co.uk> writes >Peter Alfke wrote: >>this power limitation is new to most of us. > >It certainly is to me. While we're here, is there any way to measure the >temperature of the silicon, to see if I'm overdoing things? Perhaps a >little 2-clb ring oscillator tucked away, with frequency being a >function of temperature, calibrated by heating up an otherwise empty >chip ? >Is the temperature over the die more-or-less constant, or would one need >an array of these little beasties? (and would they self-heat to the >point of futility, anyway). The device I'm slightly worried about is a >3190A-3-PC84, in a socket, which certainly gets hot to the touch, >although not painfully. (that's the resolution to which my thermal >measurements are currently working....) > A simple test for the temperature of chips is to wet your finger (with saliva) and touch the chip. If it is hot you will get a sizzling (saliva boils at about 80 degrees C from what I remember). This also protects you from getting a dry burn of a chip. If you can hold a dry finger on a dry chip then the temperature is less than 50 degrees C. Your pain threshold for heat is about 50 degrees C (depends on the person but thats about the average). This should give you an idea, at least, of the operating temperature. I know that thiese techniques are not totally accurate but s is a good engineering gues on how hot something is. You can always use a temp. probe to see what the case temperature is and then use your Thermal resistance calcs. to find out what the junction temperature is. Regards, P.S. I like your idea of a temperature controlled oscillator. If that works it'll be very useful. The problem is characterising it due to process spread. Gareth Baron %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % % % Morphesys Ltd. Tel: +44 (0)802 754 512 % % % % EMail: Gareth@trsys.demon.co.uk % % % % http://www.trsys.demon.co/ % % % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Article: 5995
In message <5hrpis$alv@sjx-ixn7.ix.netcom.com>
ccwest@ix.netcom.com (Bill Seiler) writes:
> One of the largest problems with ASIC s and FPGA s are the delays
> through gates or in the routing resources.
> My solution is a new gate technology. Premonition Gates!
> The premonition gate is a very simple logic element where the
> output changes state before the input. The premonition gate
> could be used to make up for lost time in a critical circuit.
> The premonition gate is also available as a predictOR gate.
> The premonition gate is simple to model in Verilog by using
> negative values in your '#' terms.
> // simple premonition flip flop in Verilog
> always @(negedge reset or posedge clock)
> if (!reset)
> output = # -1 1 b0 ;
> else
> output = # -1 input ;
> My first application for this new technology is to connect
> up a few billion premonition gates in series to the digital feed
> from the Stock Exchange. This device would enable you to get a
> jump on the hot trades for the day.
> I also have another new gate technology which would be very useful
> in government work. The igNOR gate. No matter what the state of
> the inputs to this gate will never changes its output. Very useful
> for the digital feed for the telephone support line.
> The present synthesis tools will not model these new devices at all.
> I propose a new language PropheC developed to for this new gate
> technology.
> Thanks
> Bill Seiler
> ccwest@ix.netcom.com
Sounds like Isaac Asimov's thiotimoline - a solvent which dissolves
substances before it is added to them. It is used as a gauge of
strength of will. If you are really sure that you are going to add
the solvent, the substance will dissolve earlier than if you're not
too sure whether to add it or not. Perhaps it could be diffused into
the silicon to make some premonition gates.
Geoff Bostock
--
************************************************************************
* FPGA Design Consultant and Bed and Breakfast in Wiltshire (UK) *
* Powernet International independant distributor *
* See http://www.users.zetnet.co.uk/gbostock *
************************************************************************
Article: 5996
Configurable Computing Research Group
Department of Electrical Engineering
Princeton University
Post-Doctoral Position Available:
- Performance and Synthesis Tools for Configurable Computing
- Applications Studies in Configurable Hardware
Configurable computing has demonstrated its ability to significantly
improve program performance, sometimes by several orders of magnitude,
via per-application customizations of a compute environment. For
configurable computing to be widely used however, programmers must be
able to harness its application-specific compute power without
herculean design efforts.
Our NSF and DARPA-sponsored research project focuses on tools for
streamlining and automating the use of configurable hardware. Although
some previous research has looked into automatic compilation and
synthesis for configurable systems, the field's current
state-of-the-art has serious shortcomings. These shortcomings
unreasonably force software programmers to become part-time hardware
designers, or to custom-build specialized tools in order to make use of
configurable hardware.
The end products of our research will be a set of performance
characterization and hardware synthesis tools for configurable
hardware, as well as an increased understanding of the applications
and implementation issues of configurable computing with automated
compilation. Our work seeks to retain a traditional software
programming model, while using performance tools to identify key
program phases that the synthesis tools can implement in configurable
hardware.
This position requires a Ph.D. in Computer Science, Electrical
Engineering, or a related discipline. The starting date and duration
are both negotiable.
For more information contact:
Professor Margaret Martonosi
Department of Electrical Engineering
Princeton University
Princeton, NJ 08544-5263
URL: http://www.ee.princeton.edu/~mrm
Email: martonosi@ee.princeton.edu
Princeton is located in a pleasant suburban area within commute
distance of both New York City and Philadelphia. On-campus housing is
available for research staff members. Princeton University is an
Affirmative Action -- Equal Opportunity Employer.
-- mrm
________________________________________________________________
Margaret Martonosi Electrical Engineering Dept.
Assistant Professor Princeton University
martonosi@princeton.edu 609-258-1912 / FAX: 609-258-3745
Article: 5997win@netwise.be (Wim Vanderstraeten) wrote: >I recently purchased a second hand 486 and found a larg( network?)ISA >card in it.On the biggest chip is inscribed XILINX xc2018-50.Can >somenone tell me what it is and what it is worth? >Wim In the most recent issue if XCELL, the Xilinx newsletter, Xilinx anounced that they were discontinuing the XC2000 family. The value of a 2018 may be approaching zero.Article: 5998
In article <1997040308570669908@zetnet.co.uk>, Geoffrey Bostock <geoff.bostock@zetnet.co.uk> wrote: It is only about 1k gates and > probably not used in any new designs these days. I doubt if it is > worth five dollars unless it has antique value now :-). > Xilinx is still shipping these parts, and will until mid-1999, then pass it on to an "end-of-life supplier" ( Rochester Electronics Inc. ) So the XC2018 will not become an antique until well into the next millenium, but there is no reason to specify it for new designs. The XC3020 and XC5202 are better devices and are faster and less expensive. Xilinx devices are often used as a Lifesaver when certain chips have become unavailable. Therefore we are very carefully before we make any of our chips unavailable. The first gentle nudge is not to upgrade the speed, and not reduce the price. That makes these old parts naturally unattractive. But some board designs have a very long life... Peter Alfke, Xilinx ApplicationsArticle: 5999
Utente Occasionale wrote: > > Did enyone knows where I can find 8051/8032 romless core for xilinx > FPGA XC40xx family? > > Davor Kovacec > SITEK s.r.l. These do exist, however you will not get even close to 40MHz / $2 for a 80C32 in FPGA. The best solution is to couple the (now much smaller) FPGA onto a C51 BUS, and run two chips. I have seen 89C55's (20K FLASH) used to also LOAD the FPGA, for a neat two chip solution. We have done a lot of work with CPLD's to slave on C51 bus. jim granville, -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Reusable object modules, for i2c, SPI and SPL bus interfaces = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55 = for more info, Email : DesignTools@xtra.co.nz Subject : c51Tools
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z