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Richard B. Katz wrote: > hi dave, > > i have measured power consumption in a large number of fpga's, mostly > actels. for most models, with no dc loads and static conditions and > inputs at cmos levels, the current is less than 1 mA. If we want to discuss FPGA power seriously, we must make a few distinctions:CPLD ( PAL-derived AND-OR circuits) are different from FPGAs. Dynamic power in FPGAs is much higher than their static power. Almost all CPLDs ( Philips seems to be the only exception ) have significant static power consumption even with all inputs and outputs static. 500 mW is not uncommon, and it is documented in the data sheets. This is static current in the read amplifiers and pull-up resistors used in the array. It is an inherent feature of the way these devices implement their AND array. Static power in FPGAs, be they SRAM or antifuse base, is very low. In SRAM-based parts it is inherently in the microamp range. The current can get into the milliamp range due to various auxiliary linear circuits inside the chip: input threshold modifiers, bias pumping circuits, voltage detectors etc. Antifuse devices have more leakage current in their antifuses. The difference between 10 microamps and 15 milliamps is of concern only to a small number of battery-operated designs with low clock frequency or low duty cycle of operation. The really serious issue is the dynamic power consumption of large devices at high clock rates. Since both device size and clock frequency are increasing, max power has increased from a watt to several, even many, watts. CMOS microprocessors, even when they run at 2.5 V, are now consuming 10 to 30 W and need fancy cooling. High-performance FPGAs are heading in the same direction, although the move to 3.3 and then 2.5 V and then 1.8 V and then even lower, will give all of us some reprieve. It is needed. Heat removal will become a major concern for all high-performance CMOS circuits, and may sometimes become the limiting factor for systems integration. The problem are the amps and watts, usually not the milliamps and milliwatts. Peter Alfke, Xilinx ApplicationsArticle: 7226
We are considering the use of ISP CPLD's. Anyone have any amusing or helpful anecdotes regarding their use? Thanks much. -- Tim Conway Prima Facie, Inc. (314) 989-0644 ext. 16 (314) 989-0654 FaxArticle: 7227
In article <33F493D6.25FB@primafacie.com>, Tim Conway <timc@primafacie.com> writes >We are considering the use of ISP CPLD's. Anyone have any amusing >or helpful anecdotes regarding their use? >Thanks much. With Lattice isp CPLDs, it is a good idea to disconnect the programming cable when you switch the PC off. A glitch on the printer port can sometimes alter the configuration programmed into the CPLD. Leon -- Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Amateur Radio Callsign G1HSM Tel: +44 (0) 118 947 1424 See http://www.lfheller.demon.co.uk/rcm.htm for details of a low-cost reconfigurable computing module using the XC6216 FPGAArticle: 7228
Has anyone done a CDMA corellator?Article: 7229
In article <5t31hd$l4i@canyon.sr.hp.com> gregq@sr.hp.com (Greg Quintana) writes: >Has anyone done a CDMA corellator? Yes oh, ... ok, here is a bit more info ... :-) CDMA correlators look very much like FIR filters, and can be implemented very efficiently on FPGAs, which do quite well at this type of DSP function. The one I designed in a XC4025E does the equivalent of 8 billion taps per second, but for proprietory reasons (my clients), I can't go into the details.Article: 7230
As an applications engineer I am very happy that Atmel has graciously jumped in to fill this void in the Xilinx product line. Let me assure you that this void will also be filled from our side. By-the-way: When you use the fast configuration option with XC4000-series devices, always check the CCLK-to-DATAout delay specification of the serial PROM. Peter Alfke, Xilinx Applications PS: I hope nobody took the recent diatribe by Wade Peterson seriously. What he wrote is complete and utter nonsense. Salespeople may be greedy, but they are not immoral, and definitely not stupid.Article: 7231
I have some 160 pin (15x15 grid) PGA zif sockets on order. Anyone know of a source of some non-zif sockets (in stock) I can get my hands on for immediate use? Thanks Rich Gaupsas rgaupsas@cts.comArticle: 7232
Hello Reader, Would you be interested in..... * receiving money by snail mail from all over the world? * in terms of MILLIONS, starting with $2 million ? * magic hands who create your financial future? Look at mailto:mm5413@persnet.com You'll be very - very - sorry if you don't!Article: 7233
On 13 Aug 1997 22:48:15 GMT, lass@xilinx.com (Steve Lass) wrote: >M1 does support the MAXSKEW constraint which can be used for clock nets. Please excuse my lack of knowledge, but does M1 support 3K series, the origin of this thread from Peter? Isn't this "preference" from the original NeoCAD engine anyway? BTW. Does M1 have a MAXCRASH=0 preference yet? (and is it a constraint, or a "preference"?) StuartArticle: 7234
daveb@iinet.net.au (David R Brooks) wrote: >peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote: >Hmm, I have done several systems using Xilinx FPGAs, that didn't use >their ROMs, for the simple reason the designs included a CPU, and >FPGAs were programmed as slaves by the CPU. > >-- Dave Brooks <http://www.iinet.net.au/~daveb> >PGP public key: finger daveb@opera.iinet.net.au > servers daveb@iinet.net.au > fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34 > What's all this? see http://www.iinet.net.au/~daveb/crypto.html A note about configuration modes, not price. I've done many projects that include a Xilinx FPGA and an 8051 micro. I have used slave mode, but usually want the Xilinx to serve as the adr latch. This means the Xilinx must configure itself in Master mode (top down) from the EPROM, while holding the micro reset, until after configuration ends. If the Master that gets the configuration stream in parallel, from the EPROM does not have enough adr bits to support all the Xilinx FPGAs in the configuration stream, then a I use a two stage (rocket) approach . (Xilinx 'does not know' this trick, and will tell you to use multiple separate, serial EPROMs!) The Master chip configures itself in Master parallel top down mode and then wakes up. All other chips have their config pins connected to mostly user I/O pins on the Master. The Master has a user designed counter connected to the Xilinx adr pins plus one or more extra bits, as required. This counter is designed to go back to the EPROM, starting at an adr below the last adr used by the Master, read the config data, and serialize it to the down stream FPGAs under user design, and user pins. After both config stages are finished, the 8051 reset is released, and it executes from the bottom of the same EPROM. The 3 sections of the EPROM (I usually use FLASH) are combined on the PROM programmer. The first section is the Xilinx Master config data. The second section is all the other Xilinx chips. These bit streams are combined using the Xilinx PROM Formatter (slave mode). The last section is the 8051 micro code. Dave Decker Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 7235
Will someone please e-mail
me the file License.dat
for FPGA-Express v1.2?
Mine is corrupt.
Thank you....
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 7236
Will someone please send me
the file License.dat for
FPGA Express v1.2?
Mine is corrupt!
Thank you...
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 7237Tim Conway <timc@primafacie.com> wrote in article <33F493D6.25FB@primafacie.com>... > We are considering the use of ISP CPLD's. Anyone have any amusing > or helpful anecdotes regarding their use? > Thanks much. There's a new programming standard being developed for programming such devices which is known as JAM. Currently supported by Altera / Cypress, others are expected to adopt it (except Lattice). Check out http://www.altera.com/jam I currently use cypress ISP parts, and have no real problems with programming them - it all works very nicely. The only minor snag is that they need a 12V programming voltage. Cypress gets away with this by creating this in the PC cable. Other devices are nicer and only need a 5V programming voltage (AMD?) Hope this helps > -- > Tim Conway > Prima Facie, Inc. > (314) 989-0644 ext. 16 > (314) 989-0654 Fax >Article: 7238
Can anyone come up with a plausible explanation of how this could be legit? Better yet, given that license.dat files are usually associated with a physical key (and the serial number it contains), or as in M1, the serial number of the C drive, can anyone come up with a way that sending your license.dat file to this person could be anything other than pointless. My suspicion of course is that the license.dat isn't the only thing that is corrupt here. In article <871861371.11015@dejanews.com> cadamson@horizon.hit.net writes: >Will someone please e-mail >me the file License.dat >for FPGA-Express v1.2? >Mine is corrupt. >Thank you.... > >-------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to UsenetArticle: 7239
I'd like to remaind (again!) the Motorola FPGA series MPA1000 which come with a FREE place&route tool for the smaller devices (up to 8000 gates) however without a design entry front-end. I have written a (VERY simple) tool for design entry and simulation which is not yet ready but is in fact able to create useful designs to be processes by the Motorola software. If you're interested drop me a line (remeber, this is still not a commercial product). Documentation and a Pre-Alpha release will be available at http://home.t-online.de/home/akugel/mpa.htm around september. The Motorola SW is located at http://design-net.com/fpga/freedl.html Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 mailto:kugel@mp-sun1.informatik.uni-mannheim.de http://www-mp.informatik.uni-mannheim.deArticle: 7240
I'm not sure if your post is a joke, but I'll respond just in case its not. First of all, license.dat is tied to each particular machine by IP address, or C: drive serial number, etc. No one's license.dat will work on your machine. But even if that were not the case, people should not send you their file because they have no way of knowing that you are really a registered user. My advice is to resolve the problem with Synopsys. -- Rich Iachetta IBM Corporation iachetta@us.ibm.com cadamson@horizon.hit.net wrote in article <871862061.11363@dejanews.com>... > Will someone please send me > the file License.dat for > FPGA Express v1.2? > Mine is corrupt! > > Thank you... > > -------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to Usenet >Article: 7241
Nice to get away from pricing issues... The two-stage approach is a neat idea, but is no longer needed with the XC4000XL parts, since they now have 22 parallel address bits ( even the XC4005XL has!). We never described any 2-stage approach because it means that not all FPGAs go active simultaneously, and we always considered that an important feature. Of course, it depends on the structure of your system whether that is important or not. Thanks for a creative suggestion. Peter Alfke, Xilinx ApplicationsArticle: 7242
Has anyone had both Altera Flex10K and Xilinx XC4000EX devices on the same board, yet configured them using the same set of configuration lines? We need to use the passive (slave) serial configuration mode, and Altera's EPC1 serial configuration PROMs (it may be possible to add Xilinx SCPs after the Altera PROMs, also). If you have any experience with a similar situation, let me know. Thanks!!! -Dirk Brandis note: remove <NO-SPAM> from reply email addressArticle: 7243
On Sun, 17 Aug 1997 19:01:12 -0600, cadamson@horizon.hit.net wrote: >Will someone please send me >the file License.dat for >FPGA Express v1.2? >Mine is corrupt! Why not just get a new one from your vendor?Article: 7244
On Mon, 18 Aug 1997 08:05:06 GMT, fliptron@netcom.com (Philip Freidin) wrote: >Can anyone come up with a plausible explanation of how this could be legit? >Better yet, given that license.dat files are usually associated with a >physical key (and the serial number it contains), or as in M1, the serial >number of the C drive, can anyone come up with a way that sending your >license.dat file to this person could be anything other than pointless. Not necessarily pointless, but certainly illegal ;-)Article: 7245
Bill Ewing wrote: > > Sorry if a post has been made like this, but my news server crashed > and finally (thank God) burned. But I have an unusual take on Xilinx > programming, perhaps... > > My stuff goes into telephony applications -- powered up for > (hopefully) years on end, no technicians around to press the "reset" > switch, so we ALWAYS have a microprocessor that scans the RAM array to > be sure it hasn't been corrupted. Do you have any stats on how often this corruption occurs ?? It is an interesting issue. > We use the venerable 8052, which just doesn't have enough room to hold > RAM array and verification information, so we use Xicor EEPROMs to hold > the Xilinx data (EPROMs consume too much space). Since they're > Electrically Eraseable, there's no waste, and Xicor makes Xilinx look > sick, price-wise. But, you can't reset them and stream-read them like > the Xilinx parts, so you HAVE to have a microprocessor. I'd love to use > the Xilinx EPROMs, if they could just cost in ... their interface is > admirably simple. Have look at the 89C2051 ( 20 pins ) and the new SPI DataFLASH from ATMEL. This has 4MBit Serial FLASH, at under ByteWIDE prices. - jim. -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Reusable object modules, for i2c, SPI and SPL bus interfaces = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55 = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 7246
This is a multi-part message in MIME format.
--------------5014FD7478
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The RAW Benchmark Suite, Version 1.0 is now available:
http://cag-www.lcs.mit.edu/raw/benchmark/README.html
Description:
The RAW benchmark suite consists of a set of programs and netlists
designed to
facilitate comparing, validating, and improving reconfigurable
computing systems. These benchmarks run the gamut of algorithms found
in general purpose computing, including sorting, matrix operations,
and graph algorithms. Each benchmark is designed in both C and
Behavioral Verilog
and parameterized to consume a range of hardware resource capacities.
This first release includes source code and 34 synthesized netlists in
the range
of a few thousand to 1 million gates.
Disclaimer:
These benchmarks are not designed to serve as a standard and have not
been selected to
represent any meaningful subset of actual programs or applications.
Jonathan Babb
jbabb@mit.edu
--------------5014FD7478
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Article: 7247
peter299@maroon.tc.umn.edu (Wade D. Peterson) wrote:
:>[snip]
:>Xilinx didn't lose a
:>EEPROM sale there: there never was one.
X
:Is XILINX selling EEPROMs yet (i.e. electrically erasable proms)?
:Last time I checked you had to buy Lucent parts if you wanted an
:electrically alterable one. The XILINX parts were all 'burn once and
:throw away'.
Sorry, my mistake. Indeed, the Xilinx parts are EPROM, while Atmel's
are EEPROM.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7248jim granville wrote: > > My stuff goes into telephony applications -- powered up for > > (hopefully) years on end, no technicians around to press the "reset" > > switch, so we ALWAYS have a microprocessor that scans the RAM array to > > be sure it hasn't been corrupted. > > Do you have any stats on how often this corruption occurs ?? > It is an interesting issue. Xilinx says practically forever -- days, months, years. I just never was left feeling like it wouldn't happen often enough to cause mysterious problems. In that scenario, traffic goes down, and eventually the card is replaced. Best case is a bunch of them come back to the factory No Problem Found (I HATE those). You can't debug it, because you can't get it onto an extender without resetting, and the problem is probably different every time (shudder...). > > We use the venerable 8052, which just doesn't have enough room to hold > > RAM array and verification information, so we use Xicor EEPROMs to hold > > the Xilinx data (EPROMs consume too much space). > > Have look at the 89C2051 ( 20 pins ) and the new SPI DataFLASH from > ATMEL. > This has 4MBit Serial FLASH, at under ByteWIDE prices. Yes, I've seen the recent discussion. I often need a few I/O pins, but I guess you can get that through the Xilinx, once it's operational. About how much does a low-end (slow, OTP) 89C251 cost? I have a pending (i.e., overdue) project I think it might fit into.Article: 7249
hi pete, this is an interesting topic and your post raises some interesting questions that we can discuss. please see the embedded comments denoted with '$$$$' although no mention of prom prices are mentioned ;^) rk ____________________________________ Peter Alfke <peter@xilinx.com> wrote in article <33F48D56.AA0982C1@xilinx.com>... > Richard B. Katz wrote: > > > hi dave, > > > > i have measured power consumption in a large number of fpga's, mostly > > actels. for most models, with no dc loads and static conditions and > > inputs at cmos levels, the current is less than 1 mA. > > If we want to discuss FPGA power seriously, we must make a few > distinctions:CPLD ( PAL-derived AND-OR circuits) are different from > FPGAs. $$$$ definitely different as the devices are very much different. the original $$$$ post in this thread discussed fpga power. my applications are typically $$$$ low power and i have had some good results in this regard. in general, though, $$$$ for low power apps it's not only a function of the technology but the use of $$$$ low power design techniques. > Dynamic power in FPGAs is much higher than their static power. $$$$ agreed. for the most part, static power is very, very low. like i said in the $$$$ original post, typically < 1 mA @ 5V, 25C. dynamic power obviously dominates. $$$$ just turning on a global clock net @ 32 MHz makes the static power irrelevant, $$$$ for example. for the amorphous silicon q-logic devices, the static currents $$$$ were higher, but still low w.r.t. high speed, dense designs. > > Almost all CPLDs ( Philips seems to be the only exception ) have > significant static power consumption even with all inputs and outputs > static. 500 mW is not uncommon, and it is documented in the data sheets. > This is static current in the read amplifiers and pull-up resistors used > in the array. It is an inherent feature of the way these devices > implement their AND array. > > Static power in FPGAs, be they SRAM or antifuse base, is very low. In > SRAM-based parts it is inherently in the microamp range. > The current can get into the milliamp range due to various auxiliary > linear circuits inside the chip: input threshold modifiers, bias pumping > circuits, voltage detectors etc. > Antifuse devices have more leakage current in their antifuses. $$$$ for the actels, the bias pump plays a key role in the static dissipation. $$$$ for example, the 2,000 gate a1020 takes considerably more power than the $$$$ 8,000 gate a1280. the a1280, according to the data book, has a two stage $$$$ pump design to minimize power dissipation after startup. with the ono $$$$ antifuse, temperature effects are minimal. for the q-logic amorphous silicon $$$$ antifuse devices, however, this may not be the case. for example, in the $$$$ q-logic data book reprint of the irps '94 reprint (wong and gordon), they $$$$ quote the following #'s for antifuse leakage: $$$$ prestress: 1 nA @ 20C $$$$ 50 nA @ 125C $$$$ now for the ono antifuse ["antifuse fpgas," proceedings of the ieee, 1993, $$$$ greene, hamdy, and beal], they quote a leakage of ~ 1E-15/antifuse. now, say $$$$ there are 1e6 *biased* antifuses, this would only produce 5 nW of power, $$$$ clearly negligible, so i'll disagree that antifuse devices have more leakage $$$$ in their antifuses, at least for the ono antifuse design. $$$$ $$$$ do you have some typical values for the xilinx devices with the auxiliary $$$$ circuits? can some others post for the other manufacturers? also, what is $$$$ the role of the bias pumping circuits in the xilinx devices? aren't there $$$$ tri-states internally to some fpga's? what is the value of the pull-up $$$$ resistors? > > The difference between 10 microamps and 15 milliamps is of concern only > to a small number of battery-operated designs with low clock frequency > or low duty cycle of operation. $$$$ actually, for designs, i see a lot of requests for lower power rather $$$$ than speed, although this is changing as the fpga's evolve and expand $$$$ their role in electronics. i would disagree with the "small number". $$$$ lately i have been designing in clock stopping circuits to go to a $$$$ minimum power mode where i want to keep everything static, use the high $$$$ pin count devices to implement bus hold circuits rather than pull-up $$$$ resistors for tri-state busses, maximize use of ripple counters, and have $$$$ even designed entire chips without getting on a global clock net, etc. $$$$ i see *a lot* of effort into low power designs and for high speed designs $$$$ ensuring that there is a low power sleep mode when the functionality is $$$$ not needed. of course, we're using low-power techniques even in high- $$$$ speed designs to avoid that nasty melting problem. for some systems, $$$$ btw, 15 mA (75 mW) would be a lot. > > The really serious issue is the dynamic power consumption of large > devices at high clock rates. Since both device size and clock frequency > are increasing, max power has increased from a watt to several, even > many, watts. > CMOS microprocessors, even when they run at 2.5 V, are now consuming > 10 to 30 W and need fancy cooling. > High-performance FPGAs are heading in the same direction, although the > move to 3.3 and then 2.5 V and then 1.8 V and then even lower, will > give all of us some reprieve. It is needed. $$$$ agreed. this is the tough case. dropping the voltage is essential. $$$$ and designs and architectures are critical too. i see the clock structures $$$$ supported by the fpga as key. for example, ripple counters are $$$$ lower power than synchronous ones - and some architectures don't support $$$$ the ripple counters. it's similar to what we used to do with cmos board $$$$ designs: minimize the capacitance per node and their switching frequencies. > > Heat removal will become a major concern for all high-performance CMOS > circuits, and may sometimes become the limiting factor for systems > integration. $$$$ interestingly, i see more and more chips being mounted cavity down in the $$$$ packages. good for systems cooled by convection; not so hot for systems $$$$ cooled by conduction. the xilinx packages i have looked at can be lead bent $$$$ (cqfp's) either side up, a nice mechanical design. > > The problem are the amps and watts, usually not the milliamps and > milliwatts. $$$$ i gotta disagree here too, a bit. i think the leading edge problems are the $$$$ amps and watts, no question. but there are still applications where 100 mW $$$$ to run a programmable device would result in a discrete cmos implementation. $$$$ comments? more info? interesting topic > > Peter Alfke, Xilinx Applications > > >
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