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The Xilinx data book, page 13-41 describes the circuit, all inside the chip. Peter Alfke, Xilinx ApplicationsArticle: 8276
Hi all (and paticularly Xilinx), I'm currently doing a design with XC4000XL and XC9500 parts and have been asked to estimate power consumption of the finished design. Xilinx on their web site does have an app note on how to estimate design power consumption, ands thats how I'll be doing it. However I also thought wouldn't it be great if part of the Xilinx software could estimate power consumption on a completed design, given the clock frequencies and a given load capacitance for the outputs. It would also be really useful if it could estimate a probable error. What do the other readers of this group think? ErikArticle: 8277
Charles,
I see that you are using the Design Compiler libraries from the
xdc_4000e-2.db library you have listed below. If this is true, then
replace_fpga is not to be performed on the design. Replace_fpga is only
for FPGA Compiler users only and is used in order to transform the CLB
and IOB primitives to regular cells to be written out in the
implementation netlist. I suggest you take a look at the sample script
for Design Compiler in $XILINX/synopsys/examples/template.dc.script if
you are using M1.x or $XACT/examples/synopsys/dc.script if you are using
XACT 5.x for examples of the synthesis flow for FPGAs.
Also, you library order is incorrect which may also cause problems. To
get a list of the libraries for a particular device, type synlibs -dc
<part> at the UNIX prompt. This is the proper library structure for
your device running Design Compiler :
For Xilinx M1.3.7:
link_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xdc_4000e-2.db xio_4000e-2.db}
target_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xdc_4000e-2.db xio_4000e-2.db}
define_design_lib xdw_4000e -path
/home/zeppelin2/tech_apps/m1_3.7/synopsys/libraries/dw/lib/xc4000e
symbol_library = {xc4000e.sdb}
synthetic_library = {xdw_4000e.sldb standard.sldb}
For XACT 5.2.1:
link_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xdc_4000e-2.db xio_4000e-2.db}
target_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xdc_4000e-2.db xio_4000e-2.db}
symbol_library = {xc4000e.sdb}
synthetic_library = {xblox_4000e.sldb standard.sldb}
If you did wiish to use Design Compiler, the proper libraries are found
by typing synlibs -fc <part> at the prompt. The proper library
structure is :
For Xilinx M1.3.7:
link_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xfpga_4000e-2.db xio_4000e-2.db}
target_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xfpga_4000e-2.db xio_4000e-2.db}
define_design_lib xdw_4000e -path
/home/zeppelin2/tech_apps/m1_3.7/synopsys/libraries/dw/lib/xc4000e
symbol_library = {xc4000e.sdb}
synthetic_library = {xdw_4000e.sldb standard.sldb}
For XACT 5.2.1:
link_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xfpga_4000e-2.db xio_4000e-2.db}
target_library = {xprim_4025e-2.db xprim_4000e-2.db xgen_4000e.db
xfpga_4000e-2.db xio_4000e-2.db}
symbol_library = {xc4000e.sdb}
synthetic_library = {xblox_4000e.sldb standard.sldb}
Also notice for all above library listing, there is and added library to
the synthetic library. You may ommit this if you do not wish to infer
designware components (arithmetic components that use architecture
specific features like the XC4000 carry chains) however I highly suggest
keeping it. If you do wish to use these, you will also need to add a
define_design_lib pointing to the proper path of the analyzed designware
libraries in the .syopsys_dc.setup file. See the examples of the setup
files for both Design Compiler and FPGA Compiler in the same directory
as I listed above for the script examples.
If you have any further questions try our answers search on the web,
http://www.xilinx.com/support/searchtd.htm There is a lot if
information in our answers database of this nature for Synopsys users.
Or look at the Xilinx-Synopsys docs,
ftp://ftp.xilinx.com/pub/documentation/interfaces/xsi_fpga.pdf
Or contact our technical hotline. We do have extensive support for
Synopsys users.
Regards,
-- Brian Philofsky
Xilinx Applications
Charles F. Shelor wrote:
> I've been doing ASICs for the last several years and have
> recently returned to the FPGA area. I have downloaded the
> XC4000 libraries from the Xilinx web site and successfully
> synthesized to a .db file with Synopsys. However, the
> "replace_fpga" command fails to translate the generic flip flops
> to their Xilinx equivalents. Haven't gotten anything useful
> from either company at this point. Was wondering if any other
> users have experienced a similar problem and have a solution
> they might want to share.
>
> The libraries that I use for the link and target libraries are:
>
> link_library = {xdc_4000e-2.db xfpga_4000e-2.db xio_4000e-2.db
> xgen_4000e.db xprim_4025e-2.db};
> target_library = {xdc_4000e-2.db xfpga_4000e-2.db xio_4000e-2.db
> xgen_4000e.db xprim_4025e-2.db};
> symbol_library = {xc4000e.sdb};
>
> Thanks,
>
> Charles
>
> --
> Charles F. Shelor charles@efficient.com
> Efficient Networks, Inc 'ATM for the Desktop'
> 4201 Spring Valley, Suite 1200 http://www.efficient.com/
> Dallas, TX 75244 (972) 991-3884
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
Article: 8278John Birkner (birkner@quicklogic.com) wrote: : name wrote in message <662ri3$bg9@news.Hawaii.Edu>... : >Is it possible to design into your system a graceful recovery? : No, How about 4 flip flops with staggered clocks, followed by four schmitt triggers, and a best 3 out of 4 vote resolver on their outputs ? The concept is that if the clocks are staggered beyond the range that temperature/process/voltage variation can move the critical window, then only one flip flop can ever go metastable. The vote taker would have to works something like this: if output is low transition to high when at least 3 inputs are high else (output is high) transition to low when at least 3 inputs are low so that the metastable flip flop is always out-voted. I guess this would fail if The clock rate is so high that there is no time to stagger the clock The meta flip flop glitched for a short enough period to throw the vote taker into a meta stable state What other flaws does this scheme have ? Graeme Gill.Article: 8279
Sam Goldwasser <sam@stdavids.picker.com> wrote in article <SAM.97Dec4104743@colossus.stdavids.picker.com>... > In article <01bd006e$c3525f80$12c4accf@mfc> "Michael F. Coyle" <mjcoyle@erols.com> writes: > > > While we're on the subject, is there a *simple* circuit to > > demonstrate metastability. I can rummage around in my > > junkbox for a slow flip-flop, say a 7474, or better yet, a > > 4013. > > Easy to demonstrate. Clock a 7474 with the clock applied to the D through > an adjustable delay set so the rising edge of the clock just trails a > transition on the D input. You will have to play with this but if you > get it just right, you will wonder who these things work at all! :-) > > You may have to search for that low gain FF to get really bad performance. > I remember doing this many years ago. It was interesting. There was one > problem I had to troubleshoot that turned out to be due to a low gain 7474. > > --- sam : Sci.Electronics.Repair FAQ: http://www.repairfaq.org/ > Lasers: http://www.geocities.com/CapeCanaveral/Lab/3931/lasersam.htm > Usually latest (ASCII): http://www.pacwest.net/byron13/sammenu.htm you might want to put two pots in, coarse and fine delay. hope this helps, ------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8280
Hi! Can you help me, please? I wish to simulate a project with external connections between pin in Altera`s MAX+Plus II. -- Sincerelly, Victor vic@alpha.PLDpodol.khmelnitskiy.ua Remove PLD in adress for e-mail me.Article: 8281
Have you used a set/reset flop? You can get a set or a reset but not both. When you write code that needs a set/reset D flop Synopsys will start to make it but then can't map it into a CLB. If you check the db file before replace fpga and it isn't all CLBs this might be your problem. Best Regards The DreamCatcherArticle: 8282
Erik de Castro Lopo wrote: > ...wouldn't it be > great if part of the Xilinx software could estimate > power consumption on a completed design, given the > clock frequencies and a given load capacitance for > the outputs. It would also be really useful if it > could estimate a probable error. YES! I have wished for this tool for years! -Steve GrossArticle: 8283
In article <01bd0136$748e8180$d080accf@default> "Richard B. Katz" <stellare_nospam@erols.com> writes:
RE: demonstation circuit for metastability.
> you might want to put two pots in, coarse and fine delay.
Yes, and the fine delay better be able to resolve much much less than a
nanosecond!
--- sam : Sci.Electronics.Repair FAQ: http://www.repairfaq.org/
Lasers: http://www.geocities.com/CapeCanaveral/Lab/3931/lasersam.htm
Usually latest (ASCII): http://www.pacwest.net/byron13/sammenu.htm
Article: 8284Hello Netland Engineers, I am just now discovering that it may be possible to design a Xilinx FPGA via OrCAD 7.0 schematic. Since I have, know, and use OrCAD 7 this would be a benefit for me to use it instead of another schematic tool, such as that bundled with Foundation. It looks like My question is this: Are there any traps waiting ahead for one that follows this path ? How smooth is the design flow with the rest of M1 ? -- George Pontis (Replies to geo at z9 dot com.)Article: 8285
In article <667os6$9vl@wallaby.digideas.com.au> graeme@wallaby.digideas.com.au (Graeme Gill) writes: >How about 4 flip flops with staggered clocks, followed by >four schmitt triggers, and a best 3 out of 4 >vote resolver on their outputs ? > >The concept is that if the clocks are staggered beyond the >range that temperature/process/voltage variation can move >the critical window, then only one flip flop can ever go >metastable. > >The vote taker would have to works something like this: > > if output is low > transition to high when at least 3 inputs are high > else (output is high) > transition to low when at least 3 inputs are low > >so that the metastable flip flop is always out-voted. > >I guess this would fail if > > The clock rate is so high that there is no time to > stagger the clock > > The meta flip flop glitched for a short enough period > to throw the vote taker into a meta stable state > >What other flaws does this scheme have ? schmitt triggers go metastable too. > >Graeme Gill.Article: 8286
Strongly agree. The topic comes up on this group now and then. Xilinx used to supply a crude power estimation utility as you describe, but it was unsupported and never got updated. Since (non-IO) power dissipation depends on switching activity of internal nodes and is hence very design and data dependant, the BEST solution would use a simulator with power estimation capability running a representive test vector set. Power estimation seems to be gradually becoming available on high-end simulators for ASICs, but I don't know if Xilinx tools can provide the node power data needed for these tools yet, or if a standard simulator netlist extension exists for this type of data. I would be very happy with a simple command line utility that would just take a routed LCA file and dump an ascii list of "node name" and "power cost per transition" (in picoJoules) pairs. Then I could do the rest with Excel, either manually assigning transition probabilities to groups of nodes, or automatically extracting them from simulator output. This would be preferable to a canned solution requiring a high-end simulator. I don't see why it would be hard for Xilinx to implement, unless they are reluctant to provide any implied guarantees on this data, don't know how to estimate node power cost, or don't see it as a priority. regards, tom Erik de Castro Lopo wrote: > > Hi all (and paticularly Xilinx), > > I'm currently doing a design with XC4000XL and XC9500 > parts and have been asked to estimate power consumption > of the finished design. > > Xilinx on their web site does have an app note on how > to estimate design power consumption, ands thats how > I'll be doing it. However I also thought wouldn't it be > great if part of the Xilinx software could estimate > power consumption on a completed design, given the > clock frequencies and a given load capacitance for > the outputs. It would also be really useful if it > could estimate a probable error. > > What do the other readers of this group think? > > ErikArticle: 8287
[ Article crossposted from comp.dsp ]
[ Author was Bob J. Conley ]
[ Posted on 5 Dec 1997 19:12:03 GMT ]
Please do not contact the poster of this message.
R&D ASIC Project Manager
-- Principles only (no agencies) please. --
Please respond with your cover letter and resume (E-mail preferred) to:
Ron Brazee
Hewlett-Packard Spokane Division M/S 3WU
24001 East Mission Ave.
Liberty Lake, WA. 99019
509-921-4345
E-mail: ron_brazee@hp-spokane-om2.om.hp.com (Subject: Attn: Ad # 5732)
________________________________________________________________
Job Title: R&D Project Manager
Department: Research & Development
Division: Spokane
City: Spokane
State: Washington
JOB FUNCTIONS:
Essential: (Major Responsibilities)
Manage team of Design Engineers assigned the responsibility of
providing ASIC and high speed digital designs in Communications Test
Equipment.
Actively work with R&D Lab Engineers, Project Managers, and
Section Managers to develop and execute a long term
Product/Productivity strategy for both ASICs (Digital, Analog,
and mixed mode) and Digital PC board designs and design
capabilities (both for the group itself and the part-time digital
designers elsewhere in R&D).
Other Duties: (Marginal Responsibilities)
Develop and implement the test and support strategies for ASICS,
and manage strategic CAE and foundry relationships.
SKILLS/KNOWLEDGE QUALIFICATIONS:
MUSTS - Minimum Degree/Experience
*Bachelor's degree or equivalent in Electrical Engineering, Computer
Science or related scientific disciplines.
*Minimum of three years of related (ASIC or high speed digital
design) design experience, including working familiarity with
requirements capture, behavioral (HDL) modeling, simulation,
design rule checks, synthesis, design for test, foundry
submission and sign off, semiconductor technology lifecycles,
and PC Board lifecycles.
*Demonstrated ability to manage/lead a group of technical
contributors, building the necessary skills and teamwork.
*Demonstrated ability to manage/lead a technical project
successfully, including the ability to build and maintain
effective working relationships across organizational &
divisional boundaries.
*Proven ability to exercise independent judgment.
DESIRED - Preferred Degree/Experience
*Masters Degree in Engineering or Computer Science preferred.
*Previous management/supervisory experience
*Familiarity with a subset of the following tools, device
processes, and standards: Synopsys, Mentor, Cadence, HPEEsof,
VHDL, event driven and cycle based simulation, floorplanning,
test insertion and ATPG, hardware modeling, ASIC emulation,
Spice, harmonic balance, high frequency structure simulation.
*Familiarity with broad range of ASIC technologies (CMOS, BiCMOS,
Bipolar, GaAs, and multi-chip modules) and digital board
families (VME, PCI, x86, 680xx), as well as digital signal
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*Previous experience coordinating applicable technology
improvements across Functional (and/or Divisional) boundaries
(e.g., use of HW/SW co-simulation to reduce integration effort,
simulation to reduce board or chip turns, etc.).
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_________________________________________________________________
Article: 8288Steve Gross <gross@pa.msu.edu> wrote: >Erik de Castro Lopo wrote: > >> ...wouldn't it be >> great if part of the Xilinx software could estimate >> power consumption Hi, At a recent seminar here in the UK, someone fron Xilinx mentioned that they had a (IIRC spreadsheet based) piece of software to do this, but only for one of their families of parts. I also gained the impression that there was some serious thinking going on about power consumption estimation. I also am interested in this due to a need to limit power consumption and push the envelope a little on ambient temperatures. Richard ------------Richard Dungan------------- Radix Electronic Designs, Orpington, UK Email: Richard.Radix@BTinternet.com --------------------------------------- Unsolicited Commercial Email is not welcome. Kill filters are in operation.Article: 8289
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Steve Gross wrote:
> Erik de Castro Lopo wrote:
>
> > ...wouldn't it be
> > great if part of the Xilinx software could estimate
> > power consumption on a completed design, given the
> > clock frequencies and a given load capacitance
>
> YES! I have wished for this tool for years!
>
Haven't we all !
Here is the problem, and thus the explanation for the lack of a good
tool.
Power is dynamic and follows the equation P = f • C • Vsquared.
Note that the transistor impedance does'nt affect power. Power
consumption is thus practically unaffected by the device
speed-grade, and is also not very temperature-dependent.
This power must be calculated for every node on the chip, and then
summed.
* V is the supply voltage ( at least in most cases, sometimes a
threshold less.)
* Xilinx knows C for every internal node ( otherwise we couldn't
calculate delays ).
* The devil is in the frequency.
In order to calculate power, one has to know the switching frequency of
each and every node on the chip, plus the outputs. That means, one has
to start with the operational statistics of each input. That means
statistically relevant input vectors, from which one then can calculate
the internal activities on a few ten-thousand nodes, multiply each by
its capacitance and voltage-sqared, and sum it up.
That means, you need to know the system activities. The LCA or XNF or
EDIF file is useless. For timing analysis and timing simulation, you
usually restrict yourself to known critical areas ( like the carry
propagation delay in a long counter ), but that isn not useful for power
calculations.
It has been suggested to do rough estimates. That isn't meaningful
either:
Plus-minus 30 percent would span an almost two-to-one ratio. Maybe
that's good enough for calculating battery life, but it is worthless for
thermal problems. Depending on power and thermal impedance, the junction
temperature falls somewhere between ambient and 85, 100, 125 or perhaps
150 degrees. A two-to-one error is not acceptable.
Luckily it is relatively easy and inexpensive to do realistic
experiments with FPGAs, as opposed to ASICs where you cannot recover
from a power mistake.
We will keep publishing the "atomic" ingredients of power consumption,
and we will improve them and make them easier to understand and to use.
But I do not believe in the great Altera simplification that "everything
behaves like a 16-bit counter, so assume that 12.5% of the circuit
toggles at the clock rate". I have seen designs where that percentage
was much lower, and others where it was approaching 50% ( highly
pipelined DSP designs ).
I wish things were simpler, but they aren't.
Peter Alfke, Xilinx Applications
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<BODY BGCOLOR="#FFFFFF">
Steve Gross wrote:
<BLOCKQUOTE TYPE=CITE>Erik de Castro Lopo wrote:
<P>> ...wouldn't it be
<BR>> great if part of the Xilinx software could estimate
<BR>> power consumption on a completed design, given the
<BR>> clock frequencies and a given load capacitance
<P>YES! I have wished for this tool for years!
<BR> </BLOCKQUOTE>
Haven't we all !
<BR>Here is the problem, and thus the explanation for the lack of a good
tool.
<P>Power is dynamic and follows the equation P = f • C • Vsquared.
<UL>Note that the transistor impedance does'nt affect power. Power consumption
is thus practically unaffected by the device speed-grade, and is also not
very temperature-dependent.</UL>
This power must be calculated for every node on the chip, and then summed.
<BR>
<UL>
<LI>
V is the supply voltage ( at least in most cases, sometimes a threshold
less.)</LI>
<LI>
Xilinx knows C for every internal node ( otherwise we couldn't calculate
delays ).</LI>
<LI>
The devil is in the frequency.</LI>
</UL>
<P>In order to calculate power, one has to know the switching frequency
of each and every node on the chip, plus the outputs. That means, one has
to start with the operational statistics of each input. That means statistically
relevant input vectors, from which one then can calculate the internal
activities on a few ten-thousand nodes, multiply each by its capacitance
and voltage-sqared, and sum it up.
<P>That means, you need to know the system activities. The LCA or XNF or
EDIF file is useless. For timing analysis and timing simulation, you usually
restrict yourself to known critical areas ( like the carry propagation
delay in a long counter ), but that isn not useful for power calculations.
<P>It has been suggested to do rough estimates. That isn't meaningful either:
<BR>Plus-minus 30 percent would span an almost two-to-one ratio. Maybe
that's good enough for calculating battery life, but it is worthless for
thermal problems. Depending on power and thermal impedance, the junction
temperature falls somewhere between ambient and 85, 100, 125 or perhaps
150 degrees. A two-to-one error is not acceptable.
<P>Luckily it is relatively easy and inexpensive to do realistic experiments
with FPGAs, as opposed to ASICs where you cannot recover from a power mistake.
<P>We will keep publishing the "atomic" ingredients of power consumption,
and we will improve them and make them easier to understand and to use.
But I do not believe in the great Altera simplification that "everything
behaves like a 16-bit counter, so assume that 12.5% of the circuit toggles
at the clock rate". I have seen designs where that percentage was much
lower, and others where it was approaching 50% ( highly pipelined DSP designs
).
<P>I wish things were simpler, but they aren't.
<P>Peter Alfke, Xilinx Applications
<P>
</BODY>
</HTML>
--------------3F004B72E17DA4856ED56A75--
Article: 8290
HeHeHe..... You will never be able to GUARANTEE a problem free solution
for a synchronizer.
However, you can probably push the probability of it happening to 1 part
in the age of the universe expressed in femtoseconds or lower :-) with
enough complexity and if you are willing to wait. Any scheme, no matter how
sophisticated or elegant, could fail given an appropriate combination of
unlikely circumstances!
There are always asynchronous (unclocked) systems!
--- sam : Sci.Electronics.Repair FAQ: http://www.repairfaq.org/
Lasers: http://www.geocities.com/CapeCanaveral/Lab/3931/lasersam.htm
Usually latest (ASCII): http://www.pacwest.net/byron13/sammenu.htm
Article: 8291In article <01bd006e$c3525f80$12c4accf@mfc>, Michael F. Coyle <mjcoyle@erols.com> wrote: >While we're on the subject, is there a *simple* circuit to >demonstrate metastability. I can rummage around in my >junkbox for a slow flip-flop, say a 7474, or better yet, a >4013. In 'High Speed Digital Design' by Johnson and Graham. 'Observing Metastable States' section 3.11, Page 120. Mark Zenier mzenier@eskimo.com mzenier@netcom.comArticle: 8292
Peter Alfke wrote: > > Steve Gross wrote: > > Erik de Castro Lopo wrote: > > > ...wouldn't it be > > great if part of the Xilinx software could estimate > > power consumption on a completed design, given the > > clock frequencies and a given load capacitance > > YES! I have wished for this tool for years! <snip> > Power is dynamic and follows the equation P = f • C • Vsquared. > It has been suggested to do rough estimates. That isn't meaningful > either: > Plus-minus 30 percent would span an almost two-to-one ratio. Maybe > that's good enough for calculating battery life, but it is worthless > for thermal problems. Depending on power and thermal impedance, the > junction temperature falls somewhere between ambient and 85, 100, 125 > or perhaps 150 degrees. A two-to-one error is not acceptable. > Peter Alfke, Xilinx Applications Maybe if your target is CHIP TEMP within 1 deg, but it would be VERY useful to have a indicator, so you could get TREND feedback. - ie is todays design LOWER POWER than Last weeks ?! For this, you could do useful, and indicative calculations 1) Power based on ALL CLOCK nodes, at Fc, and with ALL FF's ClkEnable = FALSE. This is a MINIMUM number, and also encourages Chip vendors to make the lowest power sync-disabled instance Registers. This numder INCLUDES the internal power lost in a FF, that is clocking, but whose output is NOT changing. 2) Power based on ALL CLOCK nodes, at Fc, and ALL FF's toggling. This is a MAXIMUM number - not a real world one, but still usefull, as it shows the power cost of Activity. A straight line ratio between the two can be used, to get a better real chip fit. 3) And, if you like, one in between, where the user can specify a BLOCK to enable / disable. I would be happy with 1) and 2) - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD IP Libs ========= = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 8293
Graeme Gill wrote in message <667os6$9vl@wallaby.digideas.com.au>... >How about 4 flip flops with staggered clocks, . . > . . and a best 3 out of 4 vote resolver on their outputs ? > . . then only one flip flop can ever go metastable . . The "flaws does this scheme have" is that there will always be an instant of time when the "resolver" is seeing 2 outputs transitioning to 3 outputs and the resolver will be metastable. This analogous to creating perpetual motion from water flowing over a dam to a generator that produces electricity that drives a pump to pipe the water back to the lake which flows over the dam to a generator . . . John Birkner, QuickLogicArticle: 8294
Article: 8295
Graeme Gill (graeme@wallaby.digideas.com.au) wrote: > John Birkner (birkner@quicklogic.com) wrote: > : name wrote in message <662ri3$bg9@news.Hawaii.Edu>... > : >Is it possible to design into your system a graceful recovery? > : No, > How about 4 flip flops with staggered clocks, followed by > four schmitt triggers, and a best 3 out of 4 > vote resolver on their outputs ? > The concept is that if the clocks are staggered beyond the > range that temperature/process/voltage variation can move > the critical window, then only one flip flop can ever go > metastable. > What other flaws does this scheme have ? > Graeme Gill. Lets say the input doesn't change during that time. Even with staggered clocks, you would be latching 4 metastable values. Of course, thats theoretical. But what happens when two DFF say the value is high, 2 say it is low? How can you even tell if you have a deadlock? GREGArticle: 8296
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In article <1997Dec2.105705@phobos.gent.bg.barco.com>, kho@phobos.gent.bg.barco.com (Kim Hofmans) wrote: >I'm having a hard time with the UCF files. > >I created a UCF file with the pad constraints, >e.g INST "FFTROE_N" LOC = "P127"; > >At the beginning, when implementing the design in the design manager, >all the instances were found. >After several times implementing the same design with the same UCF file, >the design manager didn't find the signals anymore. >I didn't modify the UCF file or the padnames in my design. > I have a similar (same?) problem with one of my I/O signals. It seems to have originated with my move to M1, but I can't say that I under- stand why. In my case, the signal going to the pin in question is renamed in the EDIF file i.e. for some reason the signal name is linked to or replace by a generic numbered net name. After getting no particular insight from Xilinx, my solution is to search the EDIF file and extract the new net name and enter that into the UCF pad constraint. I have always been using Synopsys tools, but I upgraded to 3.5 at roughly the same time I went from XACT to M1. Going back to figure out whether Synopsys is doing something new or M1 is more sensitive to input is not yet high on my list. DanArticle: 8298
I agree. This is an area where all the programmable logic vendors (and their EDA partners) have work to do, and I suspect what we're both looking for will eventually appear (as it has for ASICs). See my article in EDN's August 1, 1997 issue at www.ednmag.com. > ...wouldn't it be > great if part of the Xilinx software could estimate > power consumption on a completed design, given the > clock frequencies and a given load capacitance for > the outputs. It would also be really useful if it > could estimate a probable error. Brian Dipert Technical Editor EDN Magazine: The Design Magazine Of The Electronics Industry 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** Visit me at <http://members.aol.com/bdipert>Article: 8299
>The Antique PDS2XNF you are using is probably one of the worst ways to >build state machines for Xilinx chips. I would highly recomend you look >at schematic based, one hot state machines, for performance, density, and >simultion with the rest of your design. Philip, Thanks for your long reply. I can see your points but I cannot afford the cost of "up"-grading given the low volume of FPGA work which I now do. As regards CUPL -> PDS2XNF -> XNF this is actually fine for state machines. All one does is draw a top-level sheet in Viewlogic, dump a block into the middle of the page (representing the state machine, define all the pins and IOBs, add any other circuitry needed, generate an XNF file, and thereafter all the state machine work is done in CUPL. Later, if doing CUPL-only FPGA designs, the XNF file produced from that top-level sheet can be re-used, without any need to revisit Viewlogic. Simulation works fine, too. I know the advantages of one-hot state machines w.r.t. the peculiar features/limitations of FPGAs but I would never use them otherwise. I also do a lot of 22V10-based state machines, and of course there one does an encoded state machine. I have just done a really complex design in a 22V10 which *could* run at 110MHz and draw 30mA. In fact it runs at 1MHz (and draws ~0.5mA, in a Philips P5Z22V10, $4) and this just shows that one-hot designs are certainly not always appropriate, because the FPGA might be run slowly. The only other reason for using one-hot designs is that one can feasibly do the design as a schematic whereas only a masochist would be doing an encoded design in schematic form :) I like CUPL because I can use the same tool for GALs and for FPGAs. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.
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