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Messages from 101550

Article: 101550
Subject: boundary scan through Virtex
From: "boru" <aborundiya@gmail.com>
Date: 2 May 2006 20:01:58 -0700
Links: << >>  << T >>  << A >>
hi all,
I have a interface board developed and am trying to configure it but it
give me error :565 saying error at bit position '1' check ur power
supply, cable etc,,,,,,, i am sure that all thing s are good
can anybody help....


Article: 101551
Subject: Re: 50-th Anniversary of the CORDIC Algorithm
From: Ray Andraka <ray@andraka.com>
Date: Tue, 02 May 2006 23:06:11 -0400
Links: << >>  << T >>  << A >>
vladimir@baykov.de wrote:
>  50-th Anniversary of the CORDIC  Algorithm
> 
> 
> So I suggest firstly to create  the list of the bibliography in the
> CORDIC field, like it was done in 1995 (now unfortunately it is a dead
> link):
> 
> http://devil.ece.utexas.edu/cordic/index.html
> 

I have a print out of this bibliography somewhere in my files.  I 
haven't had a chance to transcribe it into an on-line bibliography.

I do have a short bibliography of a few dozen CORDIC references on my 
website at http://www.andraka.com/bibliog.htm



Article: 101552
Subject: Re: Book Software for XC3190A?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 02 May 2006 23:18:15 -0400
Links: << >>  << T >>  << A >>
Josh Rosen wrote:


> Software support for the 3000 series was dropped years ago. What's the
> copyright date on the book that you are looking at? If the copyright is
> from the early to mid-90s then the included software will support the 3000
> series. If the book has been updated in recent years the chances are they
> have a slightly obsolete version of Webpack included which won't support
> the 3000 series. If the book is from the early 90s, what media are the
> included tools on? Early 90s PCs had 5 1/4" floppies, good luck finding a
> 5 1/4" floppy drive. If it's on 3 1/2" floppies then you'll be able to
> read them because 3 1/2" drives are still available, your system might
> even have on if it's more than 2 years old. If the software is on a CDROM
> that's a sure indicator that it won't have 3000 series support. By the
> time that CDROMs became the standard means of distributing software
> support for the 3000 series had already been dropped.
> 


You'll need the hardware dongle to run the software too, along with 
either DOS or win3.1, depending on which version of the software you 
have.  On top of that, the dongles and software don't run on today's 
faster machines.  You'll probably have to resurrect an old system 
slower/older than a pentium 166 to get it to work.  I am pretty sure the 
last two versions of Xact that supported the 3100 series did come on 
CDs, but you still needed the parallel port dongle to activate the 
software.  Good luck finding one of those.

For quite a while, the 3100 series was compelling even though it was 
obsolete for very low power designs because of its low static 
dissipation.  That is no longer true.  I can't think of any good reason 
to use a 3100 series part now.  Even free, they are too expensive to use 
and rather primitive compared with what you can get today for just a few 
dollars.

Article: 101553
Subject: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
From: Ray Andraka <ray@andraka.com>
Date: Tue, 02 May 2006 23:29:35 -0400
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

> Hi all
> 
> I am looking for ideas for: "FPGA Single LED Demos", The requirements for 
> the demo Application are following:
> 
> * Display visible 'sign of live' or 'self-test passed' message
> * Impemented in FPGA Vendor neutral HDL
> * <= 3000 LUT
> * <= 4KB of Block RAM
> * uncalibrated (+-50%) high frequency oscillator
> * 1 user LED for display
> 
> The Demo application should have some sort of LED visible 'message' to 
> indicate the demo is working or has passed internal self test code. There is 
> no user interface byeound one single LED.
> 
> Current list of Applications
> ==================
> 1) LED Blink (MSB of counter) - VHDL
> 2) LED Blink (MSB of counter) - Verilog
> 3) LED Blink (MSB of counter) - MyHDL (Python)
> 4) LED Fade with PWM (waveform from counter bits)
> 5) LED Fade with Delta-Sigma DAC (waveform from counter bits)
> 6) LED Fade with DDS and Delta-Sigma (waveform from ROM Table)
> 7) PacoBlaze LED Blink with Assembler Program
> 8) PacoBlaze LED Blink with C Program
> 9) SPoC(bit-serial-processor) LED Blink with Assembler Program
> 8) AVR like MCU LED Blink with Basic Program
> 10) PIC like MCU LED Blink with Assembler Program
> 11) C16 (16 Bit CPU) LED Blink with C Program
> 12) LED Blink with 32-bit Programmable Micro-Sequencer
> 13) Frequency Measurement demo (use stop watch and calculator)
> 14) ? your idea ?
> 
> The above is my current list of demo applications, I am considering some 
> more soft-core CPU's, but all those demos would be very similar to the 
> existing soft-core demos. So any ideas to demo some other functionality are 
> welcome.
> 
> Best ideas can be rewarded with an FPGA evaluation board (with your idea 
> pre-programmed). Suggestions a-la "soft-core cpu acme/xyz" will not count.
> 
> Antti
> 
> 
> 
> 
> 

Replace or parallel the LED with an IR LED and use it to make a TV 
disrupter that randomly changes the channels, turns down the volume, or 
turns off the TV via the TV's IR remote reciever ;-)

Article: 101554
Subject: detailed description on the archetecture of FPGA's/CPLD's
From: "Guru Prasad" <guruprasad@rassit.com>
Date: Tue, 2 May 2006 21:38:04 -0700
Links: << >>  << T >>  << A >>
Hello,

I am verry new to this Field and i would be verry happy if anybody would sujjest me a link or any document which gives me an idea on what an FPGA/CPLD is and its arcitecture,how a vhdl code is actually implmented in these... Regards, Guru Prasad

Article: 101555
Subject: Table-lookup CORDIC
From: vladimir@baykov.de
Date: 2 May 2006 22:25:18 -0700
Links: << >>  << T >>  << A >>

Table-lookup implementation of CORDIC


    The idea of unification of CORDIC and table-lookup is the follo-
wing: taking leftmost m  bits of the argument X  ( for example for fu-
nction sin X ) and using them as a input address of ROM with the
capacity
2**m words we can skip the first m iterations and begin from (m+1)-th
iteration taking the table values as  the initial values of iterative
variables.
The total number of iterations in that case is (n-m) , where n - word
length.
Correspondingly the number of table constants (arctan, ln) de-
creased on m.
We considered and verified that approach for trigonometric, hyperbolic,

and exp, log, and sqrt  functions.

   That approach can be completed by stopping of iterations on n/2-th
iteration, suggested by T.C.Chen in 1972, and consequent linear inter-
polation. In such case , unifiing that with table-lookup approach
the total number of iteration is (n/2-m).

If for example n=24, m=8 we should execute only 4 iterations.

All the detailes of the implementation of this approach you
can find in:

1. Analyse of the table lookup and table-algorithmic methods of the
elementary functions evaluation. V.Baykov, V.Smolov ,  Published  in
The Journal  "Electronic modeling"  (Engineering Simulation) 1980, N1,
p.22-27
This journals  are translated  into English in the USA, since 1981
http://www.rql.kiev.ua/electr_model/.

2. The book:    Special-purpose processors:iterative algorithms
and structures"  pages: 134-143 (Vladimir Baykov,  Vladimir Smolov),
Moscow, 1985
(this book in 1988-1995 was sent to many American and European
scientists who are working in the Computer Arithmetic area)
http://baykov.de/Cordic1985.htm

3.  and in  the Usenet group   comp.arch. arithmetic  at  16 Juini 1995
in:
http://groups.google.com/groups?hl=ru&q=baykov%20cordic&btnG=%D0%9F%D0%BE%D0%B8%D1%81%D0%BA&lr=&sa=N&tab=wg


Article: 101556
Subject: Re: EDK and SYSGEN
From: "Fizzy" <fpgalearner@gmail.com>
Date: 2 May 2006 22:46:55 -0700
Links: << >>  << T >>  << A >>
I thought about APU but its kind a hard because all i want to do is to
hook my SYSGEN based model to PLB. I am sure there must be a easier way
its just i ma not aware


Article: 101557
Subject: Re: Quartus and source control
From: David Brown <david@westcontrol.removethisbit.com>
Date: 3 May 2006 08:57:08 +0200
Links: << >>  << T >>  << A >>
Subroto Datta wrote:
> For clarification purposes, I did not say that the .qws file should not be 
> versioned, or cannot be stored in a source code control system. It was 
> important to point out that you will need to take some steps to preserve its 
> integrity if you store it in a version control system.
> 
> - Subroto Datta
> Altera Corp.
> 

You don't need to uuencode a binary file to store it in a version 
control system, at least not the ones I've used (cvs and subversion). 
Something like RCS may need to use text files, since (I believe) it 
modifies the files themselves, but it hardly counts as a modern source 
code control system.  With cvs, there are a couple of gotchas regarding 
binaries, but subversion handles them smoothly and efficiently.


> "David Brown" <david@westcontrol.removethisbit.com> wrote in message 
> news:44574c78$1@news.wineasy.se...
>> pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:
>>> Subroto Datta <sdatta@altera.com> wrote:
>>>> Quartus files can be stored in any source code control system. All 
>>>> source files needed to create and compile a project are text files. We 
>>>> have customers and internal users  who have versioned Quartus projects 
>>>> with CVS, Clearcase, Perforce, RCS.... The only binary file is the .qws 
>>>> (workspace file) files that contains the locations of the window 
>>>> settings when the Quartus UI executable (quartus.exe) is closed..The 
>>>> .qws file is not needed for compilation.
>>> One can use uuencode the .qws file to get it into a source code control 
>>> system.
>>>
>> Can't you just store the binary in the source code control?  Obviously you 
>> can't compare versions in the same way as for text files, but you couldn't 
>> do that with uuencoded files anyway.  Certainly subversion should have no 
>> problem storing binary qws files - I don't know about any other systems.
>>
>>> Btw, why is there no webpack linux offering like xilinx have?
>>>
> 
> 

Article: 101558
Subject: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
From: Tommy Thorn <foobar@nowhere.void>
Date: Tue, 02 May 2006 23:59:30 -0700
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> Hi all
> 
> I am looking for ideas for: "FPGA Single LED Demos", The requirements for 
> the demo Application are following:
> 
> * Display visible 'sign of live' or 'self-test passed' message
> * Impemented in FPGA Vendor neutral HDL
> * <= 3000 LUT
> * <= 4KB of Block RAM

Thanks for a good question leading to many fun ideas (using an LED as a 
sensor is a good one).

I'm surprised none have suggested my personal favorite: a (human) heart 
beat.  Display the ECG curve with the LED intensity (via Delta-sigma 
pulse density modulation).  A flat-liner always on or off are two 
failure modes, whereas the heart rate can correspond to various phases. 
  For extra credit, modulate the LED such that it makes an interesting 
sound if played of a [piezo] speaker.

Are you going to show of the board that motivated this quest?

Cheers,
Tommy

Article: 101559
Subject: Re: Virtex-4 Gigabit Ethernet design
From: David <david.quinones@imagsa.com>
Date: Wed, 3 May 2006 00:28:48 -0700
Links: << >>  << T >>  << A >>
Yes, these are the great disadvantages of the UC-II design. The work flow is different like the XPS work flow, and the modification of the design must be do with ISE, but that is simply another way of work. You can choose:  XPS work flow: very compatible, with a great quantity of memory, with the PLB and OPB buses but with a great consumption of resources.  UC II designs: You have a lot of resources avalaible and the 32 Kb of memory are cache, the fastest possible, but the work flow it's a low level work flow but there exists options to expand the design.

I have introduced some modifications to the TEMAC UCII design. I will inform about the results

Regards

Article: 101560
Subject: Re: Someone need to port LwIP to ll_temac core/wrapper?
From: David <david.quinones@imagsa.com>
Date: Wed, 3 May 2006 00:58:15 -0700
Links: << >>  << T >>  << A >>
Hi Marco

What about the MPMC 2 component? Do you know if the GSRD has been updated?

Regards

Article: 101561
Subject: How to open an ISE 8.1 project in ISE 7.1?
From: "Rainier" <sutongqi@gmail.com>
Date: 3 May 2006 01:05:17 -0700
Links: << >>  << T >>  << A >>
I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible.
and there's even no compatibility property in the save option.

My project has verilog, vhdl, schematic and coregen files.

thanks.


Article: 101562
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: "Dave" <doomeddave@yahoo.co.uk>
Date: 3 May 2006 01:09:31 -0700
Links: << >>  << T >>  << A >>
Hi Jeff,

Sounds interesting.  Unfortunately, the input clock will sometimes be
lower than 1MHz and the output must be > 24MHz so a DCM cannot be used
at all.

I see there is a reset pin on the DCM.  I assume the procedures for
reset are to stop using the output clock when it is messed up, assert
reset and wait for a good clock again before using teh output once
more?

Many thanks,

Dave


Article: 101563
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: "Dave" <doomeddave@yahoo.co.uk>
Date: 3 May 2006 01:12:36 -0700
Links: << >>  << T >>  << A >>
Hi Jim,

What is required is to generate 2x, 4x and 8x clocks from the input.
Could be done using 3 DCMs (assuming in range inputs/outputs) each
doing 2x.

The appropriate clock would then be selected and used.

Your method of generating 8 edges sounds cool but I think a regular
clock will be required rather than a bursty one.

Cheers,

Dave


Article: 101564
Subject: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
From: "Antti" <Antti.Lukats@xilant.com>
Date: 3 May 2006 01:14:04 -0700
Links: << >>  << T >>  << A >>
Hi Tommy,

actually the board is visible in the website header at
http://www.xilant.com

displayed is second proto for the gadget (first on was with TQFP144
package) as on the picture it is powered from USB SD Card reader and it
is controlling an small 3V DC motor directly from FPGA pins - the motor
is plugged in into Sipsik(tm) extension slot :)  At the time of taking
that picture the motor was spinning and changed directions every few
seconds, its audible at change points otherweise the motor runs very
quiet.

The LED in question is at the top left corner of the FPGA (not lit on
the picture)

Lower connector is JTAG, that can also be used for user IO, and also
allows self reprogramming over SD/MMC connector, using a Card reader.
The module is designed to be shipped with an Book so getting costs down
are essential.

For the Book-PCB the FPGA will be preprogrammed with SoftCore processor
and MMC Card Side IP Core that allows the Processor code to be
downloaded (the gadget is visible as removable media for PC) from Host.
Of course the on-chip Processor has acccess to the LED, to the USER IO
slots and can communicate  with the host, by having a shared buffer
that can be read write from the host.

Of course the PCB can be used as standalone or with anything that has
MMC/SD card slot, a PDA or MP3 player.

Currently I am considering having AVR Core as default SoC for the
pre-programmed version, and the Book DVD will include AVR Basic
compiled re-targetted for this Flash-FPGA-AVR and utilitites to compile
and download programs to the unit.

So almost all the LED suggestions would be easy to implement as
software solutions and would not even require a new configuration of
the FPGA.

What I am still looking for are more different applications that
demonstrate the FPGA itself, the endless possibilities of the user
programmable logic.

Antti Lukats
Xilant Technologies.

PS the board that is going to be actually shipped with the Book will
not be any more made with laser printer of course :) - I just had
it urgent to get the design tested, so made different attempts to
make the PCB at home, all those are also described in the book too.

Ah and all the designs(sch+PCB, gerber) and IP cores used as demo will
be included with the Book, this includes licensing for the IP cores
specially developed for it - MMC Card side IP core, one bit Logic
Analyzer with JTAG acces and MMC/SD card protocol analyzer software
that developed during testing, etc, etc...


Article: 101565
Subject: Re: How to open an ISE 8.1 project in ISE 7.1?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 3 May 2006 01:15:04 -0700
Links: << >>  << T >>  << A >>
you cant.
recreate the project from scratch and add your files manually if you
really need it

Antti


Article: 101566
Subject: Re: OPB Clocking Question
From: "Guru" <ales.gorkic@email.si>
Date: 3 May 2006 02:33:42 -0700
Links: << >>  << T >>  << A >>
Dear motty,

OPB peripherals MUST use the same (syncronous) clock, which should
probably not exceed 100 MHz. I suggest you do the conversion of data
from clk2x to clk (or from clk to clk2x) by adding a data mux. In this
way you get 32 bit data (OPB standard) from 16 bit data. If you want to
use a high-speed burst transfer (32bytes transfer/OPB_cycle) adding a
asyncronous fifo is almost inevitable.

Cheers,

Guru


Article: 101567
Subject: Re: Improvement suggestions for Xilinx ChipScope
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 03 May 2006 11:45:50 +0200
Links: << >>  << T >>  << A >>
Symon schrieb:
> Hi Weng,
> I'm not so concerned about the user interface. Although that Java stuff is 
> bloody slow!
> What ChipScope really needs is a clock enable connection to go with the 
> clock. That way it can be used and meet timing whatever your clock rate. (Or 
> at least do much better than it does currently.)
> Cheers, Syms. 

An chipscope really should autotrigger once on startup. Otherwise it is
impossible to debug reset issues.

Kolja Sulimma

Article: 101568
Subject: Re: 50-th Anniversary of the CORDIC Algorithm
From: "henk" <henk@mediatronix.com>
Date: 3 May 2006 03:13:55 -0700
Links: << >>  << T >>  << A >>
Did you mean this:
http://web.archive.org/web/20001017173921/http://devil.ece.utexas.edu/
Henk van Kampen


Article: 101569
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 03 May 2006 22:34:42 +1200
Links: << >>  << T >>  << A >>
Dave wrote:
> Hi Jim,
> 
> What is required is to generate 2x, 4x and 8x clocks from the input.
> Could be done using 3 DCMs (assuming in range inputs/outputs) each
> doing 2x.
> 
> The appropriate clock would then be selected and used.
> 
> Your method of generating 8 edges sounds cool but I think a regular
> clock will be required rather than a bursty one.

  You have not defined what 'clock rate variations' will be.
  A regular locked multiple is only possible with a regular
referance IP. Wobble the IPs and the DCMs will chase their tail
trying to follow....
  So, you will need to nail down the dF and Slews (dF/dT) and also when 
it does, and does not, have to follow with 8x outputs - and then try
some designs.
-jg


Article: 101570
Subject: Re: 50-th Anniversary of the CORDIC Algorithm
From: vladimir@baykov.de
Date: 3 May 2006 03:37:40 -0700
Links: << >>  << T >>  << A >>
Did you mean this:
http://web.archive.org/web/20001017173921/http://devil.ece.utexas.edu/
Henk van Kampen 


YES!!!   Thanks a lot, Henk for your help.
Vladimir


Article: 101571
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: "Dave" <doomeddave@yahoo.co.uk>
Date: 3 May 2006 03:50:32 -0700
Links: << >>  << T >>  << A >>
>   You have not defined what 'clock rate variations' will be.
>   A regular locked multiple is only possible with a regular
> referance IP. Wobble the IPs and the DCMs will chase their tail
> trying to follow....
>   So, you will need to nail down the dF and Slews (dF/dT) and also when
> it does, and does not, have to follow with 8x outputs - and then try
> some designs.

Hi Jim,

The input clock may be as low as 200 kHz and as high as 20-30MHz
perhaps.  The frequency will be fixed at a certain frequency while the
system runs however (i.e. it is not going to swing around in that
range!).

The issue is that 2x, 4x and 8x are required.  The minimum output of
the DCM when using CLKFX is 24MHz so 12MHz is the minimum input but
downto 200kHz as input is required.  Also, 1MHz is min input of DCM and
lower freqs than this may be used.  So, DCMs cannot be used.

Many thanks for your help,

Dave


Article: 101572
Subject: Re: detailed description on the archetecture of FPGA's/CPLD's
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Wed, 03 May 2006 12:21:54 +0100
Links: << >>  << T >>  << A >>
go to one of the main PLD/FPGA vendors websites and take a look, 
download some datasheets and/or application notes.
or just google for "FPGA". If you able to post a message here, it means 
you have access to internet, so just spend some time learning
Have fun,
Aurash

Guru Prasad wrote:
> Hello,
> 
> I am verry new to this Field and i would be verry happy if anybody would sujjest me a link or any document which gives me an idea on what an FPGA/CPLD is and its arcitecture,how a vhdl code is actually implmented in these... Regards, Guru Prasad

Article: 101573
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 03 May 2006 13:43:05 +0200
Links: << >>  << T >>  << A >>
Dave schrieb:
> The input clock may be as low as 200 kHz and as high as 20-30MHz
> perhaps.  The frequency will be fixed at a certain frequency while the
> system runs however (i.e. it is not going to swing around in that
> range!).
> 
> The issue is that 2x, 4x and 8x are required.  The minimum output of
> the DCM when using CLKFX is 24MHz so 12MHz is the minimum input but
> downto 200kHz as input is required.  Also, 1MHz is min input of DCM and
> lower freqs than this may be used.  So, DCMs cannot be used.

If you can live with a few ns jitter you can digitally synthesize the
clocks from an additional fast clock.

Kolja Sulimma

Article: 101574
Subject: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
From: "Dave" <doomeddave@yahoo.co.uk>
Date: 3 May 2006 04:47:00 -0700
Links: << >>  << T >>  << A >>
> If you can live with a few ns jitter you can digitally synthesize the
> clocks from an additional fast clock.

Hi Kolja,

Do you mean take a fast clock and clock some counters to generate
enables or something more fancy?

Dave




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1994JulAugSepOctNovDec1994
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1998JanFebMarAprMayJunJulAugSepOctNovDec1998
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