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Dan wrote: > I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn the device on the red LED 'Err' turns on. The CF card has to be formatted properly. Try if downloading one of the reference CF images from http://www.xilinx.com/products/boards/ml402/reference_designs.htm works properly. If you must reformat, then use a Linux or Win2k machine, or mkdosfs to format the disk. WinXP changed the way DOS formatting is done, and such CF's will not work with Sytem ACE. /SivaArticle: 105251
Brian McFarland wrote: > Any comment's regarding PCI compliance, ease of use, compatability with > Altera parts, etc? I've used the opencores PCI core on an Altera Cyclone II (EP2C35) dev board. No implementation/compatibility issues at all really. Nice if you have wishbone peripherals you want to hook up on the back end - very easy to get going. Had opencores DMA mastering over PCI too. Performance is another issue. If you're looking to push PCI burst transfers to the limit, then it's not so straightforward. Not saying it can't be done, but it will take some effort. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 105252
Antti Lukats wrote: > Hi > > Xilinx software is getting better! With 8.1 release I managed to get first > fatal crash within 5 minutes after install, with 8.2 it did take 20mins > already! > > ok, actually its not even a crash - with WebPack 8.2 if running coregen and > selecting Clocking - Virtex 5 > > then the screen will start to blink wild > > and a double click will then terminate the coregen. > > still 20 mins to crash is an improvment compared to 5 mins. I thought webpack did not support Virtex5 ? - or is this the full foundation ? -jgArticle: 105253
I have tried already all the demos and they all work fine. Problem is with a new configuration ACE file that I create with ISE 8.1 and iMPACT - even the simplest design can not configure the board.Article: 105254
baker.ea@gmail.com wrote: > The R/nB signal should stay low for a maximum of 25us for a read > according to the data sheet. > > Even when I execute the Reset command to the flash, the flash hangs in > the Busy state. Yep, needs a pull-up. -aArticle: 105255
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:44bd8bbd$1@clear.net.nz... > Antti Lukats wrote: >> Hi >> >> Xilinx software is getting better! With 8.1 release I managed to get >> first fatal crash within 5 minutes after install, with 8.2 it did take >> 20mins already! >> >> ok, actually its not even a crash - with WebPack 8.2 if running coregen >> and selecting Clocking - Virtex 5 >> >> then the screen will start to blink wild >> >> and a double click will then terminate the coregen. >> >> still 20 mins to crash is an improvment compared to 5 mins. > > I thought webpack did not support Virtex5 ? - or is this the full > foundation ? > -jg > Hi Jim, its WebPack and you are right it does not support Virtex-5, but in WebPack 8.2 Coregen the Virtex-5 clocking ip cores are visible. but selecting that item makes the coregen Crazy! AnttiArticle: 105256
Antti Lukats wrote: > "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag > news:44bd8bbd$1@clear.net.nz... > >>Antti Lukats wrote: >> >>>Hi >>> >>>Xilinx software is getting better! With 8.1 release I managed to get >>>first fatal crash within 5 minutes after install, with 8.2 it did take >>>20mins already! >>> >>>ok, actually its not even a crash - with WebPack 8.2 if running coregen >>>and selecting Clocking - Virtex 5 >>> >>>then the screen will start to blink wild >>> >>>and a double click will then terminate the coregen. >>> >>>still 20 mins to crash is an improvment compared to 5 mins. >> >>I thought webpack did not support Virtex5 ? - or is this the full >>foundation ? >>-jg >> > > > Hi Jim, > > its WebPack and you are right it does not support Virtex-5, but in WebPack > 8.2 Coregen > the Virtex-5 clocking ip cores are visible. but selecting that item makes > the coregen Crazy! On the subject of this blindspot, I did notice these releases with a wry smile : Press release headline: "Xilinx Releases ISE WebPACK 8.2i - FPGA Industry's Only Free Fully Featured Design Suite" Well, no, not quite fully featured, but what's a marketdriod to know... and I get this promo by email : Xilinx: Webcast: Design for Performance with Virtex-5 FPGAs "In this webcast you will: How Virtex-5 FPGAs achieve 30% higher performance than previous generation device Guidelines and insight to help you design for maximum performance Advanced techniques and tool settings to maximize performance" So, it seems they DO want to sell the silicon; you just have to pay to even trial it... Does seem like the right hand has not idea what the left hand is doing ? ;) -jgArticle: 105257
Dan schrieb: > I have tried already all the demos and they all work fine. Problem is with a new configuration ACE file that I create with ISE 8.1 and iMPACT - even the simplest design can not configure the board. you can playback ACE file without the ACE controller on PC using cable III http://www.xilant.com/downloads/aceplayer_1_0.zip if I needed I can add more verbose debug output to the aceplayer Antti http://antti-brain.comArticle: 105258
Brian McFarland schreef: > I've looked at the PCI Compiler from Altera. It seems very poorly > documented, which I think will make the backend difficult to develop > and complicated. The Altera PCI Compiler has an option to generate it as a Avalon peripheral, which then enables SOPC Builder to do the back-end work for you. This is as easy as it gets. SOPC Builder Ready: http://www.altera.com/products/ip/certifications/sopc/ip-sopc.html SOPC Builder: http://www.altera.com/products/software/products/sopc/sop-index.html Look in the PCI Compiler installation folder for the 'sopc_flow' and you will find an ready to use example. Kind regards, Karl.Article: 105259
sorry antti, but do you mean that at lattice they have a downloadable pci ip retargettable to any fpga? (i.e rtl code?) if yes could put here the link? Antti Lukats ha scritto: > "Brian McFarland" <brian.mcf1985@gmail.com> schrieb im Newsbeitrag > news:1153248948.387051.197670@p79g2000cwp.googlegroups.com... >> Does anyone have experience with more than one of the PCI cores out >> there? I'm working a PCI card that's still in the early stages of the >> design. I'm hoping to be able to do pretty much everything on a single >> Altera FPGA - most likely a Cyclone II device. >> >> I've looked at the PCI Compiler from Altera. It seems very poorly >> documented, which I think will make the backend difficult to develop >> and complicated. The one from opencores.org looks like it's easier to >> use, better documented, and has the advantage of being LGPL. I haven't >> looked at the one from Eureka much. >> >> Any comment's regarding PCI compliance, ease of use, compatability with >> Altera parts, etc? >> > > the easiest is the free PCI target from lattice, free download > > I have used it on more than 5 different boards, altera and xilinx based > it has worked almost always first time tried - just set pin constraints and > thats it > > there are other free alternatives as well, but the lattice pci target is the > simplest > > Antti > >Article: 105260
Brian McFarland schreef: > I've been messing around with my own sort of development board for an > Altera MAX 3064 because I have some downtime at work (I'm a coop) and > wanted to teach myself some PLD stuff. I wanted ot put a manual clock > button on it so I could just mess around with some simple designs to > get a feel for how to use HDL's and Quartus. I have some DIPs for > inputs and LEDs for outputs, everything run on 3.3V. But the I can't > manage to get the clock to pulse just once when I press the button. > Can anyone recomend a debouncing circuit to use for something l like > this? Hi Brain, Why don't you start messing around with the MAX II / EPM240. It comes with an internal oscillator that can be used for debouncing. Additional to this it has an schmitt trigger option on the inputs. You can misuse the design example and steel the debouce: http://altera.com/support/examples/max/exm-analog-encoder.html Karl.Article: 105261
Brian McFarland wrote: > I've been messing around with my own sort of development board for an > Altera MAX 3064 because I have some downtime at work (I'm a coop) and > wanted to teach myself some PLD stuff. I wanted ot put a manual clock > button on it so I could just mess around with some simple designs to > get a feel for how to use HDL's and Quartus. I have some DIPs for > inputs and LEDs for outputs, everything run on 3.3V. But the I can't > manage to get the clock to pulse just once when I press the button. > Can anyone recomend a debouncing circuit to use for something l like > this? Hi Brain, Why don't you start messing around with the MAX II / EPM240. It comes with an internal oscillator that can be used for debouncing. Additional to this it has an schmitt trigger option on the inputs. You can misuse the design example and steal the debouce: http://altera.com/support/examples/max/exm-analog-encoder.html Karl.Article: 105262
Jesper.Kristensen@tellabs.com wrote: > Hello Group. > > Quite simple question... but I cannot seem to be able to find the > answer: > > Given a Code Image initially targeted for a Stratix EP1S40F780C8 - i.e. > Speed Grade "-8" - would it then be without troubles to load and run > that Image on the corresponding "-6" device...? > > The need for the question arises in the crossfire of device > availability and the wish of having only one Coding Image to update. > > Thanks in advance & best regards, > > Jesper. Hi Jesper, As far as I know there should not be any issue with that approatch since the device has the same ID:code. AFAIK the only diffrence between -6 and -8 is that Altera gets more parts off the waffer that meets the -8 spec than -6 spec (waffer sort). I just tried programming a CycloneII -7 with a -8 speced file without problem. Hope this helps FredrikArticle: 105263
antonio bergnoli schrieb: > sorry antti, > but do you mean that at lattice they have a downloadable pci ip > retargettable to any fpga? (i.e rtl code?) if yes could put here the link? > > > > Antti Lukats ha scritto: sure get it here http://www.latticesemi.com/products/intellectualproperty/referencedesigns/pcitarget32bit33mhz.cfm 100% verilog source included! Antti http://antti-brain.comArticle: 105264
Gabor, thanks! Of course a reset statement would prevent ISE from turning the registers into SRLs. I also found out, by browsing through some old course notes from X that duplicated registers named reg_1, reg_2 etc are mapped into the same slice. They should be named reg_a, reg_b and so forth. Maybe that will help as well. /Johan Gabor wrote: > Any register with a reset term should not infer SRL, since there > is no asynchronous (or synchronous) reset on distributed RAM. > So normally just adding the asynchronous reset process for the > pipeline stages and not for the slower stages should get the job > done. I've noticed that XST likes to use SRL whenever possible, > and it will warn you about large registers that don't fit into SRL > due to reset requirements. > > Johan Bernspång wrote: >> Hi all, >> >> I'm building a design where I want ISE (8.1) to extract the shift >> registers in some parts, i.e. where I have inferred SRL counters etc, >> and not to extract them in other parts. For instance where I have coded >> multiple stages of pipelining in order to obtain timing closure. Has >> anybody done this? Partial shift register extraction, that is. >> >> The design is occupying about 50% of a Virtex-2 2000 and running mostly >> at 200 MHz. This is why I need to insert some pipelining between >> different stages in the signal path. My intention is to add a few stages >> to enable ISE to divide the routing in shorter bits. >> >> Any input is highly appreciated >> >> /Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 105265
Jasper - On 17 Jul 2006 22:02:58 -0700, Jesper.Kristensen@tellabs.com wrote: >Hello Group. > >Quite simple question... but I cannot seem to be able to find the >answer: > >Given a Code Image initially targeted for a Stratix EP1S40F780C8 - i.e. >Speed Grade "-8" - would it then be without troubles to load and run >that Image on the corresponding "-6" device...? > >The need for the question arises in the crossfire of device >availability and the wish of having only one Coding Image to update. > >Thanks in advance & best regards, > > Jesper. If the -6 parts don't work, your -8 parts might not work reliably, either. Perhaps this isn't obvious, so let me explain. As a rule, FPGA vendors use the very same die design for every speed grade. They make a bunch of wafers, test each part for functionality and speed, then separate the working parts according to speed grade. But suppose the vendor has the bad luck to have a lot of slow-speed part orders sitting around, but happens to have a surplus of fast-speed parts on hand. It wouldn't be practical to keep cranking out wafers until they get some slower parts, because there's no telling when they'll get them. Murphy says that when you want slow, you get fast. So what digital parts vendors do, almost without exception, is spec their parts so that the faster speed grade parts can be substituted for lower-speed parts in a pinch. If you're ordering slow-grade parts, there's absolutely no guarantee that the vendor hasn't marked some fast-grade parts with the slower speed grade number and sent them to you. Of course, the vendor has to guarantee that all faster parts meet the specs for the slower parts. This is done through careful specmanship. For example, take a look at the Stratix AC specs for I/O clock-to-output times: all speed grades have the same minimum spec (at least from what I can tell from a brief perusal of the data sheet). This is important, because if you calculated external hold time margins based on a long minimum clock-to-Q, then substituted a part with a faster clock-to-Q, you could get into trouble. But as long as the vendor has been smart about choosing specs, remarking a faster part as a slower one is all perfectly above-board and legal. And has been pointed out by others, all of this is moot if you're not using solid synchronous design techniques. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 105266
Thanx! It needs the pull up resistor! I can't believe that I missed it!Article: 105267
Dear all, I recently jumped to Quartus 6.0 (from former 5.x) and experienced that the design would not compile correctly. I am working with a Cyclone II device and (in this case) have the problems in beneath a controller for an AD-converter which is not read correctly. Doing a compilation with the former 5.x Version produces valid fpga code. I did not contact the support for this yet because I cannot 100% describe the problem and locate the misbehaviour in the data chain. I also cannot pas away the code to let somebody else find it. Currently I am about to use signal tap to locate it, but have low time to spent on this, however. I have similar parts of the design /channels several times in the code, and other fragments work, however. It seems to be a problem of a particular part of the FPGA code, which might not be interpreted the same way in the both versions. Anybody else discovered genereal probs with the new 6.0 of Quartus?Article: 105268
Thanks!! and could you suggest a good staring poit to learn pci standard? better if for free..:-) Antti ha scritto: > antonio bergnoli schrieb: > >> sorry antti, >> but do you mean that at lattice they have a downloadable pci ip >> retargettable to any fpga? (i.e rtl code?) if yes could put here the link? >> >> >> >> Antti Lukats ha scritto: > > sure get it here > > http://www.latticesemi.com/products/intellectualproperty/referencedesigns/pcitarget32bit33mhz.cfm > > 100% verilog source included! > > Antti > http://antti-brain.com >Article: 105269
I am having several dual port block rams in a cyclone II device. The access takes place as simple dual port option with only one clock for the bram but sometimes a write, when a read is done simultaneously. I expexted the old data to appear at the output as demanded, when I defined the brams from within the altera megafunction wizzard. I know about the possible bugs, when using two different clocks, as described in an altera technical announcement, therefore I use only one system clock for the rams. I observe corrupted data though! :-( It obviously is caused when the reading and writing processes access the same time. I am sure that I contraint "old data" and varified this in the vhdl-definitions created be the wizzard. Ideas?Article: 105270
> I observe corrupted data though! :-( It obviously is caused when the > reading and writing processes access the same time. I am sure that I > contraint "old data" and varified this in the vhdl-definitions created > be the wizzard. > > Ideas? > Did you run a simulation (If not, then you should)? Do the actual results match the simulation results? (If they do then debug the problem in the simulation environment first) KJArticle: 105271
That is the point. Modelsim shows a well behavior. Nothing wrong. The error only shows up in real and signal tap analysis. I already changed the timing (slower). The only way to shun this problem is, to disallow simultanous access, which in fact lowers performance.Article: 105272
Johan Bernsp=E5ng wrote: > Gabor, thanks! > Of course a reset statement would prevent ISE from turning the registers > into SRLs. > I also found out, by browsing through some old course notes from X that > duplicated registers named reg_1, reg_2 etc are mapped into the same > slice. They should be named reg_a, reg_b and so forth. Maybe that will > help as well. > > /Johan Also look in the Mapping Options for "disable register ordering" if this is a problem. In the old days, slice packing was done by the mapper. Now I'm not sure how much difference this makes if you allow the XST synthesis to pack logic into slices. There may be a similar setting for XST, but I couldn't find it. Regards, Gabor > > Gabor wrote: > > Any register with a reset term should not infer SRL, since there > > is no asynchronous (or synchronous) reset on distributed RAM. > > So normally just adding the asynchronous reset process for the > > pipeline stages and not for the slower stages should get the job > > done. I've noticed that XST likes to use SRL whenever possible, > > and it will warn you about large registers that don't fit into SRL > > due to reset requirements. > > > > Johan Bernsp=E5ng wrote: > >> Hi all, > >> > >> I'm building a design where I want ISE (8.1) to extract the shift > >> registers in some parts, i.e. where I have inferred SRL counters etc, > >> and not to extract them in other parts. For instance where I have coded > >> multiple stages of pipelining in order to obtain timing closure. Has > >> anybody done this? Partial shift register extraction, that is. > >> > >> The design is occupying about 50% of a Virtex-2 2000 and running mostly > >> at 200 MHz. This is why I need to insert some pipelining between > >> different stages in the signal path. My intention is to add a few stag= es > >> to enable ISE to divide the routing in shorter bits. > >> > >> Any input is highly appreciated > >> > >> /Johan > > > > -- > ----------------------------------------------- > Johan Bernsp=E5ng, xjohbex@xfoix.se > Research engineer > > Swedish Defence Research Agency - FOI > Division of Command & Control Systems > Department of Electronic Warfare Systems > > www.foi.se > > Please remove the x's in the email address if > replying to me personally. > -----------------------------------------------Article: 105273
On Wed, 19 Jul 2006, homoalteraiensis wrote: "[..] I observe corrupted data though! :-( It obviously is caused when the reading and writing processes access the same time. I am sure that I contraint "old data" and varified this in the vhdl-definitions created be the wizzard. Ideas?" Learn about semaphores, or even better in Ada: protected objects.Article: 105274
"Noway2" <no_spam_me2@hotmail.com> wrote in message news:1152882298.931106.231460@i42g2000cwa.googlegroups.com... > > Thomas Reinemann wrote: >> Hello, >> >> usually a reset signal is applied to put the FFs of an FPGA into a known >> state. Just some days ago I had a discussion. Someone's point of view >> is, that a reset is not necessary, since the FF's output will be always >> zero, after applying the voltage. Does this happen in FPGAs really, >> especially in a Spartan3? >> >> Bye Tom > > 1 - If it were guarenteed that logic would always come up in a known > and valid state, why would the manufacturer include pins that are > dedicated to being a global reset? Does most logic power up into a > known and valid state or does it need a solid reset signal? Because you might want to reset all the FF after power-up. I believe that the FF are loaded with their reset value when the FPGA is configured whether or not the reset is there. Mike
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