Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 111975

Article: 111975
Subject: Xilinx ML310 programming failure
From: kunals.spam.account@gmail.com
Date: 13 Nov 2006 21:34:31 -0800
Links: << >>  << T >>  << A >>
I was wondering if anyone using the ML310 is having similar issues as I
am --

What I'm using:
- Platform Cable USB
- Xilinx ML310
All the latest software updates as of today (11/13/06)
- EDK v8.2.02
- ISE v8.2.02
- IP Updates v2

I'm downloading the bitstream onto the board from EDK, and it always
shows that it was successful. The board, however, randomly does not
function as it's supposed to (more often than not), and it does
nothing. No serial output, the lights don't do anything (there's a
custom IP in there that makes the lights blink -- I created it to debug
this exact issue), and the board is otherwise dead.

Questions:
1. Can I use ChipScope to debug this? What should I check (I'm guessing
the bus clock and various signals in the embedded system)
2. How can I isolate the problem to the JTAG programmer, if that's
where it is? I only have one of these, and it would be silly for me to
buy another just to isolate the problem.

- Kunal


Article: 111976
Subject: Re: MPMC2: MPMC2 with DDR2 SDRAM
From: "Antti" <Antti.Lukats@xilant.com>
Date: 13 Nov 2006 23:43:49 -0800
Links: << >>  << T >>  << A >>
Siva Velusamy schrieb:

> Antti wrote:
> > zyan schrieb:
> >
> >> Hi,
> >>
> >> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> >>
> >> Thanks.
> >
> > same here :(
> > all attempts to get MPMC2 DDR2 designs to work have failed so far
> > have tested on custom V4 board with single 16bit device and on ML501
> > all attempts failing
> >
> > I guess the only way to get going is to purchase a eval board that *IS*
> > supported by MPMC2 like ml410 and get it working there, and then
> > translate that working design to a custom board.
> >
> > Antti
> >
>
> Hi Antti,
>
> MPMC2 works fine on ML410 DDR2. You might want to start with those
> settings and then customize for your project.
>
> BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.
>
> /Siva

Hi Siva,

I belive that MPMC2 DDR2 works on "Xilinx provided boards" but the
question is how to make it to work on an "non Xilinx board?"

I have several custom V4 boards with DDR2 and I have ML501, I assumed
that as MPMC2 generates UCF file that matches ML501 so first step would
be to get MPMC2 to work on ML501 and then derive a new design for the
custom board. I dont have ML410 or any other "xilinx supported board"
for testing.

can you tell me why MPMC2 1.7 does not support V5? is it because
1) it is not tested (but may work) ?
2) IP core just want work for V-5 architecture
3) IP core is ok for V-5 but want work on ML501 because of clock buffer
errata in ES silicon as described in EN049.PDF ?

Are there any plans to make MPMC2 to support Virtex-5? If yes when can
we expect this?

Getting MPMC2 to work on our custom V4 DDR2 boards is really urgent, so
any help is welcome.

For now I will drop any MPMC2 testing on ML501 and try to modify some
MPMC2 archived project for our purpose, so far I did regenerate new
project (and that failed to workI)

Antti


Article: 111977
Subject: Re: Compile error by Cadence NC-Sim
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 14 Nov 2006 00:24:37 -0800
Links: << >>  << T >>  << A >>
No one interest in this problem? The formulationg not clearly?


Article: 111978
Subject: Re: Nested Generate Statement in VHDL
From: "Hans" <hans64@ht-lab.com>
Date: Tue, 14 Nov 2006 09:15:36 GMT
Links: << >>  << T >>  << A >>
See Peter Ashenden's proposal on generate statements:
http://www.accellera.org/apps/group_public/download.php/441/ESC-WP-009-if-and-case-generates.pdf

And the VHDL2006 standard:
http://www.accellera.org/apps/group_public/download.php/670/P1076-2006-D2.11.zip

For some reason the cleaned up P1076-2006-D2.11.pdf document was removed 
from the accellera's website, not sure why. The above zip file contains the 
document with all the corrections shown.

If you want "if & else" generate support for VHDL then email your simulator 
vendor and ask them when this standard will be supported. The more emails 
they get the more likely it is they will support it. I have already emailed 
Modeltech and they said they are working in it.....

Hans
www.ht-lab.com


<Sudhir.Singh@email.com> wrote in message 
news:1163480213.949756.230210@m7g2000cwm.googlegroups.com...
> Hi Mark,
> Thanks for your reply.
> Yeah its really annoying that VHDL doesn't have the if & else construct
> for generate.
>
> I also find the different syntaxs for if else type selection based on
> whether its a concurrent statement or inside a process, quite annoying.
>
> Thanks.
> Sudhir
>
> Mark McDougall wrote:
>> Sudhir.Singh@email.com wrote:
>>
>> > my code looks like
>> >
>> > gen_tx: if N_TX > 0 generate
>> >   gen_tx_inst: for i in 0 to N_TX-1 generate
>> >      tx_inst: tx port map(...);
>> >   end generate gen_tx_inst;
>> > end generate gen_tx;
>> >
>> > Now if I set N_TX to zero, Modelsim compiler issues a warning about the
>> > inner generate, saying "Range 0 to -1 is null". I understand that the
>> > inner range would be 0 to -1 if I set N_TX to 0, thats what I have been
>> > trying to catch by having an outer generate.
>> >
>> > Can I safely ignore this warning message? Would the synthesis & PAR
>> > tools (Xilinx) misbehave because of this?
>> > Does anyone have a better method of doing this?
>>
>> My belief is that you can safely ignore the warning. The VHDL compiler
>> will insist on 'compiling' or at least parsing the innards of a generate
>> even if the condition fails, which can be quite annoying! I'm sure
>> there's a good reason - I'm just a big fan of C macros and I wish that
>> VHDL had the same. Yes, I am aware of pre-processors but it's not really
>> an option when you're writing code for customers.
>>
>> It's also very annoying that generate *requires* a label, and that it
>> doesn't have an 'else'!
>>
>> I'm not sure you need to even catch the zero case - the inner loop
>> should suffice!?!
>>
>> Regards,
>>
>> --
>> Mark McDougall, Engineer
>> Virtual Logic Pty Ltd, <http://www.vl.com.au>
>> 21-25 King St, Rockdale, 2216
>> Ph: +612-9599-3255 Fax: +612-9599-3266
> 



Article: 111979
Subject: Re: MPMC2: MPMC2 with DDR2 SDRAM
From: "Guru" <ales.gorkic@email.si>
Date: 14 Nov 2006 02:14:26 -0800
Links: << >>  << T >>  << A >>
I got it working on Virtex4FX12 MiniModule AKA GSRD2. Actually I had no
problems at all. But It has only 64MB DDR x16. I also tried running DDR
at 200MHz but it did not pass the memory test since it is only DDR333.
I also don't know where these MPMC2 guys got the datasheet for this RAM
to get the Fmax=200 at CL=3.
But I do have some problems writing to NPI in 64 word bursts and
premature ending.

BTW: There are so many parameters to adjust that there is a good chance
that the system does not work at all.

Cheers,

Guru



Antti wrote:
> Siva Velusamy schrieb:
>
> > Antti wrote:
> > > zyan schrieb:
> > >
> > >> Hi,
> > >>
> > >> Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
> > >>
> > >> Thanks.
> > >
> > > same here :(
> > > all attempts to get MPMC2 DDR2 designs to work have failed so far
> > > have tested on custom V4 board with single 16bit device and on ML501
> > > all attempts failing
> > >
> > > I guess the only way to get going is to purchase a eval board that *IS*
> > > supported by MPMC2 like ml410 and get it working there, and then
> > > translate that working design to a custom board.
> > >
> > > Antti
> > >
> >
> > Hi Antti,
> >
> > MPMC2 works fine on ML410 DDR2. You might want to start with those
> > settings and then customize for your project.
> >
> > BTW, MPMC2 does not support Virtex5 as yet, so it will not work on ML501.
> >
> > /Siva
>
> Hi Siva,
>
> I belive that MPMC2 DDR2 works on "Xilinx provided boards" but the
> question is how to make it to work on an "non Xilinx board?"
>
> I have several custom V4 boards with DDR2 and I have ML501, I assumed
> that as MPMC2 generates UCF file that matches ML501 so first step would
> be to get MPMC2 to work on ML501 and then derive a new design for the
> custom board. I dont have ML410 or any other "xilinx supported board"
> for testing.
>
> can you tell me why MPMC2 1.7 does not support V5? is it because
> 1) it is not tested (but may work) ?
> 2) IP core just want work for V-5 architecture
> 3) IP core is ok for V-5 but want work on ML501 because of clock buffer
> errata in ES silicon as described in EN049.PDF ?
>
> Are there any plans to make MPMC2 to support Virtex-5? If yes when can
> we expect this?
>
> Getting MPMC2 to work on our custom V4 DDR2 boards is really urgent, so
> any help is welcome.
>
> For now I will drop any MPMC2 testing on ML501 and try to modify some
> MPMC2 archived project for our purpose, so far I did regenerate new
> project (and that failed to workI)
> 
> Antti


Article: 111980
Subject: Re: Fastest ISE Compile PC?
From: Joseph Samson <user@example.net>
Date: Tue, 14 Nov 2006 12:35:57 GMT
Links: << >>  << T >>  << A >>
David Brown wrote:
> I'm sure the second core will make a difference - while the one long 
> task is occupying one core, other minor tasks will run on the other 
> core.  While these other tasks might only take a tiny proportion of the 
> processor time, you avoid the penalties of task switching (like losing 
> your cache) on the working processor.
I started using a Mac Pro a few weeks ago - Dual Core2Duo Xeons, 2GB RAM 
running XP SP2. Although ISE isn't muti-threaded, I found a use for the 
2nd processor yesterday - I ran a second instance of ISE. I'm working on 
a multi-chip design, and I synthesized one project while routing a 
second project. I set the affinity so that they executed on different 
processors (at least I think they were on different processors). I 
didn't benchmark the execution speed, but the time didn't seem out of line.



---
Joe Samson
Pixel Velocity

Article: 111981
Subject: xupv2p
From: "nana" <nmichou@utk.edu>
Date: 14 Nov 2006 05:22:24 -0800
Links: << >>  << T >>  << A >>
Helllo,
Does anyone know about transfering data between two xupv2p boards, that
is from one board to another?
I appreciate your help

nmichou


Article: 111982
Subject: Re: Stratix-III announced
From: "Antti" <Antti.Lukats@xilant.com>
Date: 14 Nov 2006 05:39:24 -0800
Links: << >>  << T >>  << A >>
unknown@aol.com schrieb:

> Personnaly, I'm also waiting for Cyclone III. Looks promising.
> By the way, I've been told that MAX III is also on the way ... and that NIOS II will be
> supported :o)
>
>
> ----------------------------------------------
> Posted with NewsLeecher v3.5 Beta 5
>  * http://www.newsleecher.com/?usenet

Cyclone-III silicon will be available as first, e.g. BEFORE stratix-III

Anttti


Article: 111983
Subject: problem about license of Modelsim in Altera quartus webpack
From: "fl" <rxjwg98@gmail.com>
Date: 14 Nov 2006 05:40:52 -0800
Links: << >>  << T >>  << A >>
Hi,
I installed Quartus II and it works except Modelsim on both my laptop
and desktop computers. For desktop computer, I got the license as
follows from email:


Your license:
FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
5..........2 HOSTID=001........b SIGN="1F...............56 \
.......................... \
.....................AF B041 \
0AA5 E437"

When I run ModelSim-Altera WE-6.1d, the diaglog box said: Unable to
checkout a license, Make sure your license file environment variables
are set correctly and then run 'lmutillmdiag' to diagnose the problem.
Modelsim-Altera uses the following envrionment variables to check the
licenses (listed in the order of preference)
1. MGLS_LICENSE_FILE
2. LM_LICENSE_FILE


It seems I forgot to check for modelsim when I required the license. I
try to get a new one with modelsim, but what I get is the same. How to
get one license with modelsim enabled?

For my laptop computer, I do have a license:


Your license:
FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
CEE........ HOSTID=00XXXXXXXXXX SIGN="09B8 XXXX XXXX XXXX \
.........................................................3E \
.....................................................8 BEEF \
5.A. 2..A"
INCREMENT alteramtiwe mgcld 2007.04 15-apr-2007 uncounted \
  6.................1C VENDOR_STRING=CD.....4 HOSTID=00.......... \
  SUPERSEDE ISSUER=Alterav3.3

But I get the same diaglog error message as the above. I don't know how
to set up the license of ModelSim-Altera. Quartus II works well on both
desktop and laptop except ModelSim. Could you help me? Thank you very
much.


Article: 111984
Subject: Re: problem about license of Modelsim in Altera quartus webpack
From: "fl" <rxjwg98@gmail.com>
Date: 14 Nov 2006 05:46:49 -0800
Links: << >>  << T >>  << A >>
Sorry, to add a little. The OS is XP on both computers. The web
connection is dial-up. I don't know whether it is related. Thank you.



fl a =E9crit :

> Hi,
> I installed Quartus II and it works except Modelsim on both my laptop
> and desktop computers. For desktop computer, I got the license as
> follows from email:
>
>
> Your license:
> FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> 5..........2 HOSTID=3D001........b SIGN=3D"1F...............56 \
> .......................... \
> .....................AF B041 \
> 0AA5 E437"
>
> When I run ModelSim-Altera WE-6.1d, the diaglog box said: Unable to
> checkout a license, Make sure your license file environment variables
> are set correctly and then run 'lmutillmdiag' to diagnose the problem.
> Modelsim-Altera uses the following envrionment variables to check the
> licenses (listed in the order of preference)
> 1. MGLS_LICENSE_FILE
> 2. LM_LICENSE_FILE
>
>
> It seems I forgot to check for modelsim when I required the license. I
> try to get a new one with modelsim, but what I get is the same. How to
> get one license with modelsim enabled?
>
> For my laptop computer, I do have a license:
>
>
> Your license:
> FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> CEE........ HOSTID=3D00XXXXXXXXXX SIGN=3D"09B8 XXXX XXXX XXXX \
> .........................................................3E \
> .....................................................8 BEEF \
> 5.A. 2..A"
> INCREMENT alteramtiwe mgcld 2007.04 15-apr-2007 uncounted \
>   6.................1C VENDOR_STRING=3DCD.....4 HOSTID=3D00.......... \
>   SUPERSEDE ISSUER=3DAlterav3.3
>
> But I get the same diaglog error message as the above. I don't know how
> to set up the license of ModelSim-Altera. Quartus II works well on both
> desktop and laptop except ModelSim. Could you help me? Thank you very
> much.


Article: 111985
Subject: Re: Compile error by Cadence NC-Sim
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 14 Nov 2006 07:28:41 -0800
Links: << >>  << T >>  << A >>
uvbaz wrote:
> No one interest in this problem? The formulationg not clearly?

I have problems already.
If you want an answer, ask a question.
If you want to print text from your simulation,
try the REPORT statement.

      -- Mike Treseler


Article: 111986
Subject: Re: problem about license of Modelsim in Altera quartus webpack
From: OL <noname@free.fr>
Date: Tue, 14 Nov 2006 16:31:02 +0100
Links: << >>  << T >>  << A >>
fl a écrit :
> Hi,
> I installed Quartus II and it works except Modelsim on both my laptop
> and desktop computers. For desktop computer, I got the license as
> follows from email:
> 
> 
> Your license:
> FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> 5..........2 HOSTID=001........b SIGN="1F...............56 \
> .......................... \
> .....................AF B041 \
> 0AA5 E437"
> 
> When I run ModelSim-Altera WE-6.1d, the diaglog box said: Unable to
> checkout a license, Make sure your license file environment variables
> are set correctly and then run 'lmutillmdiag' to diagnose the problem.
> Modelsim-Altera uses the following envrionment variables to check the
> licenses (listed in the order of preference)
> 1. MGLS_LICENSE_FILE
> 2. LM_LICENSE_FILE
> 
> 
> It seems I forgot to check for modelsim when I required the license. I
> try to get a new one with modelsim, but what I get is the same. How to
> get one license with modelsim enabled?
> 
> For my laptop computer, I do have a license:
> 
> 
> Your license:
> FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> CEE........ HOSTID=00XXXXXXXXXX SIGN="09B8 XXXX XXXX XXXX \
> .........................................................3E \
> .....................................................8 BEEF \
> 5.A. 2..A"
> INCREMENT alteramtiwe mgcld 2007.04 15-apr-2007 uncounted \
>   6.................1C VENDOR_STRING=CD.....4 HOSTID=00.......... \
>   SUPERSEDE ISSUER=Alterav3.3
> 
> But I get the same diaglog error message as the above. I don't know how
> to set up the license of ModelSim-Altera. Quartus II works well on both
> desktop and laptop except ModelSim. Could you help me? Thank you very
> much.
> 
	Do you have your environment variable LM_LICENSE_FILE set to the path 
of your license file ?

	On your laptop, you seem to have the feature alteramtiwe declared on 
your license file. It might be OK for you to use Modelsim-Altera WE. 
However, you don't have this feature on your desktop computer.
	

Article: 111987
Subject: Re: Nested Generate Statement in VHDL
From: Jim Lewis <Jim@SynthWorks.com>
Date: Tue, 14 Nov 2006 07:54:30 -0800
Links: << >>  << T >>  << A >>
Hans,
The draft you want is 3.0.  It is not a public document.
To get it you must join the Accellera VHDL TSC (note this
does not require money and hence it is more like registering).
To register, go to http://www.accellera.org/activities/vhdl/
Ask to join VHDL TSC and sent the form to Lynn.

> See Peter Ashenden's proposal on generate statements:
> http://www.accellera.org/apps/group_public/download.php/441/ESC-WP-009-if-and-case-generates.pdf
> 
> And the VHDL2006 standard:
> http://www.accellera.org/apps/group_public/download.php/670/P1076-2006-D2.11.zip
> 
> For some reason the cleaned up P1076-2006-D2.11.pdf document was removed 
> from the accellera's website, not sure why. The above zip file contains the 
> document with all the corrections shown.

The copyright owner is IEEE and they forbid giving away the standard
to people other than those who are participating in the revision.
Hence, when you register, you become a participant and you can get
a copy.  :)   Since there is not a simple standards developers guide,
it took a little time to resolve this and realize that making it
public was not ok - even when Accellera developed the changes.


> If you want "if & else" generate support for VHDL then email your simulator 
> vendor and ask them when this standard will be supported. The more emails 
> they get the more likely it is they will support it. I have already emailed 
> Modeltech and they said they are working in it.....

This has more truth than you may believe.

Every revision a vendor makes to their tool is an investment.
WRT standards, they want to know their investment is a good one.
Having users interested and asking when it will be done is
a good indication that it is a good investment (and a threat
because if they fail to do it, you might buy someone else's
simulator or synthesis tool).

Cheers,
Jim
-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 111988
Subject: Re: problem about license of Modelsim in Altera quartus webpack
From: "fl" <rxjwg98@gmail.com>
Date: 14 Nov 2006 08:09:57 -0800
Links: << >>  << T >>  << A >>
Thank you. It is OK now. Sometimes the response from web is different
even though my inputs are the same. It is strange. I get the right
license now.
The laptop depends on environment variable, while Quartus can depend on
a file path.


OL a =E9crit :

> fl a =E9crit :
> > Hi,
> > I installed Quartus II and it works except Modelsim on both my laptop
> > and desktop computers. For desktop computer, I got the license as
> > follows from email:
> >
> >
> > Your license:
> > FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> > 5..........2 HOSTID=3D001........b SIGN=3D"1F...............56 \
> > .......................... \
> > .....................AF B041 \
> > 0AA5 E437"
> >
> > When I run ModelSim-Altera WE-6.1d, the diaglog box said: Unable to
> > checkout a license, Make sure your license file environment variables
> > are set correctly and then run 'lmutillmdiag' to diagnose the problem.
> > Modelsim-Altera uses the following envrionment variables to check the
> > licenses (listed in the order of preference)
> > 1. MGLS_LICENSE_FILE
> > 2. LM_LICENSE_FILE
> >
> >
> > It seems I forgot to check for modelsim when I required the license. I
> > try to get a new one with modelsim, but what I get is the same. How to
> > get one license with modelsim enabled?
> >
> > For my laptop computer, I do have a license:
> >
> >
> > Your license:
> > FEATURE quartus_lite alterad 2007.04 15-apr-2007 uncounted \
> > CEE........ HOSTID=3D00XXXXXXXXXX SIGN=3D"09B8 XXXX XXXX XXXX \
> > .........................................................3E \
> > .....................................................8 BEEF \
> > 5.A. 2..A"
> > INCREMENT alteramtiwe mgcld 2007.04 15-apr-2007 uncounted \
> >   6.................1C VENDOR_STRING=3DCD.....4 HOSTID=3D00.......... \
> >   SUPERSEDE ISSUER=3DAlterav3.3
> >
> > But I get the same diaglog error message as the above. I don't know how
> > to set up the license of ModelSim-Altera. Quartus II works well on both
> > desktop and laptop except ModelSim. Could you help me? Thank you very
> > much.
> >
> 	Do you have your environment variable LM_LICENSE_FILE set to the path
> of your license file ?
>
> 	On your laptop, you seem to have the feature alteramtiwe declared on
> your license file. It might be OK for you to use Modelsim-Altera WE.
> However, you don't have this feature on your desktop computer.


Article: 111989
Subject: Re: How to control the running of NC-Sim and Xilinx ISE under Unix?
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 14 Nov 2006 08:49:16 -0800
Links: << >>  << T >>  << A >>
Thanks Jim,

They are very useful tools

Regard,
Cheng

Jim Wu schrieb:

> You may want to use a Makefile for this. You can find an example
> Makefile for ISE tools here:
> http://home.comcast.net/~jimwu88/tools/
>
> HTH,
> Jim
>
>
>
> uvbaz wrote:
> > hi,  everyone,
> >
> > I want to run
> >
> > ncvlog
> > ncvhdl
> > ncelab
> > ncsim
> > xst
> > ngdbuild
> > .....
> > under Unix.
> > I've write a script for this, but with no control statement. How can i
> > control the running flow, namely:
> >
> > if (NCVLOG ERROR) then ERROR REPORT and STOP THE RUNNING....
> >
> > or
> >
> > if (XST ERROR) then ERROR REPORT and STOP THE RUNNING....
> > 
> > Thanks,
> > Cheng


Article: 111990
Subject: Re: Compile error by Cadence NC-Sim
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 14 Nov 2006 09:01:01 -0800
Links: << >>  << T >>  << A >>
Hi, Mike,

I'm sorry if i havent clearly describt the question:
The files 1 to 4 are the configuration files, file 5 is the script, run
file.
My question are:
1. I want to compile "fprint.vhd + fprint_body.vhd" in FPRINT, but it
didn't. Why?
2. "$XILINX/verilog/src/simprims/*.v" not recognized, why?

Thanks for your patient, Mike.

Regards,
Cheng


Mike Treseler schrieb:

> uvbaz wrote:
> > No one interest in this problem? The formulationg not clearly?
>
> I have problems already.
> If you want an answer, ask a question.
> If you want to print text from your simulation,
> try the REPORT statement.
> 
>       -- Mike Treseler


Article: 111991
Subject: FFT in VHDL (or Verilog) Tutorial
From: "Student (confused)" <confusedstudent001@gmail.com>
Date: 14 Nov 2006 09:16:03 -0800
Links: << >>  << T >>  << A >>
Hello,

Can someone point me to simple implementation of FFT in VHDL(or
Verilog) with testbench and good step-by-step description. I have
implementation from Xilinx (which I will eventually use for hardware
implementation), but I find it rather confusing (lack of vhdl
experience). Algorithm used, # of points, Radix#, bit precision do not
matter, as I'm looking for tutorial-like implementation.
The best example of what I'm looking for is (found using google)
http://www.opencores.org/projects.cgi/web/cf_fft/overview
http://www.opencores.org/cvsweb.shtml/fft/

Thanks.


Article: 111992
Subject: xilinx_device_details.xml <= which program create it?
From: "uvbaz" <uvbaz@stud.uni-karlsruhe.de>
Date: 14 Nov 2006 09:20:37 -0800
Links: << >>  << T >>  << A >>
hi, everyone,

I run ISE in line cmds, i found that "xilinx_device_details.xml" was
created automatically.

Can someone tell me, which program creates this file? And how can i
change the option, so that this file can be placed into another
location?

Thanks,^_^
Cheng


Article: 111993
Subject: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
From: "logjam" <grant@stockly.com>
Date: 14 Nov 2006 09:38:54 -0800
Links: << >>  << T >>  << A >>
> all you need is an EDK tools chain

I guess I should have bought my development board from xilinx instead
of digilent.  I've been trying to find a trial version of the EDK from
xilinx but I'm not having any luck.  From the posts I've read here, it
doesn't sound like its available.

Are there any xilinx employees in here who could put the trial up for
download?  I'm just doing this for a hobby and can't begin to justify a
$500 program unless I know that it is what I want.  :(  I don't
understand why the same product from digilent doesn't come with any
software...

Grant


Article: 111994
Subject: Re: Xilinx platform cable USB
From: "Manny" <mloulah@hotmail.com>
Date: 14 Nov 2006 09:39:51 -0800
Links: << >>  << T >>  << A >>
Sean,

Thanks a lot. I know JTAG is an IEE standard. I just wanted to be 100%
sure.

Thanks again,
Cheers,
-Manny


Article: 111995
Subject: Why are there ModelSimAltera warning
From: "fl" <rxjwg98@gmail.com>
Date: 14 Nov 2006 09:50:55 -0800
Links: << >>  << T >>  << A >>
Hi,
The following is the first example in the DSP book written by U.Meyer
Baese. I write a testbench in VHDL to have a simulation. In
ModelSimAltera, I find there are a lot of warning (see below) in the
first 25 ns. Is it normal? I rewrote the program in Xilinx previously
using my own add subroutine. Although the sum was uncertain (in red) in
the first 100 ns, there is no such warning. Are there something I can
do in the ModelSimAltera to suppress these warning?

Thanks in advance.







# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /add_1ptb_vhd_g/uut/add_3/l1/u
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /add_1ptb_vhd_g/uut/add_3/l1/u
...
...




LIBRARY lpm;
USE lpm.lpm_components.ALL;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY add_1p IS
  GENERIC (WIDTH  : INTEGER := 15; -- Total bit width
           WIDTH1 : INTEGER := 7;  -- Bit width of LSBs
           WIDTH2 : INTEGER := 8;  -- Bit width of MSBs
           ONE    : INTEGER := 1); -- 1 bit for carry reg.
  PORT (x,y : IN  STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                                  -- Inputs
        sum : OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                                  -- Result
        clk : IN  STD_LOGIC);
END add_1p;

ARCHITECTURE flex OF add_1p IS
  SIGNAL l1, l2, r1, q1                   -- LSBs of inputs
                     : STD_LOGIC_VECTOR(WIDTH1-1 DOWNTO 0);
  SIGNAL l3, l4, r2, q2, u2, h2           -- MSBs of inputs
                     : STD_LOGIC_VECTOR(WIDTH2-1 DOWNTO 0);
  SIGNAL s           : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
                                         -- Output register
  SIGNAL cr1, cq1    : STD_LOGIC_VECTOR(ONE-1 DOWNTO 0);
                                       -- LSBs carry signal


BEGIN
  PROCESS  -- Split in MSBs and LSBs and store in registers
  BEGIN
    WAIT UNTIL clk = '1';
    -- Split LSBs from input x,y
    FOR k IN WIDTH1-1 DOWNTO 0 LOOP
      l1(k) <= x(k);
      l2(k) <= y(k);
    END LOOP;
    -- Split MSBs from input x,y
    FOR k IN WIDTH2-1 DOWNTO 0 LOOP
      l3(k) <= x(k+WIDTH1);
      l4(k) <= y(k+WIDTH1);
    END LOOP;
  END PROCESS;
-------------- First stage of the adder  ------------------
  add_1: lpm_add_sub                 -- Add LSBs of x and y
         GENERIC MAP ( LPM_WIDTH => WIDTH1,
                       LPM_REPRESENTATION => "UNSIGNED",
                       LPM_DIRECTION => "ADD")
         PORT MAP ( dataa => l1, datab => l2,
                    result => r1,  cout => cr1(0));
  reg_1: lpm_ff           -- Save LSBs of x+y and carry
         GENERIC MAP ( LPM_WIDTH => WIDTH1 )
         PORT MAP ( data => r1, q => q1,clock => clk );
  reg_2: lpm_ff
         GENERIC MAP ( LPM_WIDTH => ONE )
         PORT MAP ( data => cr1, q => cq1, clock => clk );

  add_2: lpm_add_sub                 -- Add MSBs of x and y
         GENERIC MAP ( LPM_WIDTH => WIDTH2,
                       LPM_REPRESENTATION => "UNSIGNED",
                       LPM_DIRECTION => "ADD")
         PORT MAP (dataa => l3, datab => l4, result => r2);
  reg_3: lpm_ff                   -- Save MSBs of x+y
         GENERIC MAP ( LPM_WIDTH => WIDTH2 )
         PORT MAP ( data => r2, q => q2, clock => clk );
------------ Second stage of the adder --------------------
  -- One operand is zero
  h2 <= (OTHERS => '0');

  -- Add result from MSBs (x+y) and carry from LSBs
  add_3: lpm_add_sub
         GENERIC MAP ( LPM_WIDTH => WIDTH2,
                       LPM_REPRESENTATION => "UNSIGNED",
                       LPM_DIRECTION => "ADD")
         PORT MAP ( cin => cq1(0), dataa => q2,
                    datab => h2, result => u2 );

  PROCESS              -- Build a single registered output
  BEGIN                -- word of WIDTH=WIDTH1+WIDHT2
    WAIT UNTIL clk = '1';
    FOR k IN WIDTH1-1 DOWNTO 0 LOOP
      s(k) <= q1(k);
    END LOOP;
    FOR k IN WIDTH2-1 DOWNTO 0 LOOP
      s(k+WIDTH1) <= u2(k);
    END LOOP;
  END PROCESS;

  sum <= s ;    -- Connect s to output pins
END flex;


Article: 111996
Subject: sending data across a 32 bit bus
From: "rasic" <reshmid@gmail.com>
Date: 14 Nov 2006 10:28:50 -0800
Links: << >>  << T >>  << A >>
How can I send a 256 bit data across a 32 bit bus/ Could any one please
help me with how I can do this using verilog.
Thanks


Article: 111997
Subject: Influence of temperature and manufacturing to propagation delay
From: "Thomas Reinemann" <tom.reinemann@gmx.net>
Date: 14 Nov 2006 10:33:42 -0800
Links: << >>  << T >>  << A >>
Hi,

we are running in trouble with our curent design for a Xilinx Spartan 3
xc3s1500.

It does signal processing and it seems that sample got lost with
increasing temperature. Immediately after power on all works well, some
minutes later, if final temperatures is reach, some samples are missed.
I hadn't a thermometer ready, but I can always touch the FPGA for a
long time, it may be 50=B0C.
It runs with a clock of 76.8 MHz, PAR states a maximum frequency of
78.777MHz, and logic utilization is about 60%.

One board works as expected and two other show the explained effect,
the boards have the same layout but are made by different
manufacturers. At least the not working are lead free.

Just now, we had a discusion to the influence of temperature to
propagation delay. I don't believe that it influences clock lines and
other logic resources in a (big) different way. Is It true or not?

I read the thread "Propagation delay sensitivity to temperature,
voltage, and manufacturing", but the answers are very related to DCMs.

Tom


Article: 111998
Subject: Re: sending data across a 32 bit bus
From: PeteS <peter.smith8380@ntlworld.com>
Date: Tue, 14 Nov 2006 18:36:38 GMT
Links: << >>  << T >>  << A >>
rasic wrote:
> How can I send a 256 bit data across a 32 bit bus/ Could any one please
> help me with how I can do this using verilog.
> Thanks
> 

Think block RAM, multiple cycles and a counter.

Cheers

PeteS

Article: 111999
Subject: Re: Influence of temperature and manufacturing to propagation delay
From: PeteS <peter.smith8380@ntlworld.com>
Date: Tue, 14 Nov 2006 18:43:57 GMT
Links: << >>  << T >>  << A >>
Thomas Reinemann wrote:
> Hi,
> 
> we are running in trouble with our curent design for a Xilinx Spartan 3
> xc3s1500.
> 
> It does signal processing and it seems that sample got lost with
> increasing temperature. Immediately after power on all works well, some
> minutes later, if final temperatures is reach, some samples are missed.
> I hadn't a thermometer ready, but I can always touch the FPGA for a
> long time, it may be 50°C.
> It runs with a clock of 76.8 MHz, PAR states a maximum frequency of
> 78.777MHz, and logic utilization is about 60%.
> 
> One board works as expected and two other show the explained effect,
> the boards have the same layout but are made by different
> manufacturers. At least the not working are lead free.
> 
> Just now, we had a discusion to the influence of temperature to
> propagation delay. I don't believe that it influences clock lines and
> other logic resources in a (big) different way. Is It true or not?
> 
> I read the thread "Propagation delay sensitivity to temperature,
> voltage, and manufacturing", but the answers are very related to DCMs.
> 
> Tom
> 

Every IO buffer and SRAM device I have ever worked with is sensitive to 
temperature. (So is just about everything else electronic for that matter)

As the device (more strictly the cell) heats up, the propagation delay 
_and_ the rise/fall times _will_ deteriorate.

What is the core temperature rising to? My post-PAR tools give 
guaranteed timing across temperature (assuming you set them up that 
way), including self-heating (which you have to plug in yourself).

At that speed, I would assume the core (or at least those parts toggling 
at that rate) to be at least 25C above ambient.

The major FPGA mfrs provide thermal analysis tools to predict the power 
dissipation and temperature rise of their devices - have you used those 
and then plugged those numbers into post-PAR static analysis?

Cheers

PeteS



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search