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Antti, Thank you very much for your support while messing around with the demo-versions of MicroFPGA. Now everything works out fine. In the end it all was configuration bug in either the Spartan-3 Starter Kit or the Xilinx ISE package! I still think that Xilinx has a great complete solution for FPGA-development. All software has bugs... you just have to find a way to work around them! :-) PS: That LED is blinking like hell now! I can hardly get it to stop! :-) See ya! Magnus Antti Lukats wrote: > "spartan3wiz" <magnus.wedmark@gmail.com> schrieb im Newsbeitrag > news:1166710133.913520.220700@n67g2000cwd.googlegroups.com... > > Hi Antti, > > > > I like what you have done and are trying to do with MicroFPGA. Nice > > idea! > > > > I downloaded your MicroFPGA test-package but I can't get it working > > correctly. As I understand the clock used are created by some kind of > > internal DDS of something? Can you explain this further? Can this give > > problems with differnet circuits? > > > > I tried out both the build.bat for the assembler-example and the > > build.bat for the C-example. Both of them create a download.bit but > > when downloading them using Impact no LED is blinking. > > > Hi Magnus, > > thanks a lot for trying - it seems that you made all correct > there was however a minor typo in assembly example build script > namly project was set to 'blink' and source code was 'leds' as > result an empty hex file was created, and that will not do anything. > > the c example should have compiled out of the box, and assuming the > board specific include file was ok, it should have worked. > > all MicroFpga's start without the need of any external signals > eg no clock or reset is required depending on the MicroFpga > config there may be options to change the clock later to either > different frequency or source. > > note that there is also no need to worry about "startup clock" > setting, the same bitstream will work without changing the clock > option from jtag and from cclk based configuration method. > > S3sk board has LEDs active high, so when the microfpga > is loaded all of them should be half-on because of the fpga > pullups. > > if want to troubleshoot uncomment the "clean" to leave all > files in place and look that the .mem file is not empty > > after configuring with download.bit read back the usercode > should be a5000001 > > if that all doesnt help please contact per email, we do > provide support > > Antti > http://groups.google.com/group/microfpgaArticle: 113826
Antti, I seem to recall that the IO group would not generally endorse any M or D Fin combination of the DFS. Rather, the allowed ones were listed in the user's guide. I can't find it there, and I can't find it in the datasheet. I am looking in the app note... where there is quite a lengthy discussion starting on page 22. The IC designers claim more than 700 ps p-p jitter may cause issues with the locking of the IDELAY ref clock. We will have to go back and look at this first week in January when I am back at work. I will need to know: M, D, and Fin values that you are seeing problems with. We did not use any other feature of the DCM: no connection to CLKFB, so the DLL part is not active. AustinArticle: 113827
xx wrote:
> http://vhdlblog.blogspot.com/
I expect the problem is in tb.vhd
-- Mike Treseler
Article: 113828Austin wrote: > So, what was your M and D value, and > frequency of Clock IN? Were you using the DCM for anything else (any > other outputs connected)? Was the CLKFB input used (it should not have > been if all you needed was the CLKFX output, as using it would > automatically turn on the DLL part of the DCM, and that might have > created some issues (input clock frequency too low for the DLL in that > mode). All of the combinations I tested were listed in my original posts. No, the DCM was only used to create the clock. Other DCMs were being used for other functions but towards the end I removed all of this logic and focused on the idelay. > How soon after the DONE went high was the DCM reset released? Seconds to minutes. > It may be that the oscillator had not stabalized yet. In my original post I write about monitoring the states. But, even if this were the case, the 200ps / tap I measured was constant. Strange problem, but using a dedicated 100 or 200MHz oscillator just for this function seems to work fine.Article: 113829
On Mon, 18 Dec 2006 09:44:18 +0100, Al <alessandro.basili@cern.ch> wrote: >Hi guys, >I have to produce a PCB with a couple of FPGA on it and I was wondering >if the solder mask right under the FPGA would prevent a good heat >dissipation (provided that we will put the thermal paste underneath). >Some of our designers suggested that the gain you have in heat >dissipation you will loose it in short-circuit problems on the mounting, >through the via underneath which are much more of a pain. >Could you give me any suggestion? > >Thanks a lot > >Al I suspect that the solder mask is a similar heat conductor to the thermal paste, so it wouldn't matter much from a thermal standpoint. If you really need to cool the fpga's, a big copper pour on layer 1, under the chip, could be connected by a lot of thermal vias to inner layer planes and maybe another big pour on the far side, with maybe a heatsink glued to the bottom too. We've epoxied pin-fin heatsinks to the tops of fpga's, partly to cool them and partly to disguise them. I'm guessing that cooling the top of a plastic fpga package is about as good as cooling the bottom. JohnArticle: 113830
> The stimulus is automatically applied by the Test Bench Waveofrm wizard,
> it is a clock of 5 periods at 1000ns in total (5 periods). There seems to
> be
> little yellow spikes where the clock positive edges are, I don't know what
> these are supposed to be.
1. You should probably look up in the Xilinx documentation about what the
yellow spikes are all about.
2. Take a look at the testbench code that was generated, (maybe post that up
here for all to see).
3. Maybe there is some problem with your simulator.
I realize that the testbench code that you're using was generated by Mr.
Wizard, but it should roughly look like the following....in fact maybe try
copying the code below into your current testbench code file and comment out
or delete what is there and try simulating. If the code below works then
you should look for differences between it and the Mr. Wizard generated
testbench code (after finding out what yellow spikes are) and try to figure
out what is going on.
entity tb is
end tb
architecture RTL of tb is
signal a: std_logic := '0';
signal y:
begin
a <= not(a) after 100 ns;
DUT : entity work.mod1 port map(a => a, y => y);
end RTL;
KJ
Article: 113831Got it, M=14, D=1. Fin=14.318 MHz. I also need to know: was CLKFB left unused, or was it somehow connected to something? AustinArticle: 113832
early Christmas (Pico) present http://www.microfpga.com/joomla/index.php?option=com_remository&Itemid=27&func=fileinfo&id=4 Xilinx PicoBlaze based MicroFpga's supporting all Xilinx FPGA's with less than 256 I/O from XC2S15 to XC4VLX25 - a total of 112 devices. Spartan3a are not included as they are not fully supported by ISE 8.2 :( My wish that Xilinx would have released full S3A and V5LX(T) support this year did not come true - DATA2MEM doesn not support them yet :( possible only happens with ISE 9.1 release. .. if some one asks what can I do with KCPSM inside an Virtex4 !? Then one of the answers is simple - you can make the christmas lights within minutes - no synthesis, no need to look what pin is clock connected too, just set pad names in PicoBlaze assembler source , run kcpsm assembler + data2mem and configure the FPGA with download.bit - done. Your Christmas LED's blink and wink. with merry christmas wishes Antti with a smily for a change http://www.antti-brain.comArticle: 113833
hi just done the vending machine demo, is there a pin grid to specify the output somewhere i've missed, or does aal this have to be done for each of my projects in the pin assignment editor? i having lots of thoughts on a 16 bit to 8 bit memory interface?? is there already vhdl model, or what is the timing requirements of the sram memory? i need an on chip 2 cycle 16 bit of 64K words arangement. how much solder needs to be rerouted to get access to the adc for project use e.g. PID controller implementations? (i have a diesel vapour fuel control system idea for pertol compression ratio engines, it would need to monitor engine temps and AC generator output and frequency). what uk stockists have the santa clara format IDC headers and sockets? cheers for any help.Article: 113834
Is this your first simulation ever? Perhaps you are not using the tools properly. You have to save the testbench, make sure that the test bench is highlighted in the source pane, (the testbench should be under the mod1), and in the process pane the Simulate Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps there is some other things to watch out for. Then you should try y<='1'; to see if you can get the signal to move. Brad Smallridge AiVision p <xx> wrote in message news:458c623c$1_3@mk-nntp-2.news.uk.tiscali.com... > Hello all, > I am using xilinx ISE 8.2i , my program is as follows, > > entity mod1 is > Port ( a : in STD_LOGIC; > y : out STD_LOGIC); > end mod1; > > architecture Behavioral of mod1 is > > begin > y <= a; > > end Behavioral; > > I need to simulate this simple thing, I created a Test Bench Waveform, > which > creates a simulation. I have a clock signal, a, which has 10 periods 100ns > each, > and an output, y, which is constantly zero. Can anyone explain this ? > >Article: 113835
Austin - I'm not the OP, but I'm the one using a 14.318MHz input with M=14, D=1. CLKFB is not connected since this is not in a range that the DLL will work. My internal frequency meter shows that the DCM is indeed outputing 20.4 MHz. I don't know if the IDELAY is working or not - I've not gotten to that point in my design debug. I'm just want to make sure that Lecroy's problem isn't going to nail me. My reset circuitry is carefully done. I wait for the DCM to LOCK and also produce a stable / correct clock. I have an internal frequency meter in my design, so I wait for the DCM's FX output to be stable, then I release reset on the IDELAYCTRL block. Thanks for your help! Merry Christmas! John Providenza Austin wrote: > Got it, > > M=14, D=1. Fin=14.318 MHz. > > I also need to know: was CLKFB left unused, or was it somehow connected > to something? > > AustinArticle: 113836
Hello, I have seen this question many times in the newsgroups but I did not see a clear answer. I have to perform various operations on arrays of data (such as multiplication, addition, finding mean, etc.). I have code written in Matlab and would like to translate it to vhdl. I understand that such subroutines as imagesc, imwrite, etc. might not be possible to translate to vhdl and will need to be written (or similar functions might be already implemented in vhdl). Is there anyway of directly translating Matlab code directly to vhdl? Can this be done using Simulink (Xilinx System Generator)? I don't have System Generator at home and Xilinx doesn't seem to have evaluation version (asking for Product Serial Number). Or maybe my question should be: can this be done in Simulink to start with? I have Xilinx FPGA/ISE. And if this can not be done using System Generator, is there anything else that can be used? Please let me know if my requirements are not very clear. Thanks, VitaliyArticle: 113837
Hello,
I am currently working on a Verilog module within ISE and Modelsim, and
within this module it gives me the error: Signal <foo> is assigned but
never used.
I currently have a 2D array that is holding data for me, and I access
this data within a task, which is called from another block when I need
to compare the new incoming data with the older data, and
update/replace as needed. The way that I am trying to get that done is
close to this example code I had written:
-----------------------------------------------------------------------------------------
module top_mod(
input clk,
input switch_i,
input [2:0] addr_i,
output reg [3:0] data_o
);
reg [3:0] data0 = 4'b0000;
reg [3:0] data1 = 4'b0001;
reg [3:0] data2 = 4'b0010;
reg [3:0] data3 = 4'b0011;
reg [3:0] data4 = 4'b0100;
reg [3:0] data5 = 4'b0101;
reg [3:0] data6 = 4'b0111;
reg [3:0] data7 = 4'b1000;
reg [3:0] data_array [7:0];
reg [3:0] data_hold;
always @(posedge clk)
begin
if (switch_i)
switch_on;
else
data_o = data_o;
end
task switch_on;
begin
data_hold = data_array[addr_i];
data_o = {switch_i,data_hold[2:0]};
end
endtask
endmodule
-----------------------------------------------------------------------------------------
In this example I am not writing back to the array, but you get the
basic idea, and this does give me the "Signal <data_hold> is assigned
but never used." error. Does anyone know why this is happening, or
perhaps a better way to read out part of a vector in a 2D array? Let me
know if any more info is needed. Thanks for any help!
-Mark
Article: 113838Hello, I'am looking for a software to efficiently implement FPGA designs, or target to embeded processor, - simpler, - shorter source - quality of results May be mobius make it all, anyone has been tested mobius, or another sofware Thank's François Rigaud Observatoire de Paris-Meudon, France PS: http://www.codetronix.com/ --------------= Posted using GrabIt =---------------- ------= Binary Usenet downloading made easy =--------- -= Get GrabIt for free from http://www.shemes.com/ =-Article: 113839
Hello all, I am trying a new design that includes DDR2. This design has multiple accses to the memory and I need to use bank interleaving and auto-precharge function (only on the last access to the read line ,as expected). CAN someone reccomand me a decent controller that does so (even if i need to buy it)? I have tried xilinx MIG but it doesn't support interleaving. thanks Guy.Article: 113840
Hi, I am designing an OPB Peripheral which has to act as a master and a slave on the OPB Bus . I am not happy with the IPIF master logic functionality provided by Xilinx . I am trying to design the master logic support myself , but the VHDL code for the Xilinx implementation is not provided in any of the directories .. Does any one have any documents / app notes , which discusses guidelines for the master logic design? thank you venuArticle: 113841
Try Northwest Logic--they do good work but you have to pay for it. http://www.nwlogic.com/ Terry Brown On Sun, 24 Dec 2006 03:46:05 -0800, Guy_FPGA wrote: > Hello all, > I am trying a new design that includes DDR2. This design has multiple > accses to the memory and I need to use bank interleaving and > auto-precharge function (only on the last access to the read line ,as > expected). CAN someone reccomand me a decent controller that does so > (even if i need to buy it)? I have tried xilinx MIG but it doesn't > support interleaving. > > thanks > > Guy.Article: 113842
hey terry, Did you use their IP? what was your exact application? Any other oppinion would help... thanks Guy tbrown wrote: > Try Northwest Logic--they do good work but you have to pay for it. > > http://www.nwlogic.com/ > > Terry Brown > > > > > On Sun, 24 Dec 2006 03:46:05 -0800, Guy_FPGA wrote: > > > Hello all, > > I am trying a new design that includes DDR2. This design has multiple > > accses to the memory and I need to use bank interleaving and > > auto-precharge function (only on the last access to the read line ,as > > expected). CAN someone reccomand me a decent controller that does so > > (even if i need to buy it)? I have tried xilinx MIG but it doesn't > > support interleaving. > > > > thanks > > > > Guy.Article: 113843
<mwiesbock@gmail.com> wrote in message news:1166948288.146776.100020@79g2000cws.googlegroups.com... > Hello, > > I am currently working on a Verilog module within ISE and Modelsim, and > within this module it gives me the error: Signal <foo> is assigned but > never used. > > I currently have a 2D array that is holding data for me, and I access > this data within a task, which is called from another block when I need > to compare the new incoming data with the older data, and > update/replace as needed. The way that I am trying to get that done is > close to this example code I had written: <snip> > > In this example I am not writing back to the array, but you get the > basic idea, and this does give me the "Signal <data_hold> is assigned > but never used." error. Does anyone know why this is happening, or > perhaps a better way to read out part of a vector in a 2D array? Let me > know if any more info is needed. Thanks for any help! Synthesis will optomize out anything that does not factor into the equations for an output pin of the TOP level entity. For example, if your top level entity has no outputs then everything will get optomized away. Even though you may be assigning to signal 'data_hold', if 'data_hold' is not an output of the top level entity itself or it does not cause any changes in any of the outputs that you do have then they will get optomized away and result in the warning that you're seeing. Check your code for places where you use 'data_hold' and see where the path to the output pins of the device breaks down. KJArticle: 113844
mwiesbock@gmail.com wrote: > Hello, > > I am currently working on a Verilog module within ISE and Modelsim, and > within this module it gives me the error: Signal <foo> is assigned but > never used. It looks like data_hold[3] is assigned but never used. In the task, you assign all 4 bits of data_hold, but only bits [2:0] are used to form data_o. XST reports individual bits that are assigned but not used, so I would expect to see: WARNING:Xst:646 - Signal <data_hold<3>> is assigned but never used.Article: 113845
chat wrote:
> I'am looking for a software to
> efficiently implement FPGA designs, or target to embeded processor,
> - simpler,
> - shorter source
> - quality of results
> May be mobius make it all,
> anyone has been tested mobius,
> or another sofware
I haven't used it, but it looks similar to Matlab.
The articles are interesting at the DSP level
but the examples are weak at the hardware level.
In this example:
http://www.codetronix.com/index.php?module=documents&JAS_DocumentManager_op=downloadFile&JAS_File_id=27
a vhdl wrapper file is required for the simplest of designs.
The mobius code itself is short but not portable.
The do-it-yourself hardware interface is a bigger problem than direct
vhdl or verilog synthesis would have been in this case.
See also:
http://groups.google.com/groups/search?q=functional+hardware+myhdl+process
-- Mike Treseler
Article: 113846> Is this your first simulation ever? Perhaps you are not using > the tools properly. You have to save the testbench, make sure that The fact that I am getting a simulation indicates to me that I have been using the tools correctly. The fact that the simulation is not working indicate to me that xilinx tools do not work 'out of the box' (if at all). > the test bench is highlighted in the source pane, (the testbench > should be under the mod1), and in the process pane the Simulate > Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps > there is some other things to watch out for. > > Then you should try y<='1'; to see if you can get the signal to > move. y<='1'; is the same, output is y = 0Article: 113847
> I expect the problem is in tb.vhd What am I supposed to ask?Article: 113848
> 1. You should probably look up in the Xilinx documentation about what the > yellow spikes are all about. These comment were made so that people know what I am looking at. Reading the manuals will come later, after I know the xilinx tools do work. After all, what good is it to learn a tool if it doesn't work? > 2. Take a look at the testbench code that was generated, (maybe post that up > here for all to see). I explained what I did, surely you can duplicate it and see what the code is ? > 3. Maybe there is some problem with your simulator. > > I realize that the testbench code that you're using was generated by Mr. > Wizard, but it should roughly look like the following....in fact maybe try > copying the code below into your current testbench code file and comment out > or delete what is there and try simulating. If the code below works then > you should look for differences between it and the Mr. Wizard generated > testbench code (after finding out what yellow spikes are) and try to figure > out what is going on. OK I'll see if I can, but really, I don't want to be debugging for xilinx, this is their job. If it doesn't work, I'll wait for their next version. > > entity tb is > end tb > > architecture RTL of tb is > signal a: std_logic := '0'; > signal y: > begin > a <= not(a) after 100 ns; > DUT : entity work.mod1 port map(a => a, y => y); > end RTL; > > KJ > >Article: 113849
> Is this your first simulation ever? Perhaps you are not using > the tools properly. You have to save the testbench, make sure that The fact that the simulation is displays shows that I am using it correctly. > the test bench is highlighted in the source pane, (the testbench > should be under the mod1), and in the process pane the Simulate > Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps > there is some other things to watch out for. > > Then you should try y<='1'; to see if you can get the signal to > move. still y = 0
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