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Messages from 118350

Article: 118350
Subject: Re: XTREME DSP Development Kit2 JTAG Problem
From: mtsukanov@gmail.com
Date: 24 Apr 2007 10:16:47 -0700
Links: << >>  << T >>  << A >>
if the fpga is stuck in reset (prog_b pulled low), then the jtag chain
will fail. thats a start


On Apr 24, 1:52 am, "Bryan" <s...@xilinx.com> wrote:
> Hi all, I m using the Xtreme DSP Development Kit 2 with Viretex 2
> XC2V3000-4FG676 FPGA.
>
> While doing JTAG cosimulation in Simulink, i got an error message:"Error
> configuring  device: A problem may exist in the hardware configuration.
> Check that the cable, scan chain and power connections are intact, that the
> specified scan chain configuration matches the actual hardware,and that the
> power supply is adequateand delivering the correct voltage." Thanks for the
> help.



Article: 118351
Subject: Re: XPS behavioral simulation fails: the design is not loaded
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 24 Apr 2007 11:07:35 -0700
Links: << >>  << T >>  << A >>
ferorcue wrote:
> hello, thank you for answering but i am not able to solve my problem
> yet.
> 
> the generic C_BUS_WIDHT has a default of 1, and the upper levels are
> using the or_gate.vhd file with the same generic.
> 
> What make me angry is that i cannot modify this files, because they
> are cores from XILINX, that means that i have not modified them, and
> it should work.


The alternative is to enter the design
directly in vhdl or verilog for synthesis.

This way, I still find frustrations,
but I can simulate and edit the code as well
as swear at it :)

        -- Mike Treseler

Article: 118352
Subject: Re: VHDL editing with UltraEdit
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Tue, 24 Apr 2007 18:29:59 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-04-24, Nicolas Matringe <nicolas.matringe@fre.fre> wrote:
> The problem with emacs is that all its shortcuts are rather alien to 
> most Windows users. I have stopped trying to convince my colleagues to 
> use it.

Although I haven't tried it myself (since Windows shortcuts are alien to
me :)) I've heard about an emacs mode that mimics some common
windows shortcuts. A quick google search reveals that www.cua.dk seems
to host the CUA mode for emacs which allows the use of ctrl-v, ctrl-c
ctrl-z, and ctrl-x as expected on windows. (While still allowing C-x
style emacs keybindings to function as expected as long as no region is
active.)

/Andreas

Article: 118353
Subject: Re: FPGA and DAC for wave generation
From: Gabor <gabor@alacron.com>
Date: 24 Apr 2007 12:44:53 -0700
Links: << >>  << T >>  << A >>
On Apr 24, 7:25 am, Sheetal <sheetalgandhi...@gmail.com> wrote:
> hi..I'm a university student familiar with the only the basics of VHDL
> and FPGA implementation..For my project, I'm trying a make a sine
> wave, ramp, triangular and square wave generator which outputs
> required wave of required amplitude and required frequency
>
> The FPGA is connected with DAC thru I2C bus..
>
> The development board (nanoboard) has on- board freq of 20 mhz...now the
> dac being connected to the I2c bus can work upto max 400 Mhz..so a
> suitable clock divisor has to be implemented ..thus a low frequency
> can be used as SCL input to DAC..
>

400 KHz, i hope.  This means you're not going to get very high
frequencies
on your output, but you must realize that already...

> a)Now, for the sine and square wave, I'm assuming that we can use the
> same look-up table(values ranging from 0 to 256)for the output values
> of DAC.for obtaining different frequencies, only the SCL needs to be
> changed . i.e.if SCl rate is high, the DAC would output from 0 to 256,
> then to 0 at a faster rate, if SCL is low, it would output the same
> values, but with some delay. THus, variable frequency can be obtained
> by changing SCL rate..am I correct in assuming so?
>

This is one way to do it, but not how it is generally done.  Realizing
that your I2C update rate is on the order of 1/20th of the SCL
frequency already, making the update rate slower will even further
limit your output quality due to lower update rate.  In a typical
waveform generator, the data is sent to the DAC at the highest
frequency possible.  This reduces output filtering requirements.
Changes in output frequency and waveform are made by altering
the increment added to the table index on each DAC update.

> b)If this is correct, can anyone please tell me the relationship
> between SCL and output wave frequency..if such a formula/well defined
> relationship does exist
>

This depends on the DAC you're using.  Most I2C devices are
written by sending a 7-bit address plus write bit followed by an
8 bit value for a simple device (one internal register) or two
8-bit values (internal address followed by data) for multi-
register devices.  Additional cycles (always another 8-bit
word at a time) may be required if the value you're writing
is more than 8 bits (e.g. 12-bit DAC needs at least two
data writes plus any address and "subaddress" bytes).

In any case SCL will not be free-running (take a look at the
I2C spec or the DAC device datasheet).  So you'll have
some additional time to generate start and stop conditions
on the bus.  Some very simple DAC devices may allow
you to write continuously after startup.  Again you'll need to
check your device's datasheet.

So now you've got some frequency that you can update the
DAC in the low 10's of KHz rate at best.  Your output wave
frequency will then depend on how many table look-ups
you do per complete waveform.  As I said earlier, it is the
latter that normally changes the frequency in a typical
waveform generator.  i.e. you may have a 128 word
waveform table.  So to get a frequency of 1/128 of the
DAC update frequency you'd increment the table index
by 1 on each update.  Increasing the index increment
will increase the frequency.  It is also possible to increment
the index by a non-integer amount (with or without
table interpolation depending on requirements for
output accuracy).

HTH,
Gabor

> c) Also, can anyone tell me about a good link for a simple tutorial on
> implementing look-up table?I did find some on the web, but they all
> seemed to be complicated..either because they ARE..or because my mind
> has gone all-blank right now, with the submission date coming so
> near..
>
> Any help at this time would be hugely appreciated
>
> Kind Regards,
> Sheetal Gandhi



Article: 118354
Subject: Altera DPA compatible with Xilinx IOSERDES?
From: jhallen@TheWorld.com (Joseph H Allen)
Date: Tue, 24 Apr 2007 19:49:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
Has anyone had success interfacing Altera DPA with Xilinx
ISERDES/OSERDES/IDELAY?  Is 1 Gb/s/pin feasible for Virtex-5 and Stratix-II?

(did having both Altera and Xilinx on the same board cause some kind of
exposion? :-)

I'm considering using a Virtex-5 LXT for its nice x8 PCI-E block in an
otherwise mostly Altera design.
-- 
/*  jhallen@world.std.com AB1GO */                        /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 118355
Subject: Re: VHDL editing with UltraEdit
From: Nicolas Matringe <nicolas.matringe@fre.fre>
Date: Tue, 24 Apr 2007 21:50:27 +0200
Links: << >>  << T >>  << A >>
wallge a écrit :
> I don't know about ultraedit,
> 
> but emacs VHDL mode does a wonderful job colorizing and
> beautifying source code.
> I use it exclusively... It also has a nice hierarchy browser and
> lots of other VHDL specific functionality built in.
> 
> There are some nice cheat sheets available through
> a google search that have all the important keyboard shortcuts
> as well...

The problem with emacs is that all its shortcuts are rather alien to 
most Windows users. I have stopped trying to convince my colleagues to 
use it.

Nicolas

Article: 118356
Subject: EDK Simulation library compilation wizard can't find modelsim
From: Rebecca <pang.dudu.pang@hotmail.com>
Date: 24 Apr 2007 13:41:05 -0700
Links: << >>  << T >>  << A >>
Hello,
I am using the Simulation library compilation wizard in EDK9.1.01i and
was told that "Modlelsim isn't found!  please ensure this simulator is
correctly intalled and/or the correspoind enviroment settings are
available"
I do have Modelsim 6.2e installed at my computer and it works. The
only system variable that I set for modlesim is about the license.
Should I set any other variables?
And EDK says it ony support Modelsim Se/Pe 6.1e. I am wondering if it
can support the later versions.  But anyway, I installed Modelsim se
6.1e and got the same result.
Any suggestion?
By the way, I can't get the wizard work successfully for EDK8.2 either
and I have to do it manually. Am I wrong somewhere?
Thanks a lot,
Rebecca


Article: 118357
Subject: The simulation library compilation wizard of EDK can't find modelsim
From: Rebecca <pang.dudu.pang@hotmail.com>
Date: 24 Apr 2007 13:57:04 -0700
Links: << >>  << T >>  << A >>
Hi, All:
When I complie the simulation library in EDK 9.1.01i using the library
compilation wizard, it told me that "modlesim is not found! please
ensure that the simulator is correctly installed and/or the necessary
envoroment settings are available". But I do have modelsim se 6.2e and
6.1e intalled on my machine and they work fine. The only system
variable I set for modelsim is LM_LICENSE_FILE, should I set any other
variables?
And EDK says it only support Modelsim SE/PE 6.1e. I am wondering can't
it support the later versions? But anyway, I intalled 6.1e and got the
same result.
By the way, the wizard didn't work when I used EDK 8.2 and I had to do
it manually? Am I wrong somewhere?

Thanks a lot,
Rebecca


Article: 118358
Subject: Re: FPGA and DAC for wave generation
From: Peter Alfke <peter@xilinx.com>
Date: 24 Apr 2007 15:16:58 -0700
Links: << >>  << T >>  << A >>
To generate programmable frequencies in an FPGA, use Direct Digital
Synthesis (DDS)
Look it up in google.
Driving the DAC through an I2C bus seems to be unnecessarily slow.
If your FPGA has BlockRAMs, then look-up tables are very easy to
implement.

You did not mention any parameter values, but your project seems very
easy. And even fun.
Peter Alfke

On Apr 24, 4:25 am, Sheetal <sheetalgandhi...@gmail.com> wrote:
> hi..I'm a university student familiar with the only the basics of VHDL
> and FPGA implementation..For my project, I'm trying a make a sine
> wave, ramp, triangular and square wave generator which outputs
> required wave of required amplitude and required frequency
>
> The FPGA is connected with DAC thru I2C bus..
>
> The development board (nanoboard) has on- board freq of 20 mhz...now the
> dac being connected to the I2c bus can work upto max 400 Mhz..so a
> suitable clock divisor has to be implemented ..thus a low frequency
> can be used as SCL input to DAC..
>
> a)Now, for the sine and square wave, I'm assuming that we can use the
> same look-up table(values ranging from 0 to 256)for the output values
> of DAC.for obtaining different frequencies, only the SCL needs to be
> changed . i.e.if SCl rate is high, the DAC would output from 0 to 256,
> then to 0 at a faster rate, if SCL is low, it would output the same
> values, but with some delay. THus, variable frequency can be obtained
> by changing SCL rate..am I correct in assuming so?
>
> b)If this is correct, can anyone please tell me the relationship
> between SCL and output wave frequency..if such a formula/well defined
> relationship does exist
>
> c) Also, can anyone tell me about a good link for a simple tutorial on
> implementing look-up table?I did find some on the web, but they all
> seemed to be complicated..either because they ARE..or because my mind
> has gone all-blank right now, with the submission date coming so
> near..
>
> Any help at this time would be hugely appreciated
>
> Kind Regards,
> Sheetal Gandhi



Article: 118359
Subject: Problem with PowerPC PIT interrupt
From: Matthew Hicks <mdhicks2@uiuc.edu>
Date: Tue, 24 Apr 2007 22:25:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
I'm working on a RTOS for the PowerPC chip on the Virtex-II XUP board.  I 
need an interrupt to trigger so I run my scheduler at regular intervals, 
so I setup the PIT to trigger an interrupt at 1s (purely for testing reasons, 
I will be going down to around 5ms).  The program seems to pause when I finally 
enable the interrupt and I see no signs that the handler has been run.  I 
looked at several references and spent a day shifting around my code, to 
no avail.   If someone could take a peek at my code below and offer assistance 
that would be great.  Thanks.


#include "xparameters.h"
#include "stdio.h"
#include "xbasic_types.h"
#include "gpio_header.h"
#include "xexception_l.h"
#include "xtime_l.h"

Xuint32 status;

void pit_InterruptHandler(void *dataPtr)
{	
	status = 55;
	XTime_PITClearInterrupt();
}

int main(void)
{
	Xuint32 DataRead;
	
	XExc_Init();
	XExc_RegisterHandler(XEXC_ID_PIT_INT, (XExceptionHandler)pit_InterruptHandler, 
(void*) 0);
	XTime_PITSetInterval(100000);
	XTime_PITEnableAutoReload();
	XExc_mEnableExceptions(XEXC_NON_CRITICAL);
	
   	print("-- Entering main() --\r\n");
	print("\r\nRunning GpioOutputExample() for LEDs_4Bit...\r\n");
	status = GpioOutputExample(XPAR_LEDS_4BIT_DEVICE_ID,4);
	if(status == 0)
	{
		print("GpioOutputExample PASSED.\r\n");
	}
	else
	{
		print("GpioOutputExample FAILED.\r\n");
	}
	
	XTime_PITClearInterrupt();
	XTime_PITEnableInterrupt();
	
	print("Here\r\n");
	status = 0;
	while(status != 55)
	{
		;
	}
		
	print("-- Exiting main() --\r\n");
	
	return 0;
}


---Matthew Hicks



Article: 118360
Subject: XPS and inout ports: is it possible?
From: IB <ibonesana@freesurf.ch>
Date: Wed, 25 Apr 2007 01:42:40 +0200
Links: << >>  << T >>  << A >>
Hi,
Im woerking on a Xilinx Virtex-II pro with Xilinx Platform Studio 7.1

My design has a bidirectional 8-bits bus. If I synthesize with Project 
Navigator and then I download the result using impact. everything works 
without any problem.

I tried to integrate the design in a custom IP and i got this error 
during the synthesis:

ERROR:Xst:759 - "c:/xps2/synthesis/../hdl/opbusblogic_0_wrapper.vhd" 
line 94: No default binding for component: <opbusblogic>. Ports 
<data_bus_I,data_bus_O,data_bus_T> are not on the entity.

It seems that the original design

port(
...
data_bus: inout std_logic_vector(7 downto 0);
...);

has been converted in

port(
...
data_bus_I : in std_logic_vector(7 downto 0);
data_bus_O : out std_logic_vector(7 downto 0);
data_bus_T : out std_logic;
...);

of course, these three signals are not defined in my design.

What can I do?

Thans,
Ivano.

Article: 118361
Subject: Re: FPGA and DAC for wave generation
From: -jg <Jim.Granville@gmail.com>
Date: 24 Apr 2007 17:29:26 -0700
Links: << >>  << T >>  << A >>

Sheetal wrote:
> hi..I'm a university student familiar with the only the basics of VHDL
> and FPGA implementation..For my project, I'm trying a make a sine
> wave, ramp, triangular and square wave generator which outputs
> required wave of required amplitude and required frequency
>
> The FPGA is connected with DAC thru I2C bus..
>
> The development board (nanoboard) has on- board freq of 20 mhz...now the
> dac being connected to the I2c bus can work upto max 400 Mhz..so a
> suitable clock divisor has to be implemented ..thus a low frequency
> can be used as SCL input to DAC..

Tip: Some tutors will mark incorrect units wrong, so take care on
these.
m=milli, and M-Mega, and check when you write MHz that is what you
mean.


>
> a)Now, for the sine and square wave, I'm assuming that we can use the
> same look-up table(values ranging from 0 to 256)for the output values
> of DAC.for obtaining different frequencies, only the SCL needs to be
> changed . i.e.if SCl rate is high, the DAC would output from 0 to 256,
> then to 0 at a faster rate, if SCL is low, it would output the same
> values, but with some delay. THus, variable frequency can be obtained
> by changing SCL rate..am I correct in assuming so?

Broadly speaking, yes.

>
> b)If this is correct, can anyone please tell me the relationship
> between SCL and output wave frequency..if such a formula/well defined
> relationship does exist

Read the data sheet on the DAC.
Each DAC update will take an i2c frame, of a number of clocks
[address.data]

>
> c) Also, can anyone tell me about a good link for a simple tutorial on
> implementing look-up table?I did find some on the web, but they all
> seemed to be complicated..either because they ARE..or because my mind
> has gone all-blank right now, with the submission date coming so
> near..

How hard can a table be - you can draw a Graph, and use XCELL ?
Tip: For table compression, it is common to fold the table, so for a
sine wave,
how much of the whole sine cycle, do you actually need to store ?

I'd look for a SPI DAC, as it seems silly to constrain the MAX clock
speed
of a design, by the i2c MAX - SPI DACs can run closer to the FPGA
speeds.

-jg


Article: 118362
Subject: compact flash slave ip core
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: 24 Apr 2007 19:49:11 -0700
Links: << >>  << T >>  << A >>
Where can I find the compact flash slave ip core for free,thanks!


Article: 118363
Subject: Incorrect response from MAC FIR Low Pass Filter
From: "Bryan" <sfoo@xilinx.com>
Date: Wed, 25 Apr 2007 11:23:25 +0800
Links: << >>  << T >>  << A >>
Hi all, thanks to your help, I have managed to solve the JTAG problem on my 
XTREME DSP Development Kit.

However I had a response which attenuates all frequencies even though my 
design is low pass filter.. Anybody can help me with that because i checked 
through my design n it seems fine. It is a MAC based FIR 43 tap filter 
though. 



Article: 118364
Subject: Re: Slave PLB core interrupt
From: Manny <mloulah@hotmail.com>
Date: 24 Apr 2007 21:18:24 -0700
Links: << >>  << T >>  << A >>
> Appearently your source code specifies (explicitly or
> implicitly) sections in reverse order, ie first the code for fffff070
> and then the code for00000070.  If you manage to rearrange this in
> your sources, the error should go away.

I rearranged my functions using a demo program as a template and
indeed it worked. So you'r right 100% on this.

Thanks a lot for the hint.

Regards,
-Manny


Article: 118365
Subject: Using PCI in EDK 8.21
From: sheikh.m.farhan@gmail.com
Date: 24 Apr 2007 21:53:41 -0700
Links: << >>  << T >>  << A >>
Hi,
I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have
not been able to synthesize it properly. I am using a custom board
with Virtex II, I include the PCI bridge during the BSB wizard. Is the
assembly view, I configure the IP to be used as a target. My first
milestone is to put PCI target on an FPGA board withe the PCI edge
connector, put it in a PC and the PC should detect the PCI board. I
need to have the PCI target to be configured from the PC side.
Now my questions are:
1. When I set all the configurations for the PCI to be used as a
target, why dont I see the IDSEL line in my ucf file?
2. In the generated ucf, I see two clocks with the name PCI_CLK_FB and
PCI_CLK_OUT. After digging, I came to know that these clocks make more
sense when the PCI bridge is to be used as a host (on a mothernboard
as is used in ML310 board) where PCI_CLK_OUT is the source PCI clock
and PCI_CLK_FB is the feedback clock. AFter consulting some more MHS
files from the reference designs, I do see the PCLK appearing in the
ucf and MHS file (instead of PCI_CLK_FB and PCI_CLK_OUT clocks).
When I set the PCI bridge as a target (by setting
C_INCLUDE_OPB_MST2PCI_TARG = 0), I dont see any IDSEL line appearing
in my ucf, why is that so?
3. Synthesizing the project as it is, without the IDSEL line available
at the ports, I start getting NgdBuild errors on ilmb_BE line to be
driven by mulitple sources. I am pasting the MHS file. Kindly guide
how to achieve the first milestone.

Farhan



#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build
EDK_Im_Sp2.4
# Tue Apr 24 17:00:33 2007
# Target Board:  Custom
# Family:	 virtex2
# Device:	 xc2v1000
# Package:	 fg456
# Speed Grade:	 -4
# Processor: Microblaze
# System clock frequency: 40.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
#
##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_PCI_Bridge_PAR = fpga_0_PCI_Bridge_PAR, DIR = IO
 PORT fpga_0_PCI_Bridge_PERR_N = fpga_0_PCI_Bridge_PERR_N, DIR = IO
 PORT fpga_0_PCI_Bridge_SERR_N = fpga_0_PCI_Bridge_SERR_N, DIR = IO
 PORT fpga_0_PCI_Bridge_IRDY_N = fpga_0_PCI_Bridge_IRDY_N, DIR = IO
 PORT fpga_0_PCI_Bridge_FRAME_N = fpga_0_PCI_Bridge_FRAME_N, DIR = IO
 PORT fpga_0_PCI_Bridge_DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N, DIR =
IO
 PORT fpga_0_PCI_Bridge_STOP_N = fpga_0_PCI_Bridge_STOP_N, DIR = IO
 PORT fpga_0_PCI_Bridge_TRDY_N = fpga_0_PCI_Bridge_TRDY_N, DIR = IO
 PORT fpga_0_PCI_Bridge_AD = fpga_0_PCI_Bridge_AD, DIR = IO, VEC =
[31:0]
 PORT fpga_0_PCI_Bridge_CBE = fpga_0_PCI_Bridge_CBE, DIR = IO, VEC =
[3:0]
 PORT fpga_0_PCI_CLK_FB = pci_feedback_s, DIR = I, SIGIS = CLK
 PORT fpga_0_PCI_CLK_OUT = pci_clk_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
40000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 5.00.c
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_pci
 PARAMETER INSTANCE = PCI_Bridge
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DMA_CHAN_TYPE = 0
 PARAMETER C_INCLUDE_INTR_MODULE = 0
 PARAMETER C_PCIBAR_NUM = 2
 PARAMETER C_TRIG_PCI_READ_OCC_LEVEL = 8
 PARAMETER C_TRIG_IPIF_WRBURST_OCC_LEVEL = 8
 PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 8
 PARAMETER C_INHIBIT_IPIF_READ_VAC_LEVEL = 8
 PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL = 8
 PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 15
 PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 15
 PARAMETER C_MAX_LAT = 0x54
 PARAMETER C_MIN_GNT = 0x32
 PARAMETER C_NUM_IDSEL = 1
 PARAMETER C_DMA_LENGTH_WIDTH = 11
 PARAMETER C_INCLUDE_DEV_PENCODER = 0
 PARAMETER C_DEV_MIR_ENABLE = 0
 PARAMETER C_DEV_BLK_ID = 6
 PARAMETER C_INCLUDE_INTR_A_BUF = 1
 PARAMETER C_INCLUDE_REQ_N_BUF = 1
 PARAMETER C_IPIFBAR_NUM = 1
 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
 PARAMETER C_IPIF_SPACETYPE_1 = 0
 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x20000000
 PARAMETER C_IPIFBAR_0 = 0x20000000
 PARAMETER C_IPIF_HIGHADDR_0 = 0x3fffffff
 PARAMETER C_IPIFBAR_1 = 0xe8000000
 PARAMETER C_IPIF_HIGHADDR_1 = 0xebffffff
 PARAMETER C_BASEADDR = 0x42600000
 PARAMETER C_HIGHADDR = 0x4260ffff
 PARAMETER C_DMA_BASEADDR = 0x42800000
 PARAMETER C_DMA_HIGHADDR = 0x4280ffff
 PARAMETER C_INCLUDE_OPB_MST2PCI_TARG = 0
 PARAMETER C_INCLUDE_PCI_CONFIG = 0
 PARAMETER C_DEVICE_ID = 0x1004
 PARAMETER C_VENDOR_ID = 0x1004
 PARAMETER C_CLASS_CODE = 0x050000
 PARAMETER C_REV_ID = 0x01
 PARAMETER C_SUBSYSTEM_ID = 0xDCBA
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x9876
 PARAMETER C_INCLUDE_DEV_ISC = 0
 PARAMETER C_INCLUDE_ERR_REG_MODULE = 0
 PARAMETER C_IPIF2PCI_FIFO_ABUS_WIDTH = 6
 PARAMETER C_PCI2IPIF_FIFO_ABUS_WIDTH = 6
 BUS_INTERFACE MSOPB = mb_opb
 PORT PAR = fpga_0_PCI_Bridge_PAR
 PORT PERR_N = fpga_0_PCI_Bridge_PERR_N
 PORT SERR_N = fpga_0_PCI_Bridge_SERR_N
 PORT IRDY_N = fpga_0_PCI_Bridge_IRDY_N
 PORT FRAME_N = fpga_0_PCI_Bridge_FRAME_N
 PORT DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N
 PORT STOP_N = fpga_0_PCI_Bridge_STOP_N
 PORT TRDY_N = fpga_0_PCI_Bridge_TRDY_N
 PORT AD = fpga_0_PCI_Bridge_AD
 PORT CBE = fpga_0_PCI_Bridge_CBE
 PORT PCLK = pci_feedback_s
 PORT RST_N = sys_rst_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKFX_BUF = TRUE
 PARAMETER C_CLKFX_DIVIDE = 6
 PARAMETER C_CLKFX_MULTIPLY = 5
 PARAMETER C_CLKIN_PERIOD = 25.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DFS_FREQUENCY_MODE = LOW
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFX = pci_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END


Article: 118366
Subject: Using OPB PCI Bridge in EDK 8.2i
From: sheikh.m.farhan@gmail.com
Date: 24 Apr 2007 22:10:46 -0700
Links: << >>  << T >>  << A >>
Hi,
I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have
not been able to synthesize it properly. I am using a custom board
with Virtex II, I include the PCI bridge during the BSB wizard. Is the
assembly view, I configure the IP to be used as a target. My first
milestone is to put PCI target on an FPGA board withe the PCI edge
connector, put it in a PC and the PC should detect the PCI board. I
need to have the PCI target to be configured from the PC side.
Now my questions are:
1. When I set all the configurations for the PCI to be used as a
target, why dont I see the IDSEL line in my ucf file?
2. In the generated ucf, I see two clocks with the name PCI_CLK_FB and
PCI_CLK_OUT. After digging, I came to know that these clocks make more
sense when the PCI bridge is to be used as a host (on a mothernboard
as is used in ML310 board) where PCI_CLK_OUT is the source PCI clock
and PCI_CLK_FB is the feedback clock. AFter consulting some more MHS
files from the reference designs, I do see the PCLK appearing in the
ucf and MHS file (instead of PCI_CLK_FB and PCI_CLK_OUT clocks).
When I set the PCI bridge as a target (by setting
C_INCLUDE_OPB_MST2PCI_TARG = 0), I dont see any IDSEL line appearing
in my ucf, why is that so?
3. Synthesizing the project as it is, without the IDSEL line available
at the ports, I start getting NgdBuild errors on ilmb_BE line to be
driven by mulitple sources. I am pasting the MHS file. Kindly guide
how to achieve the first milestone.

Farhan



#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build
EDK_Im_Sp2.4
# Tue Apr 24 17:00:33 2007
# Target Board:  Custom
# Family:	 virtex2
# Device:	 xc2v1000
# Package:	 fg456
# Speed Grade:	 -4
# Processor: Microblaze
# System clock frequency: 40.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
#
##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_PCI_Bridge_PAR = fpga_0_PCI_Bridge_PAR, DIR = IO
 PORT fpga_0_PCI_Bridge_PERR_N = fpga_0_PCI_Bridge_PERR_N, DIR = IO
 PORT fpga_0_PCI_Bridge_SERR_N = fpga_0_PCI_Bridge_SERR_N, DIR = IO
 PORT fpga_0_PCI_Bridge_IRDY_N = fpga_0_PCI_Bridge_IRDY_N, DIR = IO
 PORT fpga_0_PCI_Bridge_FRAME_N = fpga_0_PCI_Bridge_FRAME_N, DIR = IO
 PORT fpga_0_PCI_Bridge_DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N, DIR =
IO
 PORT fpga_0_PCI_Bridge_STOP_N = fpga_0_PCI_Bridge_STOP_N, DIR = IO
 PORT fpga_0_PCI_Bridge_TRDY_N = fpga_0_PCI_Bridge_TRDY_N, DIR = IO
 PORT fpga_0_PCI_Bridge_AD = fpga_0_PCI_Bridge_AD, DIR = IO, VEC =
[31:0]
 PORT fpga_0_PCI_Bridge_CBE = fpga_0_PCI_Bridge_CBE, DIR = IO, VEC =
[3:0]
 PORT fpga_0_PCI_CLK_FB = pci_feedback_s, DIR = I, SIGIS = CLK
 PORT fpga_0_PCI_CLK_OUT = pci_clk_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
40000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 5.00.c
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_pci
 PARAMETER INSTANCE = PCI_Bridge
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DMA_CHAN_TYPE = 0
 PARAMETER C_INCLUDE_INTR_MODULE = 0
 PARAMETER C_PCIBAR_NUM = 2
 PARAMETER C_TRIG_PCI_READ_OCC_LEVEL = 8
 PARAMETER C_TRIG_IPIF_WRBURST_OCC_LEVEL = 8
 PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 8
 PARAMETER C_INHIBIT_IPIF_READ_VAC_LEVEL = 8
 PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL = 8
 PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 15
 PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 15
 PARAMETER C_MAX_LAT = 0x54
 PARAMETER C_MIN_GNT = 0x32
 PARAMETER C_NUM_IDSEL = 1
 PARAMETER C_DMA_LENGTH_WIDTH = 11
 PARAMETER C_INCLUDE_DEV_PENCODER = 0
 PARAMETER C_DEV_MIR_ENABLE = 0
 PARAMETER C_DEV_BLK_ID = 6
 PARAMETER C_INCLUDE_INTR_A_BUF = 1
 PARAMETER C_INCLUDE_REQ_N_BUF = 1
 PARAMETER C_IPIFBAR_NUM = 1
 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
 PARAMETER C_IPIF_SPACETYPE_1 = 0
 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x20000000
 PARAMETER C_IPIFBAR_0 = 0x20000000
 PARAMETER C_IPIF_HIGHADDR_0 = 0x3fffffff
 PARAMETER C_IPIFBAR_1 = 0xe8000000
 PARAMETER C_IPIF_HIGHADDR_1 = 0xebffffff
 PARAMETER C_BASEADDR = 0x42600000
 PARAMETER C_HIGHADDR = 0x4260ffff
 PARAMETER C_DMA_BASEADDR = 0x42800000
 PARAMETER C_DMA_HIGHADDR = 0x4280ffff
 PARAMETER C_INCLUDE_OPB_MST2PCI_TARG = 0
 PARAMETER C_INCLUDE_PCI_CONFIG = 0
 PARAMETER C_DEVICE_ID = 0x1004
 PARAMETER C_VENDOR_ID = 0x1004
 PARAMETER C_CLASS_CODE = 0x050000
 PARAMETER C_REV_ID = 0x01
 PARAMETER C_SUBSYSTEM_ID = 0xDCBA
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x9876
 PARAMETER C_INCLUDE_DEV_ISC = 0
 PARAMETER C_INCLUDE_ERR_REG_MODULE = 0
 PARAMETER C_IPIF2PCI_FIFO_ABUS_WIDTH = 6
 PARAMETER C_PCI2IPIF_FIFO_ABUS_WIDTH = 6
 BUS_INTERFACE MSOPB = mb_opb
 PORT PAR = fpga_0_PCI_Bridge_PAR
 PORT PERR_N = fpga_0_PCI_Bridge_PERR_N
 PORT SERR_N = fpga_0_PCI_Bridge_SERR_N
 PORT IRDY_N = fpga_0_PCI_Bridge_IRDY_N
 PORT FRAME_N = fpga_0_PCI_Bridge_FRAME_N
 PORT DEVSEL_N = fpga_0_PCI_Bridge_DEVSEL_N
 PORT STOP_N = fpga_0_PCI_Bridge_STOP_N
 PORT TRDY_N = fpga_0_PCI_Bridge_TRDY_N
 PORT AD = fpga_0_PCI_Bridge_AD
 PORT CBE = fpga_0_PCI_Bridge_CBE
 PORT PCLK = pci_feedback_s
 PORT RST_N = sys_rst_s
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKFX_BUF = TRUE
 PARAMETER C_CLKFX_DIVIDE = 6
 PARAMETER C_CLKFX_MULTIPLY = 5
 PARAMETER C_CLKIN_PERIOD = 25.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DFS_FREQUENCY_MODE = LOW
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFX = pci_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END


Article: 118367
Subject: Re: Summer with fpgas
From: Eric Smith <eric@brouhaha.com>
Date: 24 Apr 2007 23:35:16 -0700
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> Well, the blank sheet (3) is for the USB interface.
> Not sure why...
> 
> If it is proprietary (now, in this revision), then I suppose someone
> else owns the USB interface design, and they have rights to it we must
> protect.

Someone is Xilinx.  The circuit is nearly identical to the Platform
Cable USB, and Xilinx seems to be mighty proud of that.  Since there's
nothing that magic going on in the hardware (the magic is in the downloaded
firmware and CPLD code), I would guess that you guys are afraid that someone
will clone the cable and cut into your profit.

But as others have observed, keeping part of the schematic of the board
secret does make it difficult to use that USB interface for other things
than Impact and Chipscope.  It would clearly have more value to at
least some of your customers if the page was included.

> If someone really wants to look at a USB to FPGA interface, not only is
> there the previous revision of the board schematic,

No, it's not in there either.

> but thousands of them out there on the web.

The point isn't to get some other design for a USB interface.  Yes,
there are plenty of those.  The point is that those of us who have
purchased the Spartan 3 or Spartan 3E Starter Boards might like to
actually use the USB port on board.

The reality is that if someone really wanted to clone the Platform
Cable USB, keeping the schematics of the Starter Boards secret is
NOT going to be a signifiant impediment.  The secrecy isn't actually
in Xilinx' own interest, but rather is counterproductive.

Eric

Article: 118368
Subject: Image compression on FPGA
From: eric <erixx@gmx.net>
Date: Wed, 25 Apr 2007 09:18:06 +0200
Links: << >>  << T >>  << A >>
Hello,

i'd like to have some informations about image compression on FPGA 
hardware. Do you have some experiences with the Matrox Solios
and in special the version with the Altera FPGA?
I need some informations how much time it could take to implement
compression algorithms on FPGA and how to get an idea how many gates
are needed. Are there other solution than the one from Matrox?

Thanks a lot,Eric

Article: 118369
Subject: Re: Take verilog code from Xilinx Core generator
From: FPGA <espzzh@gmail.com>
Date: 25 Apr 2007 01:00:38 -0700
Links: << >>  << T >>  << A >>
There is no synthesizable verilog code from core generator. It only
generate the netlist, verlog
funtional simulation model and some template to instantiate the core
in your toplevel design. You can
take a look the <corename>_readme.txt for the detail generated files
information.

If you don't use ISE for your design, then take a look the help in
"Design Flow->Verilog Design Flow(Standalone)
from the online help of Core Generator.  There is also help for
"Design flow Within ISE" which tell you how to add
your core in ISE step-by-step.

On Apr 24, 4:06 am, Gordon Freeman <gordonfreeman1...@gmail.com>
wrote:
> On Apr 24, 4:29 pm, FPGA <esp...@gmail.com> wrote:
>
>
>
> > Hi Gordon,
>
> > The core generator only generates the netlist for the IP with Verilog/
> > VHDL wrapper file functional simulation.
> > If you use ISE, then you can generate the core inside the ISE and you
> > can instantiate the core in your design.
> > Just right click on your project and select "New source" and
> > IP(Coregen & Arch Wizard) and you can generate
> > the same core and ISE will add the necessary files automatically.
>
> > William
> > On Apr 24, 12:16 am, Gordon Freeman <gordonfreeman1...@gmail.com>
> > wrote:
>
> > > Hi everyone!
> > > I use Xilinx Core generator to generate DA FIR filter. Right now, I
> > > want to take the verilog code for DA FIR filter but I don't know how
> > > can I do it.
> > > Can you help me?
>
> Thank you for your reply.
> But I can't modify it.
> Can you show me how to take the verilog code for synthesize? I would
> like to know how they process in this code.



Article: 118370
Subject: Virtex-5 FX when ? (II)
From: Udo <WeikEngOff@aol.com>
Date: 25 Apr 2007 01:10:04 -0700
Links: << >>  << T >>  << A >>
Hello Antti, Peter and ...,

yep, some months later now - the same question...
V5-FX?


Thanks and greetings
Udo


Article: 118371
Subject: Re: Image compression on FPGA
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Wed, 25 Apr 2007 10:35:30 +0200
Links: << >>  << T >>  << A >>
>
> i'd like to have some informations about image compression on FPGA 
> hardware. Do you have some experiences with the Matrox Solios
> and in special the version with the Altera FPGA?
> I need some informations how much time it could take to implement
> compression algorithms on FPGA and how to get an idea how many gates
> are needed. Are there other solution than the one from Matrox?
>

Hi Eric,

we have JPEG compression/decompression-IP-cores (no info yet on our 
web-page, sorry...), which are fast and small (but not free). Of course they 
are also usable for MJPEG (which are just JPEG-pics one after another).

To give you an idea about the size:
JPEG-Encoder (YUV4:2:0), Cyclone II:
2350 LEs
4 M4K-blocks
14 9bit-multiplier-elements (=7 18x18-multipliers)

But it is really optimized for size, so I think it will be difficult to 
achieve this size with another solution.

Performance: >120MHz in slowest speedgrade (->80MPixel/s peak compression 
rate)

Regards,

Thomas

www.entner-electronics.com



Article: 118372
Subject: Re: VHDL editing with UltraEdit
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 25 Apr 2007 09:43:44 +0100
Links: << >>  << T >>  << A >>
Nicolas Matringe <nicolas.matringe@fre.fre> writes:

> wallge a écrit :
>> I don't know about ultraedit,
>>
>> but emacs VHDL mode does a wonderful job colorizing and
>> beautifying source code.
>> I use it exclusively... It also has a nice hierarchy browser and
>> lots of other VHDL specific functionality built in.
>>
>> There are some nice cheat sheets available through
>> a google search that have all the important keyboard shortcuts
>> as well...
>
> The problem with emacs is that all its shortcuts are rather alien to
> most Windows users. I have stopped trying to convince my colleagues to
> use it.
>

There is now a "pretty" Windows installer and configurator for Emacs
which makes it much more straightforward for traditional windows users
to have a go.  It sets up lots of the stuff that is unfamiliar to
Windowsers to be more familiar, so CUA keys work, F1 for help etc.
They'll still feel the slashes are all the wrong way around, but I
don't think that'll ever get into Emacs :-)

http://www.ourcomments.org/Emacs/EmacsW32.html

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 118373
Subject: Re: Virtex-5 FX when ? (II)
From: Sean Durkin <news_mar07@durkin.de>
Date: Wed, 25 Apr 2007 10:54:58 +0200
Links: << >>  << T >>  << A >>
Udo wrote:
> Hello Antti, Peter and ...,
> 
> yep, some months later now - the same question...
> V5-FX?
At X-Fest they said "second half of 2007", nothing more specific...

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 118374
Subject: physical chip size
From: Pasacco <pasacco@gmail.com>
Date: 25 Apr 2007 03:22:00 -0700
Links: << >>  << T >>  << A >>
Dear

I am looking at data book of Xilinx Virtex-II Pro

to find ACTUAL CHIP SIZE.

So far, I could not find yet -:

(as an example, 900 um X 1.5 cm)

I need a DIE (that we see in FPGA editor) size for V2P30-ff896 and
V2Pro100-ff1704.

Can anyone help me, where I can find? Should I ask Xilinx?




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