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On some other thread, MikeJ wrote:
>
> I usually try and keep work and the games separate, but it
> would make an excellent platform and save me finishing the
> DDR controller !!
> I have a broadcast serial digital 720P output module somewhere,
> but what I need to make is a DVI output I think ....
>
If you ever spot ( or need help writing/testing )
a FPGA DVI transmitter, let us know!
I've been thinking about trying that for a small S3E
home project; lots of colo{u}rful pixels with only a
few differential output pins and no PHY.
Seems like a simple bias network could shift the
(DC-balanced) encoding scheme from LVDS to TMDS
levels ( or just use an S3A with TMDS drivers )
Max resolution would be limited by the FPGA I/O rates
to say a 60-80 Mhz pixel clock; I think that gets you
into (or near) 1024x768 territory.
IIRC, you can map the DVI-D signals directly onto an
even smaller HDMI connector for a really tiny board
( PS/2, HDMI, VQ100 FPGA )
have fun,
Brian
Article: 120576Hi guys, I have a question regarding how to use linker script to place specific data in the specific memory. Lets make long story short. Assume I have four arrays: a[100], b[100], c[1000], d[1000] in the main.c. I wanna put the first two array a[100], b[100] into local memory, DSOCM, while the others into the external DDR. How can I do this by linker script? Any input would be greatly appreciated! I just found a webpage briefly touches this issue from xilinx answer database. See the solution2, It says"Another method is to keep any variables whose locations you want to control in a separate file (this example will use "special.c")." I just wondered how can I keep those variables in a separate file .c? http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13810 Thanks in advance, YaoArticle: 120577
Un bel giorno Daveb digiṭ: > I am involved in a high reliability application where the device we > want to use (Quicklogic EclipsePlus QL7160) is only available in a > 208pin plastic PQFP (30mm sq) or 280pin plastic BGA (17mm sq). The > environment will subject the device to elevated temperature (~115deg) > and vibration (TBD). Has anyone any experience with using these types > of devices in such an environment & what kind of measures can be taken > to improve mechanical reliability ? I haven't had direct experiences yet, but I know that in some aerospace application BGA isn't looked much well. For example, AFAIK the european space agency explicitly forbids to use them, at least for the scientific experiments (I don't know if different restrictions apply for different applications). -- emboliaschizoide.splinder.comArticle: 120578
Hi there, I'm trying to think hard how design compiler and synplify pro differ with each other from a user's point of view, for example, synthesizing for xilinx virtex fpga. Any inputs would be grateful.Article: 120579
MikeJ wrote: > Add these attributes to the top level : > > attribute MAX_FANOUT : string; > attribute MAX_FANOUT of por_whatever : signal is "10000"; > attribute MAX_FANOUT of por_whatever_else : signal is "10000"; OK, that's the sort of clue I was looking for. Although it would seem that this would prevent the net splitting in the first place, rather than allowing it to happen and restricting the assignment of loads to common sub-nets. > I try not to use a global reset anymore, instead each module takes a > re-clocked synchronous reset and uses that on the control path where > necessary. Don't reset something if you don't need to (data path > usually) as it takes routing resources. Good point. I usually try to follow this rule, but since these flip-flops are address counters for a FIFO, there's no other way to get them into a known state. > p.s. you could use a generate loop on your instantiations to save some > typing. > > flops : for i in 0 to 3 generate > begin > ff_wr_addrp : fdc > port map (d => wr_addrp_d(i), c => lxclk, clr => rst, q => > wr_addrp(i)); > end generate; > > you will have to change your loc constraints of course. Well, the typing is already done :-) Seriously, the file had generate loops to start with, but I couldn't find a way to control the assignment of instance names so that I could use the LOC constraints in a deterministic way. Is there a trick, or a convention as to how the loop index gets added to the name? Thanks for all your help! -- DaveArticle: 120580
> I'm trying to think hard how design compiler and synplify pro differ > with each other from a user's point of view, for example, synthesizing > for xilinx virtex fpga. Any inputs would be grateful. Synplify Pro will give you better results. Cheers, JonArticle: 120581
Hello, i designed such a thing with an FPGA in our entire products. We have a ready design running up to 1920x1200@24 RGB with Analog or DVI-Input and local loopback. Due to the limit of the 2.5 Gbits, we can only support Framerates about 30 FPS@24 Bit colourdepht over the Fibre (when you reduce colourdepth the framerate can be higher). The framerate will then be restored with an Framebuffercontorller on the RX to 60Hz. In further releases we want to feature things like losless compressions to enable higher refresh rates over the fibre. If you are interessted in our product, design support or other things, don't hesitate to contact me via mail. Regards Christian AlbertCo schrieb: > hello > > I need to design DVI over FIBER > my idea to do as follow > > DVI to data then to FPGA > the FPGA will use memory sunc SDRAM or DDRAM > will send info via phy > > and the same on RX side > > I need help with FPGA > please help > > i am on msn or skype avcohen or applicau2 > Albert > 818 2558700 >Article: 120582
On Jun 11, 6:46 am, Jon Beniston <j...@beniston.com> wrote: > > I'm trying to think hard how design compiler and synplify pro differ > > with each other from a user's point of view, for example, synthesizing > > for xilinx virtex fpga. Any inputs would be grateful. > > Synplify Pro will give you better results. > > Cheers, > Jon Last I heard, Synopsys end-of-lifed their FPGA synthesis product. Merciful end to a pitiful product. AndyArticle: 120583
Hello All, I'm learning how to use Xilinx EDK, but am stuck... I figured out how to create a simple Microblaze system which uses the opb_ethernet IP core, but I would like to switch to the hard MAC on the virtex5 fpga. EDK does not have a wrapper for this in it's IP core list, so I used the Xilinx Core Generator to generate it. The problem I am having is importing the core into EDK. This is what I have tried so far: 1. Import the core using the EDK wizard, Selecting DCR slave bus as my connection [ I can only find two .vhd source files to import] 2. Add the core to my design. 3. Add an opb_dcr bridge Am I on the right track? Any hints? Thanks -JorgeArticle: 120584
On Jun 10, 8:22 pm, "lyra" <ss_c...@csmsc.com> wrote:
> > I face a program error and can not solve it. Pls you help me if you know
> > how.
> > { chip:Stratix 2--EP2S15F484I4
> > Hardware Setup: ByteBlaster[LPT1] Mode:Active Serial Programming
> > error information:current programming hardware does not support Active
> > Serial Programming programming mode}
Sure. Use Passive Serial mode or Jtag, depending on what signals you
have hooked up. Active Serial is only for use when the FPGA loads
from certain configuration memories, not when it's loaded with a
programmer cable (the idea is that you want the computer, not the
FPGA, to be clocking the data transfer)
Article: 120585-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Alex Gibson wrote: > I am after a pcie card where the ip doesn't cost an arm and a leg > unlike that for xilinx's s3 pcie starter kit > > Got quoted > $15,000 for the pcie core(End point pipe) by the local > distributor > who was trying to push us towards > Virtex-5 ML555 PCI Express Board HW-V5-ML555-G > which is overkill for what we need. > > Looking for a card that has drivers and examples for windows and linux > and includes the ipcores needed(board license is fine) > > Basically uni research project to prove a design concept (one off) > 1x is fine. > > Doesn't have to be xilinx based even though that would be easier as we have > all the software.. PLDA has a wide variety of PCIe test boards, and if you buy one they come with a board license for their 'lite' core. If you don't need full access to all PCIe features, these should work for you, and are available in a variety of flavors, with both Xilinx and Altera part options. I've personally used several of the Altera based boards, and they ranged from $1000 to $5000 each, well under the $15K you were quoted, but you don't get a license for using the core on anything other than their eval board. > Has any here used the Lattice pcie cards and cores ? Not here...just the Altera SGX parts for PCIe. My previous history with the AT&T/Lucent/Lattice parts is well remembered, however...these are still my favorite FPGA family, and I've done extensive work with everything from Xilinx 2000 series parts in the 80's to the million gate parts out now. - -- Charles Steinkuehler cstein@newtek.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.4 (MingW32) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFGbWZVenk4xp+mH40RAoWJAJ9VzfJ/HJwQAzMUsSgBdff8+3sR+gCg3efG /s80J8s1rlJ0BmXEpGn3MUw= =Os/y -----END PGP SIGNATURE-----Article: 120586
Hi, I have a program which needs to allocate high memory with calloc, but I want to load the app on the BRAM, so I wish to configure linker script so heap resides on the SDRAM. Is it possible?. Does anyone try to do this?Article: 120587
I'm doing a PCB design for a client which incorporates a Cyclone II. I have only used two of the 8 dedicated clock pins so had left the rest floating. During a schematic review one of the client's engineers said that he thought it might be a good idea to tie the unused clock pins to GND. I have never done this before, I was under the impression that these were weakly held high or low but can't find any reference to this in the documentation. If these aren't pulled weakly I'd definitely add the extra few components, but don't want to add extra stuff to be placed/routed/built if it's not necessary. What's the panel's view? Nial.Article: 120588
I am programing a 8-channel digitizing board based on xc3s400 and I
ran into the following situation:
Here are peaces of code that I think might make it easier to
understand:
COMPONENT ADC_Channel
Port ( CLK : in STD_LOGIC;
FX_CLK : in STD_LOGIC;
S1WE : in STD_LOGIC;
S2WE : in STD_LOGIC;
S1Found : out STD_LOGIC;
S2Found : out STD_LOGIC;
ADC_Raw : in STD_LOGIC_VECTOR (14 downto 0);
CurSample : out STD_LOGIC_VECTOR (15 downto 0);
FX_IOBUS : inout STD_LOGIC_VECTOR (7 downto 0);
FX_ADDR : in STD_LOGIC_VECTOR (15 downto 0);
FX_MemSelect: in STD_LOGIC);
END COMPONENT;
signal S1Found,S2Found: STD_LOGIC_VECTOR(7 downto 0):="00000000";
signal S1FoundB: STD_LOGIC:='0';
Channel1: ADC_Channel
Port Map( CLK => NOT CLKIN,
FX_CLK => FX_CLKIN,
S1WE => S1WEC1,
S2WE => '0',
S1Found => S1Found(0),
S2Found => S2Found(0),
ADC_Raw => ADC_A,
CurSample => CurSampleC1,
FX_IOBUS => FX_IOBUS,
FX_ADDR => FX_ADDR,
FX_MemSelect => FX_MemSelect(0)
);
.
. .... and so on until Channel 8
.
Channel8: ADC_Channel
Port Map( CLK => CLKIN,
FX_CLK => FX_CLKIN,
S1WE => S1WEC1,
S2WE => '0',
S1Found => S1Found(7),
S2Found => S2Found(7),
ADC_Raw => ADC_D,
CurSample => CurSampleC8,
FX_IOBUS => FX_IOBUS,
FX_ADDR => FX_ADDR,
FX_MemSelect => FX_MemSelect(7)
);
What is important here is that each channel asserts S1Found or S2Found
single bits whenever a specific signal is found.
What I want is to stop acquisition on all channels once a signal S1 is
found on any of the channels. So I want to create a "global" S1Found.
So firstly I placed a single bit check just to see if anything works:
PROCESS(CLKIN)
begin
if CLKIN = '0' and CLKIN'Event then
if (S1Found(0)='1') then
S1FoundB <= '1';
else
S1FoundB <= '0';
end if;
end if;
end process;
with the above code the "Synthesize" part of the compilation yields
the following results:
Found area constraint ratio of 100 (+ 5) on block Top_level, actual
ratio is 64.
Logic Utilization Used Available Utilization
Number of Slices 2308 3584 64%
Number of Slice Flip Flops 1558 7168 21%
Number of 4 input LUTs 3975 7168 55%
but once I want to check the state of any of the eight bits with the
following code:
PROCESS(CLKIN)
begin
if CLKIN = '0' and CLKIN'Event then
if (S1Found /= "00000000") then
S1FoundB <= '1';
else
S1FoundB <= '0';
end if;
end if;
end process;
the "Synthesize compilation yields:
Found area constraint ratio of 100 (+ 5) on block Top_level, actual
ratio is 97.
Logic Utilization Used Available Utilization
Number of Slices 3497 3584 97%
Number of Slice Flip Flops 2692 7168 37%
Number of 4 input LUTs 5329 7168 74%
and I don't understand that because I was expecting an increase in
Slices by 1, no change in Slice F-F, and increase of 4 input LUTs by
2.
This is especially surprising on the Synthesize level, before Placing
and Routing.
I tried:
- setting Optimization Goal to Area - very minor improvement (still in
the 96-97% of utilization)
- setting Optimization Effort to High - still in the 96-97% of
utilization
- separating/isolating the S1Found (8bit) signal from the "channels"
by a FF.
I would be very thankful for any input that might solve this problem.
Thank you for your time and assistance,
With regards,
Eryk Druszkiewicz
Article: 120589On Mon, 11 Jun 2007 16:01:24 -0000, eryksson@gmail.com wrote: >I am programing a 8-channel digitizing board based on xc3s400 and I >ran into the following situation: > >Here are peaces of code that I think might make it easier to >understand: > >COMPONENT ADC_Channel > Port ( CLK : in STD_LOGIC; > FX_CLK : in STD_LOGIC; > S1WE : in STD_LOGIC; > S2WE : in STD_LOGIC; > S1Found : out STD_LOGIC; > S2Found : out STD_LOGIC; > ADC_Raw : in STD_LOGIC_VECTOR (14 downto 0); > CurSample : out STD_LOGIC_VECTOR (15 downto 0); > FX_IOBUS : inout STD_LOGIC_VECTOR (7 downto 0); > FX_ADDR : in STD_LOGIC_VECTOR (15 downto 0); > FX_MemSelect: in STD_LOGIC); >END COMPONENT; Is it possible that the logic which generates SxFound in the ADC_Channel is being trimmed when it's not being used and when you actually use it, it's using too many resources?Article: 120590
Hi folks, I have not tested your recommended procedure yet. I have reinstaled the ModelSim to the older, recommended revision 6.1e and it works. I followed "Introduction" section in "EDK Concepts, Tools, and Techniques" Xilinx article. It well describes what shoud be done step-by-step. It works, and I am happy ;) Have a nice day JanArticle: 120591
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:5d59eaF32s4reU1@mid.individual.net... > I'm doing a PCB design for a client which incorporates a Cyclone II. > > I have only used two of the 8 dedicated clock pins so had left the > rest floating. > > During a schematic review one of the client's engineers said that he > thought it might be a good idea to tie the unused clock pins to GND. > > I have never done this before, I was under the impression that these > were weakly held high or low but can't find any reference to this in the > documentation. > > If these aren't pulled weakly I'd definitely add the extra few components, > but don't want to add extra stuff to be placed/routed/built if it's > not necessary. > > > What's the panel's view? > > > > > Nial. I'd love to reference the specific App note or data page but this information comes second hand. The same issue came up here a couple days ago where an engineer was told to connect the unused Altera clock inputs to ground. There was a short initial debate among a few of us before another engineer (who had a recent Cyclone-II design) interjected that Altera explicitly calls out that the unused clock pins should be grounded. Since it's near and dear to the Altera designers (it's been too many years since I've used "Brand A") you might get a quick document reference from your FAE or someone at the Altera Application Hotline. - John_HArticle: 120592
Just to add some information about Synplify DSP, which provides very similar functionality to System Generator but allows you to target devices from several different vendors, which would be useful to you if you want to compare devices from different vendors before taking the plunge on their products... Cheers, JonathanArticle: 120593
On Jun 11, 12:46 pm, Jon Beniston <j...@beniston.com> wrote: > > I'm trying to think hard how design compiler and synplify pro differ > > with each other from a user's point of view, for example, synthesizing > > for xilinx virtex fpga. Any inputs would be grateful. > > Synplify Pro will give you better results. > > Cheers, > Jon any review articles comparing those two products? pointers to those articles would be greatly appreciated.Article: 120594
Ugggggghhhhhhhhhhhhhhhhhhhhhhh!!!!!! I HATE UPGRADING XILINX TOOLS!!! Seems like every time we do, there are days of pain involved. I have a sim that used to work in 8.2 that now does not work in 9.1. I have traced the problem to the fact that the BRAM for Microblaze instructions never initialize to anything. I have checked the system_init.v file and there is certainly non-zero data there. I have the system_conf module instantiated in my testfixture so there should be no problem there. The only warning that ModelSim SE 6.2f gives is" ** Warning: Parameter expressions did not converge. Possible loop involving defparams." But it doesn't tell anything about what parameter expressions are causing this or where they are. The sim continues on fine. But internally, all I get is a program counter that increments to infinity. There is nothing coming over the LMB. Is there something that I am missing? I run the system.do file in ModelSim. Then I invoke the simulator with: vsim -L unisims_ver -L XilinxCoreLib_ver -voptargs="+acc" system_tb glbl. This is really driving me nutz! It is probably going to be some thing stupid!!!!Article: 120595
I looked into this, then realised you can buy a small chip which not only
had a decent DAC to give you RGB analogue outputs, it also drives DVI.
There is one on the cheaper V5 eval board from Xilinx. As I need a DAC
anyhow it seems the way forward ...
/Mike
"Brian Davis" <brimdavis@aol.com> wrote in message
news:1181534433.879042.306260@q69g2000hsb.googlegroups.com...
> On some other thread, MikeJ wrote:
>>
>> I usually try and keep work and the games separate, but it
>> would make an excellent platform and save me finishing the
>> DDR controller !!
>> I have a broadcast serial digital 720P output module somewhere,
>> but what I need to make is a DVI output I think ....
>>
> If you ever spot ( or need help writing/testing )
> a FPGA DVI transmitter, let us know!
>
> I've been thinking about trying that for a small S3E
> home project; lots of colo{u}rful pixels with only a
> few differential output pins and no PHY.
>
> Seems like a simple bias network could shift the
> (DC-balanced) encoding scheme from LVDS to TMDS
> levels ( or just use an S3A with TMDS drivers )
>
> Max resolution would be limited by the FPGA I/O rates
> to say a 60-80 Mhz pixel clock; I think that gets you
> into (or near) 1024x768 territory.
>
> IIRC, you can map the DVI-D signals directly onto an
> even smaller HDMI connector for a really tiny board
> ( PS/2, HDMI, VQ100 FPGA )
>
> have fun,
> Brian
>
Article: 120596> > Seriously, the file had generate loops to start with, but I couldn't > find a way to control the assignment of instance names so that I could > use the LOC constraints in a deterministic way. Is there a trick, or > a convention as to how the loop index gets added to the name? > Earlier XST versions were a bit broken in this regard, but 9.1 is more consistent. Have a read of the XST users guide it explains it. I usually leave the LOCs off to start with, build it and then find them in floorplanner to work out the path. Floorplanner can write out a UCF file, so place one flop, write out to a temp.ucf file then steal the necessary line. /MikeArticle: 120597
> My recall of QDR is a little fuzzy- do your address > outputs also use the FPGA DDR output registers, or is > only the clock/data done on both edges with a DDR flop? Address change at SDR rate but I am still using DDR output flops. > > Is this all done with global clocks, or are you using > regional/local clocks? Global clocks in V4. > > If this were V2, I'd ask if you were using internal DDR > clock inversion for the DDR 180 degree clock phase, or using > two BUFGs to distribute clock and NOT clock. thankfully we don't have to do that anymore :) > >> >> > - Do you have any spare LVDS input/outputs elsewhere >> > on the chip ? ( handy for clock troubleshooting ) >> >> I have an unused bank with 2V5 IO actually so I could possibly get some >> clocks in and out here. >> > I like to have some LVDS I/O available for these sorts of > measurements; I've been thinking about plunking a vertical > launch SATA connector down on my boards to provide an easy > clock test I/O connector ( less space then 4 SMAs, easier > to probe/drive than resistor pads ) neat idea that! /MikeArticle: 120598
Mark McDougall <markm@vl.com.au> writes: > Hmmm, I'm sure I've seen _some_ disk controller datasheet that mentions an > internal processor... wonder where that was... ? The NEC uPD7261 Winchester disk controller contained an 8048-based processor core, IIRC. The Motorola MC68HC98 and MC68HC99, intended as embedded SCSI controllers for disk drives, contained the 68HC11 core. There were probably other HDC controller chips that contained a general-purpose processor core, but I'm not aware of any FDC chips that did. It's not a disk controller, but the National Semiconductor NS455 TMP (terminal management processor) contained an 8048 core. EricArticle: 120599
Brian Davis <brimdavis@aol.com> writes: > Seems like a simple bias network could shift the > (DC-balanced) encoding scheme from LVDS to TMDS > levels ( or just use an S3A with TMDS drivers ) Can you get TMDS drivers that aren't part of a DVI transmitter chip (which also does the encoding)? It doesn't appear that DVI transmitter chips cost much, so is it really worthwhile to try to avoid using one?
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Compare FPGA features and resources
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