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On Oct 3, 12:10 am, Jarek Rozanski <jarek.rozan...@gmail.com> wrote: > On 2 Pa , 18:54, Mike Treseler <mike_trese...@comcast.net> wrote: > > > Tom Lucas wrote: > > > Does anybody have any suggestions for a cheap and basic development kit > > > to practice VHDL on? It doesn't need to do much more than toggle a few > > > output pins and I'm happy to make up my own programming leads etc. UK > > > based distributors would be preferred. > > > If the objective is to learn vhdl, all you need is > > > 1. A simulator to verify and debug > > the uut and testbench code and > > Good solution is a Aldec Active-HDL 7.2 SE (student edition). Very > good simulation and verification tool. Nice schematic diagrams, easy > waveform manipulation. Very good choice (personal opinion) for > learning. Moreover, for this purposes it is free :) I'll second this recommendation. I've found Active HDL's free student edition more than enough for educational purposes. EliArticle: 124901
Hella all:) I would like to ask for the complier option in the XILINX EDK. I have written ans inline assembly code. and simulation in Modelshim. When i am compling the code i said "No Optimization". But in the debug symbols what is the deffierence between symbols for debugging (-g)and symbols for assembly(-gstabs). ? And for inline assembly what is the best settings? regards xenix From removethisthenleavejea@replacewithcompanyname.co.uk Wed Oct 10 05:31:38 2007 Path: newssvr11.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!newsfeed-0.progon.net!progon.net!newsfeed.freenet.de!feed.xsnews.nl!border-2.ams.xsnews.nl!feeder.news-service.com!feeder.news-service.com!eweka.nl!hq-usenetpeers.eweka.nl!195.245.201.2.MISMATCH!news.clara.net!wagner.news.clara.net!proxy00.news.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1191912804.745576.296080@o80g2000hse.googlegroups.com> <feg4tk$q8g1@cnn.xilinx.com> <1191943165.072232.169820@v3g2000hsg.googlegroups.com> <fegdg0$q961@cnn.xilinx.com> <1192006925.353130.28330@k79g2000hse.googlegroups.com> Subject: Re: Need suggestion on FPGA kit Date: Wed, 10 Oct 2007 13:31:38 +0100 Lines: 49 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: b20af041e96502a16e7440c06774660b577060b0e1e112485a608e22470cc68c NNTP-Posting-Date: Wed, 10 Oct 2007 13:33:16 +0100 Message-Id: <1192019596.23630.0@proxy00.news.clara.net> Xref: prodigy.net comp.arch.fpga:136917 It depends on what physical format you want. we get a lot of interest on our Hollybush1, Darnaw1 and Craignel1/2/3/4 in the embedded world because of their form factors. We will be adding Hollybush2 and the CR1 to that list before too long as well and they will have new and different things over what we already offer in boards for the embedded market. For details of these go http://www.enterpoint.co.uk/boardproducts.html. John Adair Enterpoint Ltd. "yeah" <thiyagu.in@gmail.com> wrote in message news:1192006925.353130.28330@k79g2000hse.googlegroups.com... > On Oct 9, 10:24 pm, austin <aus...@xilinx.com> wrote: >> 15 family members is what I count from the data sheet.... >> >> There is no such thing as SX (no transceivers). >> >> Sorry about that, SX always is SXT. >> >> http://direct.xilinx.com/bvdocs/publications/ds100.pdf >> >> page 2, Table 1. >> >> Austin >> >> Antti wrote: >> > On 9 Okt., 16:57, austin <aus...@xilinx.com> wrote: >> >> Well, >> >> >> All Virtex 5 family members: LX, LXT, SX, SXT are all now in full >> >> production. >> >> > ALL 5 ? >> > I count 4 ? >> >> > Antti > > thanks friends > > Our intention is to use the kit for embedded applications. > The choice is "Virtex-5 LXT ML505 Evaluation Platform (HW-V5-ML505- > UNI-G)". > Is there any other FPGA kit which has better configuration(and > feautures) in Altera than Virtex-5 specially for embedded > applications. > > From removethisthenleavejea@replacewithcompanyname.co.uk Wed Oct 10 05:33:06 2007 Path: newssvr11.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.astraweb.com!border1.newsrouter.astraweb.com!news.glorb.com!feeder.news-service.com!eweka.nl!hq-usenetpeers.eweka.nl!195.245.201.2.MISMATCH!news.clara.net!wagner.news.clara.net!proxy00.news.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1192004800.613653.202520@y42g2000hsy.googlegroups.com> Subject: Re: UK Supplier XILINX spartan 3 development board?? Date: Wed, 10 Oct 2007 13:33:06 +0100 Lines: 21 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: b20af041e96502a16e7440c06774660b577060b0e1e112485a608e22470cc68c NNTP-Posting-Date: Wed, 10 Oct 2007 13:33:16 +0100 Message-Id: <1192019596.23630.1@proxy00.news.clara.net> Xref: prodigy.net comp.arch.fpga:136918 Dan We are UK based but have only a limited USB support on currently released products. Details of what we have here http://www.enterpoint.co.uk/boardproducts.html. John Adair Enterpoint Ltd. <dan.walmsley@gmail.com> wrote in message news:1192004800.613653.202520@y42g2000hsy.googlegroups.com... >I need to find a cheap UK supplier for a spartan 3 development kit, > prepherably USB, it needs to be suitable to implement a small softcore > processor and ideal for someone with no previous experience. > > I can find lots of products in the US but none in the UK. > > Dan Walmsley >Article: 124902
Pierrick wrote: > On Oct 9, 12:53 pm, Guenter Dannoritzer <kratfkryk...@spammotel.com> > wrote: >> Pierrick wrote: >>> 4DSP offers a floating point FFT and it seems like the only one >>> available today with true IEEE-754 (float) arithmetic for FPGA >>> devices. >> That is a bold statement and I would be interested which other available >> cores you compared yours to and ruled out that they do not support true >> IEEE-754 arithmetic? >> >> Cheers, >> >> Guenter > > Fair enough! The message however is related to the original thread > where the user is looking for a 1M points FFT. It looks indeed as if > there are some alternatives for shorter lengths FFTs (<32k points). I see your point, but don't agree with that statement. When I do a google search for floating point FFT, the first five hits show information about floating point FFT cores from: - 4DSP - Dillon Engineering - Andraka Consulting - Sundance Multiprocessor Technology Ltd - Altera From all the above only on the web page of Andraka Consulting it says that their core is limited to 2048 points. The other hits either explicit say their core supports lengths up to 1M or do not state any length limitations. And they all state that they are IEEE-754 compliant.Article: 124903
Andrew FPGA wrote: > Hi all, > Just read an interesting article in Xilinx's xcel publication. Lots of > technical detail, and no "marketing" to speak of. > http://www.xilinx.com/publications/magazines/dsp_03/xc_pdf/p42-44-3dsp-andraka.pdf > > After reading this I had a couple of burning questions I'm wondering > if anyone, or Ray himself, can shed some light on > 1) 1.2 Gsamples/s seems like a pretty high input data rate - no doubt > there are a few applications around that need it. But what about the > 1.2Gsamples/sec data output rate? What systems can take the FFT > outputs at this rate, and do something sensible with the data? Actually, I would say there are far more fixed-point FFT cores used than this floating-point one, because the fixed-point cores can achieve even faster throughput. If you look at the Andraka Consultant web page you will see explanations about where it is used in. In general a FFT core is not a stand alone block, but usually used in connection with other functionality. So the core is embedded in an application and from the outside you don't see that data rate anymore. > Although the FFT engine has done a bunch of processing, it hasn't > really reduced the amount of data in any way? I mean you can't go > hookup 1.2Gsps to a pc based platform. Even 10 gigabit ethernet cannot > transport this amount of data, let alone the cpu do much processing > with it. Well, actually in many cases the FFT will actually increase the data amount. If you come from real world applications, usually you have real data and can set the imaginary part to 0. Then the output of the FFT is complex. Also, if you want to use that core in connection with a PC, you probably will not hook it up over a Ethernet connection, but use it with an FPGA on a PCI or PCI-E plug in card. Cheers, GuenterArticle: 124904
A good question, This board is presently not available with a Virtex 5 FX part (which has the IBM PowerPC(tm). That will be available soon, as the Virtex 5 FX family has not yet been announced for general ES shipments. Until then, the LX and SX devices may be placed on this board, and you may use the MicroBlaze soft processor. So, the question is: how powerful a processor is required? As Altera offers no hard embedded processor, and their NIOS2 is similar in performance to our MicroBlaze, the IBM PowerPC represents quite a step up in capability. For example, full LINUX may be run by the PowerPC, but only LINUX-Lite may run on the soft processors. The reason for this is more advanced processors have the memory management which is required by LINUX for all of its features. If you do not plan on running an operating system, or your operating system is very simple, then either soft processor solution is probably adequate. If Altera had a competitive offering to the ML505 board, I am sure that they would have posted here by now. All V5 devices have a PCIe core, and combined with the transcievers, a 1, 2, or 4 lane PCIe interface is provided by this development pcb (I think, but I would have to check to be sure -- the chip has the capability, I just would have to see if the 505 is the right pcb, as I haven't memorized all the numbers and features of the support platforms). AustinArticle: 124905
On Tue, 09 Oct 2007 12:19:08 -0000, dan.walmsley@gmail.com wrote: >i have downloaded the xilinx webpack and gone through a few tutorials >on the software can anyone recommend a good starter board, that would >cope with trying a small softcore microcontroller. > >If anyone has any good tutorials or educational material on FPGAs >please could you email me. > >Any advice would be greatly appreciated. > >Dan Walmsley In addition to the Digilent boards, take a look at Enterpoint's products, e.g. http://www.enterpoint.co.uk/moelbryn/raggedstone1.html - BrianArticle: 124906
On Tue, 9 Oct 2007 18:04:12 +0200, pgw <"SwietyMikolaj["@]poczta.onet.pl> wrote: >Hi > >I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM. >And I'm wondering how to distribute clock signal. >DIMM has 6 clock signals (3 differential pairs). >I figure out two solution: > >1. Use differential output PLL_OUT and split signals to three DIMM input. > >2. Use 6 general purpose FPGA IO to distribute three pairs of clock and >shifted clock. (This IO pins will be single-ended not differential) > >Which soulution is better and will have lower skew to other DDR signals? >Or maybe do that on different way? In Xilinx devices it's quite common to use the DDR output registers in IOBs, to register the DDR clock in the IOB itself, and reduce skew that way. I would expect you can do the same in Cyclone but don't know for sure. - BrianArticle: 124907
On Oct 9, 4:41 pm, motty <mottobla...@yahoo.com> wrote: > I am working with an EDK design that utilizes an MPMC2 core. There > are several clocks associated with this core. All of the clocks are > created using DCM's and inverters. I am failing timing b/c cross- > clock domain paths are being analyzed and are failing. > > My first question is: Should these paths be analyzed for this core? > I didn't see any info in the documentation. I know the calibration > routine/architecture is supposed to take care of finding the sweet > spot to sample data so a TIG should apply for that logic. But I am > not certain if every cross-domain path in the core is a TIG. > > Second question: If all the paths are indeed TIG's, then is there an > easy way to make the constraints? The only timing constraint > currently implemented is the input clock to the FPGA that is fed to > the DCM chain. Then all other clocks constraints are automatically > determined by the tools. Is there a similar feature where I can tell > the tools to apply TIG constraints to certain DCM-derived clock paths? > > Thanks! You could TIG the outputs by using: NET dcm_clock_output_name TIG; But then you'd have NO timing constraints for that clock at all. Not what you're looking for. One way of handling the cross-domain clocking is to specify a timing constraint for the cross-clock-domain. Here's an example of this: NET clk_100MHz TNM = ffs_100; NET clk_200MHz TNM = ffs_200; TIMESPEC TS_100_to_200 = FROM ffs_100 TO ffs_200 10 ns; This is an example from a MPMC2 design I was working on. It states that where the 100MHz clock meets the 200MHz clock, only worry about meeting 100MHz timing. This design had a MPMC2 core running at 200MHz for DDR2 memory, but the rest of the logic was running at 100MHz. This includes the PPC405s, the ports on the MPMC2, and all of the other logic inside. One item to note is that this will probably not work if you have CDMAC on the MPMC2. From reading through Xilinx's website, it was stated that the CDMAC in v1.8 did not have enough buffering to handle cross- clock domain timing in its logic. Therefore the MPMC2 core could not running faster than 150MHz. I did get a build together with a 100MHz CDMAC and a 200MHz MPMC2, but did not perform any testing on it. -- MikeArticle: 124908
There is a difference between what is available today for 1M points (COTS that can be shipped today) and what can be designed and be available in 6 months time. Dillon, as a consulting company you claim you can do it. Maybe you have it as a product but there are no figures showing number of slices, transform time, etc... So it is questionable. Since there is no limitation in the length of your FFT length, can you supply a 512M points FFT today? 4DSP, as a product company we have the 1M points COTS and it can ship it today. However, I can confirm we do not have a 512M points FFT today. But we can do it if given enough time:)Article: 124909
On Oct 10, 4:38 am, xenix <last...@gmail.com> wrote: > Hella all:) > > I would like to ask for the complier option in the XILINX EDK. I have > written ans inline assembly code. and simulation in Modelshim. When i > am compling the code i said "No Optimization". > > But in the debug symbols what is the deffierence between symbols for > debugging (-g)and symbols for assembly(-gstabs). ? And for inline > assembly what is the best settings? > > regards > xenix The EDK compiler is a GCC derivative. Any documentation on GCC should apply (except for the code generation). G.Article: 124910
It seems that the launchbird site has disappeared. I had heard that Confluence was superceded by HDCaml, but it looks like that site is dead as well. I'm currently learning OCaml and would like to play with HDCaml - anyone know if the source code is still available?Article: 124911
Hello Could someone tell me how to make timing constraints in a particular part of a VHDL design? Inside my design I have an enity that makes a calculation. That entity I can clock at about 50 MHz (the syntesis report says that), so I select 40MHz (divided from 80MHz). The rest of my design I want to clock at 80MHz. How do I make timing constraints for my calculation entity?Article: 124912
Hi, I'm trying to build a board that will use a DDRAM PC2700 memory module connected to a Cyclone II FPGA. It uses SSTL-2 signaling, and one thing I really don't understand is why the on-chip series resistor for SSTL-2 seems to be 50 ohms (according to http://www.altera.com/products/devices/cyclone2/features/onchip/cy2-onchip.html) while it should be 25 ohms (according to http://www.interfacebus.com/SSTL_Logic_Interface.html - I've also measured the series resistors of my memory module and they are about 25 ohms). I think I'm going to use SSTL-2 Class I for simplicity (btw I wonder why Class II exists ? it just uses more components and sucks more power). Any suggestion ? Thanks, SebastienArticle: 124913
On Oct 10, 12:40 pm, "DoVHDL" <DoV...@DoVHDL.DoVHDL> wrote: > Hello > > Could someone tell me how to make timing constraints in a particular part of > a VHDL design? > > Inside my design I have an enity that makes a calculation. That entity I can > clock at about 50 MHz (the syntesis report says that), so I select 40MHz > (divided from 80MHz). The rest of my design I want to clock at 80MHz. How do > I make timing constraints for my calculation entity? Timing constraints vary by tool, what are you using? If you are using Xilinx/ISE and you are using a DCM to divide your 80 MHz clock down to 40 MHz, timing constraints you put on the 80 MHz clock will be propagated through the DCM and adjusted accordingly. Regards, John McCaskill www.fastertechnology.comArticle: 124914
On Oct 10, 3:03 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 09 Oct 2007 12:19:08 -0000, dan.walms...@gmail.com wrote: > >i have downloaded the xilinx webpack and gone through a few tutorials > >on the software can anyone recommend a good starter board, that would > >cope with trying a small softcore microcontroller. > > >If anyone has any good tutorials or educational material on FPGAs > >please could you email me. > > >Any advice would be greatly appreciated. > > >Dan Walmsley > > In addition to the Digilent boards, take a look at Enterpoint's > products, e.g. > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - Brian You can read my blog: http://www.fpgafromscratch.com SvenArticle: 124915
"John McCaskill" <jhmccaskill@gmail.com> wrote news:1192041075.893467.288100@d55g2000hsg.googlegroups.com... > On Oct 10, 12:40 pm, "DoVHDL" <DoV...@DoVHDL.DoVHDL> wrote: >> Hello >> >> Could someone tell me how to make timing constraints in a particular part >> of >> a VHDL design? >> >> Inside my design I have an enity that makes a calculation. That entity I >> can >> clock at about 50 MHz (the syntesis report says that), so I select 40MHz >> (divided from 80MHz). The rest of my design I want to clock at 80MHz. How >> do >> I make timing constraints for my calculation entity? > > Timing constraints vary by tool, what are you using? > > If you are using Xilinx/ISE and you are using a DCM to divide your 80 > MHz clock down to 40 MHz, timing constraints you put on the 80 MHz > clock will be propagated through the DCM and adjusted accordingly. > > Regards, > > John McCaskill > www.fastertechnology.com > I'm using Xilinx ISE WebPack for my design. I have 4 ADC interface entities that operaates on a 80MHz clk that I'm creating from an external 20MHz clock with a DCM. The calculation part (having a MAC-operation) must run on a 40MHz clock (divided from the 80MHz clock).Article: 124916
Andrew FPGA wrote: > Hi all, > Just read an interesting article in Xilinx's xcel publication. Lots of > technical detail, and no "marketing" to speak of. > http://www.xilinx.com/publications/magazines/dsp_03/xc_pdf/p42-44-3dsp-andraka.pdf > > After reading this I had a couple of burning questions I'm wondering > if anyone, or Ray himself, can shed some light on > 1) 1.2 Gsamples/s seems like a pretty high input data rate - no doubt > there are a few applications around that need it. But what about the > 1.2Gsamples/sec data output rate? What systems can take the FFT > outputs at this rate, and do something sensible with the data? > Although the FFT engine has done a bunch of processing, it hasn't > really reduced the amount of data in any way? I mean you can't go > hookup 1.2Gsps to a pc based platform. Even 10 gigabit ethernet cannot > transport this amount of data, let alone the cpu do much processing > with it. > > 2)I didn't understand the comparison between the 66 Gflop fpga FFT > core and the 48 GFLOP Cell processor implementation. Was the cell > processor implementation processing samples at 1.2Gsps? was it also at > from 32 to 2048 point transform? > > Cheers > Andrew > That particular application was for image processing, the FFT was used in two passes to perform a 2D FFT of various sizes. Fast FFTs are also commonly used in communications, digital radio and SIGINT applications, all of which need to do the FFT on incoming data streams sampled at high rates. The 1.2 GS is the upper bound for this architecture in this device. The application in question needed a sustained 1.0 Gs/sec to keep up with the frame data. The FFT is surrounded with other hardware, not connected (at least on the data path) to a computer. The cell processor was not working at 1.2Gsps, in fact it would not be able to achieve that data rate. The comparison was to show that the FPGA design could substantially out-perform the cell processor. The cell application was actually a large FFT, 512K points as I recall. The large FFT is essentially the same process as a 2D FFT except that there is a phase rotation between passes for the large FFT that is not there for the 2D FFT. While the comparison is not exactly 1:1, it is similar enough to be able to draw a valid conclusion. I have used the same floating point core to perform large FFTs instead of 2D.Article: 124917
I mean I would like to make a local time constraint for an entity (if that makes things more clear). :-)Article: 124918
Guenter Dannoritzer wrote: > > Actually, I would say there are far more fixed-point FFT cores used than > this floating-point one, because the fixed-point cores can achieve even > faster throughput. > In this case, the fixed point version has about the same speed as the floating point, but with considerably less latency. A single instance of the core runs at up to 400 MHz in a -10 V4SX55 for both the floating point and fixed point versions. That speed is limited by the max clock of the DSP48 and BRAM elements. The fixed point core is smaller, which means more instances can be fit into a device for a higher overall throughput.Article: 124919
Sebastien, The class II is bidirectional. Class I is unidirectional. I have no comment on the Altera part, the series component is not supposed to be 50, but as you note, 25 ohms. I suspect it is a typographic error, you should report it to them. AustinArticle: 124920
DoVHDL wrote: > I'm using Xilinx ISE WebPack for my design. I have 4 ADC interface entities > that operaates on a 80MHz clk that I'm creating from an external 20MHz clock > with a DCM. The calculation part (having a MAC-operation) must run on a > 40MHz clock (divided from the 80MHz clock). Are you going to have a separate clock domain clocked at 40MHz? Then you put a 25nS period constraint on the entire domain, not an entity. The same kind of constraint as on your 80MHz clock. But how are you handling getting data across the domain boundaries? That can be tricky. Or are you going to clock everything at 80MHz, but have an enable in your "calculation part" that toggles, effectively operating it at 40MHz? This would be a better idea. You would apply a multicycle constraint, but that also can be a tricky thing to get right. But the best thing to do would be to figure out why your MAC cannot operate at 80MHz, and fix it. How you do that depends somewhat on what device you are using. Are you using a device with builtin hardware multipliers? Then the first step would be to look in the project.syr file, and look for the word "pipeline". Look down through that section and see if there is something like: INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult__mult0004 by adding 1 register level(s). If so, you probably just need to pipeline your multipliers more. Make sure to go through the file and find all instances of the word "pipeline".Article: 124921
On Oct 10, 3:26 am, dan.walms...@gmail.com wrote: > I need to find a cheap UK supplier for a spartan 3 development kit, > prepherably USB, it needs to be suitable to implement a small softcore > processor and ideal for someone with no previous experience. > > I can find lots of products in the US but none in the UK. > > Dan Walmsley Trenz Electronics carries FPGA boards. They are in Germany, and while that's not the UK, it's not the US either. http://www.trenz-electronic.de/home/indexen.htm (the web site is in english) -Dave PollumArticle: 124922
rubyfan@gmail.com schrieb: > It seems that the launchbird site has disappeared. I had heard that > Confluence was superceded by HDCaml, but it looks like that site is > dead as well. I'm currently learning OCaml and would like to play > with HDCaml - anyone know if the source code is still available? > Confluence is to be replaced by Atom, a Haskell-based HDL. PhilippArticle: 124923
Evan Lavelle wrote:
> The syntax is valid; (this) assign is a procedural statement which can
> only be used on variables (and the test code works on two other sims).
> The procedural assign isn't particularly useful; I only mentioned it
> because it shows the same problem as the 'force' statement, which *is*
> very useful.
I get it. Thanks.
> X's error message and docs claim that it's the hierarchical reference
> on the LHS ('top.mod.x') which is unsupported, but ISE actually has no
> problem with hierarchical lvalues. It only appears to be procedural
> force/assign which is affected.
See slide 4 here
http://www.csee.umbc.edu/~plusquel/415/slides/verilog_behav_const.pdf
claims a related Xilinx synthesis limitation.
"A procedural continuous assignment (PCA)
creates a dynamic binding to a register
variable when the statement executes.
It uses "=" as in procedural assignment
with the keyword assign.
WARNING: The Xilinx synthesis engine does not accept this Verilog construct"
-- Mike Treseler
Article: 124924Dan We are based in the UK although only have limited USM coverage on released products. Details of our products here http://www.enterpoint.co.uk/boardproducts.html. John Adair Enterpoint Ltd. On 10 Oct, 09:26, dan.walms...@gmail.com wrote: > I need to find a cheap UK supplier for a spartan 3 development kit, > prepherably USB, it needs to be suitable to implement a small softcore > processor and ideal for someone with no previous experience. > > I can find lots of products in the US but none in the UK. > > Dan Walmsley
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