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When i add existing source files ISE copies them to the project directory but i want to use them in their current directories (by reference). It's a small point but i cant seem to find out how to do it...... Is there a box I can tick somewhere saying Do Not Copy Source To Project Directory? Cheers :-SArticle: 130776
http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 Ta Da! AustinArticle: 130777
On Apr 1, 3:42 pm, robquig...@gmail.com wrote: > When i add existing source files ISE copies them to the project > directory but i want to use them in their current directories (by > reference). It's a small point but i cant seem to find out how to do > it...... > > Is there a box I can tick somewhere saying Do Not Copy Source To > Project Directory? > > Cheers > > :-S Oh i think this was because i was using the wizard and it must copy files to the project directory by default :-(Article: 130778
On Apr 1, 12:44 am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > 9.2.4 > Number of 4 input LUTs: 55604 out of 88192 63% > > 10.1.0 > Number of 4 input LUTs: 54316 out of 88192 61% > > Actually there is a 2.3% reduction in area. > The number of slices is meaningless, it only tells you the LUTs are > distributed. OK - I'm with you part of the way on that. New behavior in XST has altered the balance of FFs to LUTs and should improve the overall area of the design. Further on though, MAP has spread this smaller area out over a larger portion of the available logic. Is this a problem? Maybe, maybe not. You have to admit however that the new PAR has intractable place and route issues. Whether those originated in XST or MAP or even PAR is difficult to determine. EricArticle: 130779
On 1 Apr, 15:59, austin <aus...@xilinx.com> wrote: > http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 > > Ta Da! > > Austin Must be an April fools joke, because obviously you wont be able to buy it for a year.Article: 130780
Jon, Ha ha. It is shipping, as ES. Right now. The early access program is now over, and we have already been shipping ES parts, for quite awhile. AustinArticle: 130781
Minor Correction, The 'early access' program isn't "over", but it is winding down! One could say it is over for the two released parts, and ongoing for the others to be released as stated. We decided that it was in everyone's interest to release everything: silicon, software, IP, reference designs, demo pcbs, characterization reports, ... all at once (what a concept). So, we just did. Quite honestly, I am frankly amazed at what has been accomplished, and how smoothly it has been. If I compare this to the other 8 major releases I have taken part in over the last ten years, this is in every category, the most complete, and highest quality. Does that mean we can stop working? Are we done? Of course not: the goal is to do it even better with each and every release, so we do note down every complaint, and every "whoops" so that attention is focused for the future releases. Yes, I do write down every complaint of our friend, Antti and everyone else, too. AustinArticle: 130782
On Apr 1, 5:31=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > I've read all the posts here but have lost track of how you're > getting on. > > Can you post an update and describe what the problem turned out > to be? > > Nial. Let me make a categorical statement: When a high-frequency clocks a flip-flop that has a significantly lower frequency on its D input (which is what Antti descibes) then there is NO POSSIBILITY for the flip-flop Q output to have FEWER transitions than its D input. But there can be additional transitions on Q due to slow data transitions, noise, and even the rare metastability. But NEVER a missing transition on Q. Peter AlfkeArticle: 130783
On 1 Apr., 18:52, Peter Alfke <pe...@xilinx.com> wrote: > On Apr 1, 5:31 am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > I've read all the posts here but have lost track of how you're > > getting on. > > > Can you post an update and describe what the problem turned out > > to be? > > > Nial. > > Let me make a categorical statement: > When a high-frequency clocks a flip-flop that has a significantly > lower frequency on its D input (which is what Antti descibes) then > there is NO POSSIBILITY for the flip-flop Q output to have FEWER > transitions than its D input. But there can be additional transitions > on Q due to slow data transitions, noise, and even the rare > metastability. But NEVER a missing transition on Q. > > Peter Alfke hi Peter, you know was almost to ask this in private (to save embarrassement) from what I understand I also did think that the Q can not have missing (less) transactions. thats why my results did wonder me so much: 1:10M double (extra transition) 1:100M missing transition now the signal and PCB are know be ok, and without the FF in the strobe line there are no error as long as i have tested >6hours, not single error. the input signal is actually very good one, so I would bet even the 1:10M extra transitions is too much (well here I dont know for sure if there is any rule of thumb to calculate this ration) eh, I wisch I could have choose Xilinx FPGA this project, as the first Xilinx based prototype worked without any issues ever seen. But unfortunatly the target device is Actel, where the fabric is very different, and device is way too small also :( ok, the rd_wr_strobe errors I got fully rid off, but my full design still has errors, which also may be related so some strobe/clocking the first "glitch" strobe was one of 2 async interfaces, there other being slave SPI in FPGA, where external MCU is SPI master at about 4 mhz spi clock. the second interface reads 8 bytes, and writes 3 bytes while all the reads are always good, in the data path external SPI into FPGA seem again be random errors, with rather high rate, but the logic is only 2 shift registers one shifting in SPI data, and the other being initialized from the spi shift register. no on this path, seems also be some violation.. so i am still debugging my design :( this secondary SPI is where i did see the shift register to fail (when it uses local routing), but now it is forced global clock, and besides that shift register there is only one load to another register that may be failing. working step by step closer to the place where the last error could be. eh without onchip logic analyzer it not so fun, and adding it is out of the question, only if route out and use some xilinx board to desirialize trace data Antti Nial I was about to answer you too, but I wasnt onlineArticle: 130784
On Apr 1, 9:04=A0am, Jon Beniston <j...@beniston.com> wrote: > On 1 Apr, 15:59, austin <aus...@xilinx.com> wrote: > > >http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=3D7 > > > Ta Da! > > > Austin > > Must be an April fools joke, because obviously you wont be able to buy > it for a year. Jon, as the press release says: "Virtex-5 FXT FPGA samples are now shipping for the FX30T and FX70T devices. " So, when do you need one of those, or how many? Put your order in with your favorite distributor, and let's compare notes. This is NOT April fools' day, this is serious business. I hope you are serious, too. We love to have you as a customer. Peter Alfke, XilinxArticle: 130785
> Jon, as the press release says: > "Virtex-5 FXT FPGA samples are now shipping for the FX30T and FX70T > devices. " > So, when do you need one of those, or how many? > Put your order in with your favorite distributor, and let's compare > notes. > This is NOT April fools' day, this is serious business. I hope you are > serious, too. > We love to have you as a customer. > Peter Alfke, Xilinx You know what they say: once bitten, twice shy. When the main distributors have parts actually in stock, I might take a look. Cheers, JonArticle: 130786
On Apr 1, 10:59 am, austin <aus...@xilinx.com> wrote: > http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 > > Ta Da! > > Austin I am salivating over the SX240T. Any idea of when it will be available and for how much?Article: 130787
I am curious about the ISE fuse FATAL_ERROR that was encountered. What platform/OS is ISE running on? Sonal Antti wrote: > On 31 Mrz., 16:29, Antti <Antti.Luk...@googlemail.com> wrote: >> On 31 Mrz., 15:31, Kolja Sulimma <ksuli...@googlemail.com> wrote: >> >>> On 31 Mrz., 10:46, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: >>>> I just wanted to mention.. >> ok, here come my comments too, FIRST TRIAL with 10.1, 4 minutes after >> first installation >> >> "Errorr:Portability:3, please open webcase" >> it tells me that it has run OUT memory, and that current memory useage >> is 312200 kb >> >> this is brand new PC with 2GB RAM, its FRESH new OS install, no other >> applications running than ISE >> >> so time to first fatal error has decreased from 20 (ISE 9.X) to 4 >> minutes. >> >> Antti is waiting for 10.x service packs. > > after terminating the initial msg popups, another did come with "fatal > in gui something" then ISE self-terminated. > after opening the project again, doing clean and rerun, following > comes: > > FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 > 21:25:47 > sonals Exp $ - Failed to link the design Process will terminate. > For > technical support on this issue, please open a WebCase with this > project > attached at http://www.xilinx.com/support. > FATAL_ERROR:Simulator:Fuse.cpp:164:$Id: Fuse.cpp,v 1.35 2007/11/07 > 21:25:47 sonals Exp $ - Failed to link the design Process will > terminate. For technical support on this issue, please open a WebCase > with this project attached at http://www.xilinx.com/support. > > well done Xilinx, I just installed it on new PC to checkout something > quick... and all i get quick are fatal errors and self termination and > requests to open webcases... > > Antti > > > > >Article: 130788
On Apr 1, 12:52=A0pm, Peter Alfke <pe...@xilinx.com> wrote: > On Apr 1, 5:31=A0am, "Nial Stewart" > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > I've read all the posts here but have lost track of how you're > > getting on. > > > Can you post an update and describe what the problem turned out > > to be? > > > Nial. > > Let me make a categorical statement: > When a high-frequency clocks a flip-flop that has a significantly > lower frequency on its D input (which is what Antti descibes) then > there is NO POSSIBILITY for the flip-flop Q output to have FEWER > transitions than its D input. But there can be additional transitions > on Q due to slow data transitions, noise, and even the rare > metastability. But NEVER a missing transition on Q. > > Peter Alfke Peter, While while you said is true, Antti and you (I think) are both assuming that there was a missing transition on the output of the flop that Antti put on the input strobe. While that would produce the symptoms that he saw, it is not possible as you've noted. Keep in mind that Antti never actually measured a missing strobe, he never even measured a skip or hiccup on the two bit counter that the strobe was clocking. What he did measure were other downstream symptoms that could be explained by a missing strobe...or by a two bit counter that counted 4 times instead of 1...or by one that counted incorrectly in some other fashion due to failing timing. The symptoms that he did report could be explained by failing timing (it's not clear that timing analysis on both fast and slow sides or cross clock domain analysis was performed even when I specifically asked that). Another issue is that the flop output has potential for metastability which then creates possibilities for creating additional clocks inside the device which might be violating timing as well or simply clocking the two bit counter more times that expected to give the system level appearance of a 'missing' strobe. Getting rid of the flop on the strobe input pin thereby allowing the input pin to basically be used to clock whatever it is that needs clocking with that signal, seems to have gotten Antti's design over the hump. Take your choice, I'll lean towards the explainable hypothesis rather than the unexplainable one at any time. Kevin JenningsArticle: 130789
On 1 Apr., 20:28, KJ <kkjenni...@sbcglobal.net> wrote: > On Apr 1, 12:52 pm, Peter Alfke <pe...@xilinx.com> wrote: > > > On Apr 1, 5:31 am, "Nial Stewart" > > > <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > > I've read all the posts here but have lost track of how you're > > > getting on. > > > > Can you post an update and describe what the problem turned out > > > to be? > > > > Nial. > > > Let me make a categorical statement: > > When a high-frequency clocks a flip-flop that has a significantly > > lower frequency on its D input (which is what Antti descibes) then > > there is NO POSSIBILITY for the flip-flop Q output to have FEWER > > transitions than its D input. But there can be additional transitions > > on Q due to slow data transitions, noise, and even the rare > > metastability. But NEVER a missing transition on Q. > > > Peter Alfke > > Peter, > > While while you said is true, Antti and you (I think) are both > assuming that there was a missing transition on the output of the flop > that Antti put on the input strobe. While that would produce the > symptoms that he saw, it is not possible as you've noted. > > Keep in mind that Antti never actually measured a missing strobe, he > never even measured a skip or hiccup on the two bit counter that the > strobe was clocking. What he did measure were other downstream > symptoms that could be explained by a missing strobe...or by a two bit > counter that counted 4 times instead of 1...or by one that counted > incorrectly in some other fashion due to failing timing. > > The symptoms that he did report could be explained by failing timing > (it's not clear that timing analysis on both fast and slow sides or > cross clock domain analysis was performed even when I specifically > asked that). Another issue is that the flop output has potential for > metastability which then creates possibilities for creating additional > clocks inside the device which might be violating timing as well or > simply clocking the two bit counter more times that expected to give > the system level appearance of a 'missing' strobe. > > Getting rid of the flop on the strobe input pin thereby allowing the > input pin to basically be used to clock whatever it is that needs > clocking with that signal, seems to have gotten Antti's design over > the hump. Take your choice, I'll lean towards the explainable > hypothesis rather than the unexplainable one at any time. > > Kevin Jennings Hi Kevin, yes i only monitored a table lookup addressed by the 2 bit counter. correct the "missing" could have been extra 3 clocks, but well I measured in chunks of 12 strobes, and withing those 3 strobes either was 1 extra or 1 missing, this could have been 3 extra also but a case 2 exra was never seen so I assumed the possibility that 1 extra clocks comes 1:10M 2 extra clocks NEVER 3 extra clocks 1:100M while missing clock could have basically been 3 clocks, well it looked very inlikely that withing 12 clocks only either 1 or 3 extra clocks happen, also i think the error ratio of 3 vs 1 extra should have been greater. whatever speculations all, as the test was not done clean enough.. AnttiArticle: 130790
On Apr 1, 10:59=A0am, Jon Beniston <j...@beniston.com> wrote: > > You know what they say: once bitten, twice shy. > > When the main distributors have parts actually in stock, I might take > a look. > > Cheers, > Jon Jon, good news: Order entry is open as of today Lead time is 5 weeks. That means, with luck you can have parts in your hand this April, but definitely in May. Challenge us! Peter AlfkeArticle: 130791
Jon, Nope, but this is: http://www.pldesignline.com/products/207000972;jsessionid=YJDDTCDB5RJLWQSNDLOSKH0CJUNN2JVN AustinArticle: 130792
On Mar 31, 5:25 pm, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Hi All, > > I have custom board with 4 Spartan-3E (XC3S500E-PQ208). For > configuration I have both JTAG and slave serial access. Slave serial > works fine. However, when I try to identify the JTAG chain the first > FPGA always comes back UNKNOWN. > > If I'm correct, impact's response to the identify command lists the > devices in reverse order. So the when it reports this: > > '1': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:1777 - > Reading /opt/xilinx-ProgTools-9.1i/spartan3e/data/xc3s500e.bsd... > > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 0000 > > '2': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 0000 > > '3': : Manufacturer's ID =Xilinx xc3s500e, Version : 0 > INFO:iMPACT:501 - '1': Added Device xc3s500e successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > Version is 1110 > INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part. > '4': : Manufacturer's ID =Unknown , Version : 14 > > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > done. > > the unknown device is actually the first in the chain. Slave serial uses > the same device order, so the problem FPGA is also the first in the > slave serial chain. > > - I'm using a Platform Cable USB. > - VCCAUX is 2.5V > - All DONE pins are commoned with a 330R to 2.5V (VCCAUX) > - All PROG_B pins are commoned with a 4.7K to 2.5V > - All INIT_B pins are commoned with a 4.7K to 3.3V (VCCO) > - ISE 9.1i under linux > > I've tried isolating the problem FPGA and it will not identify. I've > also isolated the last three, these do identify (and configure). > > I'm quite sure it is not a faulty FPGA. I've 4 other boards that show > the same behaviour. > > Here are the complete schematics:http://www.elec.york.ac.uk/intsys/users/ajg112/board.pdf > > Any suggestions as to what the problem might be would be a great help > > Thanks > Andy Try to add 100R serial resitor between each TCK and the corresponding FPGA PAD (up the PAD pin and add the resistor) Verify that the last TDO (FPGA3config to your JTAG connector) is not routed close to the TCK !!! I am almost sure your VCCAUX is OK, I will first check the JTAG signal integrity ;-) Also, check that the GND is weel connected between the board and your JTAG emulator. - Larry http://www.amontec.comArticle: 130793
Hi,
I want to use RLOC function of ISE 9.2. I find at the end, all logic
are optimized out, see below the simplest example. I can see the
results after synthesis are correct. How to avoid this? Thanks in
advance.
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
--
-- op <= A +/- B or A
--
entity acc_sub1 is
generic (
WIDTH : in natural := 4
);
port (
POPT_A : in std_logic_vector(WIDTH-1 downto 0);
PORT_B : in std_logic_vector(WIDTH-1 downto 0);
PORT_S : out std_logic_vector(WIDTH-1 downto 0)
);
end;
--use work.pkg_xilinx_prims.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
architecture VIRTEX of acc_sub1 is
attribute RLOC: string;
attribute INIT: string;
begin
INST : for i in WIDTH-1 to 1 generate
attribute RLOC of u_lut : label is "X" & integer'image(i) &
"Y0";
attribute INIT of u_lut : label is "C6C6";
begin
u_lut : LUT4
--pragma translate_off
generic map (INIT => X"6C6C") --6969")
--pragma translate_on
port map (
I0 => POPT_A(i),
I1 => PORT_B(i),
I2 => '0',
I3 => '0',
O => PORT_S(i));
end generate;
end Virtex;
Article: 130794Andrew Greensted <ajg112@ohm.york.ac.uk> wrote: >Andrew Greensted wrote: >> Looks like I've got a similar problem. After removing the oscillator >> module the JTAG identification works fine. > >I've dropped in a lower frequency oscillator module, that seems to have >improved things. It's not a massive problem, I'll just use a DCM to >multiply things up. > >I'm guessing the oscillator was causing noise on VCCO. However, isn't >the JTAG TAP and IO powered by VCCAUX? SOmehow JTAG is extremely sensitive to electrical parameters. IIRC the method used to generate the waveforms by Impact is not the best around (data and clk are changed simultaneously). I've also had these sort of problems on boards with multiple FPGAs. Sometimes adding a small RC to the clock (TCK) line may help. You can use an oscilloscope to very setup & hold timing on the JTAG bus. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 130795
I've been getting a lot of GUI errors in XPS. It pops up an error message and then it hangs. I really wanna know: when are they going to shitcan the binary ISE project file and go back to a text file? You know, some of us actually LIKE things we can put into our source-code control systems. -aArticle: 130796
On Mar 19, 4:20 am, ratztafaz <heinerl...@googlemail.com> wrote: > What other major features to you still miss? - Discuss! Oh, let's see: a) When you include an EDK project (.xmp) in your ISE project, the tools should be smart enough to know that the external ports in your .mhs file should NOT synthesize to include I/O pads. b) The magic line in the .xmp file that makes what I describe in a) actually work should be DOCUMENTED. c) The ISE project file should be PLAIN TEXT, not some magic binary file that grows and grows. Xilinx, do you know anything about source- code control? I didn't think so. d) The required directory hierarchy for the EDK is inflexible and very unfriendly for those who use source-code control. I'm sure I'll come up with more later ... -aArticle: 130797
austin wrote: > It is shipping, as ES. Right now. > > The early access program is now over, and we have already been shipping > ES parts, for quite awhile. What means ES? At your online store: http://www.xilinx.com/onlinestore/silicon/online_store_v5.htm I don't see it. How much will it cost? I'm working for a company, who plans a new product and we are evaluating new chips. Do you know the new AT91SAM9263? http://www.atmel.com/dyn/resources/prod_documents/6249s.pdf This chip costs about $19 for 100 units ( http://tinyurl.com/36wbud ) and I have quotes of $13 for 1000 units. But our product needs some FPGA and DSP power, too. A single chip solution like the Virtex-5 FXT, sounds like an interesting idea, but how much does the IP cost for USB, ethernet, LCD controller, 2D graphics accelerator etc., which I get for free with the Atmel chip, a free Linux distribution included? The Atmel chip, with some small integrated FPGA capabilities, like Spartan, would be the ideal solution for our product. Currently we are planning to use an additional small FPGA and some inexpensive DSPs from Freescale. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 130798
austin <austin@xilinx.com> wrote: >http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 "Xilinx is actively engaged in the open source Linux community." We are looking forward for the system friendly libusb jtag drivers.Article: 130799
paragon.john@gmail.com wrote: > On Apr 1, 10:59 am, austin <aus...@xilinx.com> wrote: >> http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 >> >> Ta Da! >> >> Austin > > I am salivating over the SX240T. Any idea of when it will be > available and for how much? Ding ding. http://en.wikipedia.org/wiki/Ivan_Pavlov HTH, Syms.
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