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I have written a VHDL code to generate random numbers using a "process". I want to implement the same using function/procedure so it be a part of a package. I would like to know if this should be done using a function or procedure. How would a variable maintatin its pervious state in a function/procedure? eg: if i generated 3 using rand, then next time i call rand I want to generate the next random number after that Can this be implemented using impure functions?Article: 131801
On May 2, 4:39=A0pm, austin <aus...@xilinx.com> wrote: > Nemesis, > > How is the HSWAP_EN pin connected? =A0This enables/disables the internal > weak pullups while configuring. > > If the weak pullup is not enabled, then the pin is tristate while > powering ON. I don't know, the FPGA is mounted on a mezzanine card (GE Fanuc, ICS8550) ... and I don't have schematics of this board. > A pulldown resistor, once the IOs are set to be tristate while > configuring, is the probably answer. =A0The IO pin leakage worst case is > 10uA, so if there is no other leakage, the pulldown could be something > like 10K or 100K ohms, and be sufficient. > > Even a very weak LVCMOS IO standard should be able to pull up 10K to the > Vcco rail. Unfortunately the mezzanine is mounted on a carrier board with some LVCMOS bufffers, I'm not sure I can add pulldown resistors. I think this is going to be a tough problem.Article: 131802
FP wrote:
> Can this be implemented using impure functions?
Yes, but if you want to package it, pass a
parameter to a shift function something like this ...
_______
constant msb : natural := len_char_g -1;
subtype char_t is unsigned(msb downto 0); -- generic type, 8 bits
constant mask_c : char_t := "111" + zero_c;
function randomize (arg_byte : char_t)
return char_t is
variable result_v : char_t;
begin
result_v := arg_byte; -- here it is
result_v := shift_left(result_v, 1); -- shift it
if (result_v(result_v'left)) = '1' then -- maybe invert mask bits
result_v := result_v xor mask_c;
end if;
return result_v;
end function randomize;
______
... from a synchronous process.
-- Mike Treseler
Article: 131803
Mike Treseler wrote:
> 1. Make sure that your one clock got assigned to a global
> clock line. When a clock is routed through the fabric,
> even for a short excursion, hold violations will occur and shifters
> don't always shift right. What is the worst slack time on your
> STA report? Make sure to use the newer of two static
> timers. Any odd or complicated constraints? Are all paths
> being covered?
>
> 2. Double check your design rules.
> Are all processes synchronous using
> a standard template? Is the reset pulse
> synchronized to the clock on deassertion?
> Any odd IP or generated code or netlists?
>
> 3. Check your functional sims for coverage
> and add some edge cases.
>
> 4. Zero in on the problem area by slicing
> out pieces of the design. Make a simple entity
> that demonstrates the problem.
>
> 5. Find out who your local FAE is and call him every day.
>
> 6. Eliminate or understand all of the synthesis warnings from quartus.
Repeat using brand X-ise and look at those warnings.
Tell your brand A-FAE about your ISE experiments ;)
Article: 131804FP, I can't possibly see how you have done what you claim (generate a random number from VHDL code). Did you mean to say a quasi-random number? Such as a LFSR? And a process statement, http://www.gmvhdl.com/process.htm creates no hardware, but is a "black box" of the function, and mostly just used in verification to model something that is not part of what is being implemented. The fact that you use the word "call" means you are thinking of VHDL as a conventional software program, which it is NOT. VHDL and verilog are hardware description languages, and all statements are executed in parallel. So, one the next clock tick, whatever is supposed to change (update) does so, in parallel, all at once. AustinArticle: 131805
Nemesis, OK, let us assume the weak pullups are enabled. How strong are they? Table 3 states 200 uA to 3.3 V (check for your Vcco) http://www.gmvhdl.com/process.htm So, to pull that down to 0.3 volts, ie drop 3 volts, you need 3/200uA = 3/2 E4 ohms, or 15K (check my math). AustinArticle: 131806
<bishopg12@gmail.com> wrote in message news:50337b3d-7acd-4285-9de3-0e19f98fab96@t54g2000hsg.googlegroups.com... > We are trying to develop a system that utilizes a Xilinx XC4VFX12 chip > and platform flash. One of our main goals is to be able to remotely > upgrade the bitfiles in the platform flash through ethernet and > rs232. Is it possible to program the platform flash from the fpga/ > powerpc core using the jtag chain? My idea was to have the powerpc > get the bitfile from whatever source, store it in ram, then send it to > the platform flash using some type of jtag interface (soft core or > software on the powerpc). Many of the examples I have seen involve > using cplds and other external logic, not this way. The answer is XAPP058 :) Also read the recent thread about the xsvf player. /MikhailArticle: 131807
On May 2, 12:56=A0pm, austin <aus...@xilinx.com> wrote: > FP, > > I can't possibly see how you have done what you claim (generate a random > number from VHDL code). > > Did you mean to say a quasi-random number? Such as a LFSR? > > And a process statement, > > http://www.gmvhdl.com/process.htm > > creates no hardware, but is a "black box" of the function, and mostly > just used in verification to model something that is not part of what is > being implemented. > > The fact that you use the word "call" means you are thinking of VHDL as > a conventional software program, which it is NOT. =A0VHDL and verilog are > hardware description languages, and all statements are executed in paralle= l. > > So, one the next clock tick, whatever is supposed to change (update) > does so, in parallel, all at once. > > Austin Here is is code procedure rand ( S1,S2 : in positive; min,max : in integer; rand : out real ) is begin -- generate random number in real format uniform(S1,S2,rand1); -- seed values rand :=3D (real(min) + (rand1 * (real(max)-real(min)))); end procedure rand; process variable randOut : real; begin rand(50,10,2,20,randOut); wait for 5 ns; end process; The problem with the above is, it just gives me one output. I want it to give me a new output every 5 ns. If I put the procedure functionality in the process, I get that but not when I seperate them. I need something to hold the pervious state.Article: 131808
On May 2, 12:56=A0pm, austin <aus...@xilinx.com> wrote: > FP, > > I can't possibly see how you have done what you claim (generate a random > number from VHDL code). > > Did you mean to say a quasi-random number? Such as a LFSR? > > And a process statement, > > http://www.gmvhdl.com/process.htm > > creates no hardware, but is a "black box" of the function, and mostly > just used in verification to model something that is not part of what is > being implemented. > > The fact that you use the word "call" means you are thinking of VHDL as > a conventional software program, which it is NOT. =A0VHDL and verilog are > hardware description languages, and all statements are executed in paralle= l. > > So, one the next clock tick, whatever is supposed to change (update) > does so, in parallel, all at once. > > Austin This is just for siumlation.Article: 131809
Bob, The startup clock problem didn't occur to me because I am actually programming a Platform Flash rather than FPGA, thus CCLK is the correct clock in my case.... > Looking at the Properties dialog for the "Generate Programming File" > process, I see "FPGA Start-Up Clock" under "Startup Options" , which > is indeed set to CCLK - seems this is the default setting, is that > true? So you are suggesting I change this to "JTAG Clock", right? That's what you have to do. > And just in case, where do I "check the startup options to check how > many clocks you need"? Is this in the data sheet? Under the same "Start Options" you can see Done (output Events) set to probably 4 and Release Write Enable set to probably 6. The last number I believe is the number of extra clocks required after the bitstream has been shifted in the chip. However, I don't think this is your problem as I am sure iMPACT adds all the required cycles to your xsvf file. I am pretty sure your problem is with the startup clock as Gabor noticed. /MikhailArticle: 131810
More, The process statement does execute statements (in this case, instructions) in order, and is in essence, a convenience to put conventional software 'instructions' inside the VHDL, but as I noted, it doesn't create any hardware. AustinArticle: 131811
austin wrote:
> And a process statement,
> http://www.gmvhdl.com/process.htm
> creates no hardware, but is a "black box" of the function, and mostly
> just used in verification to model something that is not part of what is
> being implemented.
If we are talking about VHDL,
a process is always required to make *any* hardware.
> The fact that you use the word "call" means you are thinking of VHDL as
> a conventional software program, which it is NOT. VHDL and verilog are
> hardware description languages, and all statements are executed in parallel.
That is how most hardware guys write vhdl code.
But I can, if I choose, describe parallel hardware with a
sequential description in a single process like this...
http://mysite.verizon.net/miketreseler/
...and call all the functions a procedures that I want.
-- Mike Treseler
Article: 131812On May 2, 1:28=A0pm, FP <FPGA.unkn...@gmail.com> wrote: > On May 2, 12:56=A0pm, austin <aus...@xilinx.com> wrote: > > > Here is is code > procedure rand ( S1,S2 : in positive; min,max : in integer; rand : out > real ) is > > =A0 begin > =A0 =A0 =A0 =A0 -- generate random number in real format > =A0 =A0 =A0 =A0 uniform(S1,S2,rand1); -- seed values > =A0 =A0 =A0 =A0 rand :=3D (real(min) + (rand1 * (real(max)-real(min)))); > =A0end procedure rand; > > =A0process > =A0 =A0variable randOut : real; > =A0 begin > =A0 =A0 =A0 =A0 rand(50,10,2,20,randOut); > =A0 =A0 =A0 =A0 wait for 5 ns; > =A0 end process; > > The problem with the above is, it just gives me one output. I want it > to give me a new output every 5 ns. If I put the procedure > functionality in the process, I get that but not when I seperate them. > I need something to hold the pervious state.- Hide quoted text - > Your seed values that get passed into 'uniform' (S1, S2) need to be of type 'inout' and they need to be maintained in whatever process it is that calls your 'rand' procedure. KJArticle: 131813
KJ wrote:
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
> news:fv7i38$69n6@cnn.xsj.xilinx.com...
>> My question: what is the cleanest way to describe an FSM requiring
>> pipelining?
...
> The other thing to consider is whether the latency being introduced by this
> outsourced logic needs to be 'compensated for' in some fashion or is it OK
> to simply wait for the acknowledge. In some instances, it is fine for the
> FSM to simply wait in a particular state until the acknowledge comes back.
> In others you need to be feeding new data into the hunk-o-logic on every
> clock cycle even though you haven't got the results from the first back. In
> that situation you still have the req/ack pair but now the ack is simply
> saying that the request has been accepted for processing, the actual results
> will be coming out later. Now the hunk-o-logic needs an additional output
> to flag when the output is actually valid. This output data valid signal
> would typically tend to feed into a separate FSM or some other logic (i.e.
> 'usually' not the first FSM). The first FSM controls feeding stuff in, the
> second FSM or other processing logic is in charge of taking up the outputs
> and doing something with it.
>
...
>
> Kevin Jennings
>
In this case I do indeed have to continue to keep the pipe full, so
inserting wait states is not an option. And the latency of the "hunk of
logic", aka concurrent process, is actually significant because I have
to get the result and feed it back into the FSM. This example shows why:
STATE2: begin
if (condition)
begin
state <= STATE3;
y <= (a*b+c)*d;
end
end
I have to get the result (a*b+c) and then feed it back into the FSM so I
can multiply by d. Why not just let the concurrent process handle that?
Because I want to limit my resource usage to a single DSP48, so I have
to schedule the multiplications inside the FSM. But I'll have to check
out the Wishbone thing you're talking about.
-Kevin
Article: 131814On 2 Mai, 19:32, "MM" <mb...@yahoo.com> wrote: > Bob, > > The startup clock problem didn't occur to me because I am actually > programming a Platform Flash rather than FPGA, thus CCLK is the correct > clock in my case.... > > > Looking at the Properties dialog for the "Generate Programming File" > > process, I see "FPGA Start-Up Clock" under "Startup Options" , which > > is indeed set to CCLK - seems this is the default setting, is that > > true? So you are suggesting I change this to "JTAG Clock", right? > > That's what you have to do. > > > And just in case, where do I "check the startup options to check how > > many clocks you need"? Is this in the data sheet? > > Under the same "Start Options" you can see Done (output Events) set to > probably 4 and Release Write Enable set to probably 6. The last number I > believe is the number of extra clocks required after the bitstream has been > shifted in the chip. However, I don't think this is your problem as I am > sure iMPACT adds all the required cycles to your xsvf file. I am pretty sure > your problem is with the startup clock as Gabor noticed. > > /Mikhail impact DOES NOT and CAN NOT change startup clock if playing back already generated xsvf files. just think about it. it can not do it. so if the xscv played with impact work, then it is valid (also correct startup clock) AnttiArticle: 131815
Mike, OK, I thought I knew something and now I am confused by your answer. A simulator will "execute" the VHDL and provide you with a verification (simulation) of whatever it is you are trying to do. Targeting that VHDL to a synthesis tool will use a library of hardware elements (in an FPGA: LUTs, CLBs, etc; or in an ASIC: gates, registers, flip flops, etc) and result in a hardware design that performs the function you desired. Some VHDL statements are for testing and test benches (simulation) and don't create hardware (like a "wait 5ns" statement), right? The hardware only knows about clock edges, so every single element of the hardware (statement of VHDL) operates at once, there is no "sequence of operation" as there is in a c program, for example execute the first instruction, then the next, and so on -- does not exist in the synthesized hardware. In hardware it is on the next rising edge, do everything everywhere based on the last state of all of the registers, flip flops, latches, etc. http://www.sunburst-design.com/papers/CummingsSNUG1999SJ_SynthMismatch.pdf http://www.martiangeek.com/2008/01/16/how-to-write-hdl-code-that-works/ http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m12_23/sld004.htm AustinArticle: 131816
Hmmm, I see something that might confuse. A VHDL if, case, or loop may seem to have sequential behavior, but when synthesized into hardware, really "executes" on a condition (such as a rising clock edge). Thus on a clock tick, the entire if-then-else, case, or loop is evaluated, and the new state is a result of the previous state after the clock tick. This is much different than a software program which takes many clock cycles to rattle though each instruction of the if-then-else, case, or loop; and after each instruction, you are not really through evaluating all the conditions, and you haven't updated the entire state until to get to the end of the if-then-else, case, or loop. AustinArticle: 131817
Having two bits hot in a one-hot FSM would normally be a bad thing. But
I was wondering if anybody does this purposely, in order to fork, which
might be a syntactically nicer way to have a concurrent FSM. This would
imply that multiple states in the FSM could be active at once. This
would be an example:
parameter STATE1=1, STATE2=2, STATE33,... // state defs
casex (state)
...
if (state[STATE1]) begin
if (condition)
begin
m <= a*b;
state[STATE3] <= 1; // fork into 2 new states
state[STATE4] <= 1;
state[STATE1] <= 0; // leave current state
end
end
if (state[STATE3]) begin // DSP48 Adder Stage
p <= m+c;
state[STATE3] <= 0; // this fork dies
end
if (state[STATE4]) begin
m <= a2*b2;
state[STATE3] <= 1; // fork into 2 new states
state[STATE5] <= 1;
state[STATE4] <= 0; // leave current state
end
In this case I have a pipeline (as in a DSP48) which I can keep
continuously fed. A separate fork of the SM runs the pipeline. I can
turn on two one-hot bits (essentially ORing the states) to fork into
multiple states. One fork eventually kills itself. This might be nicer
than having a separate concurrent FSM. There may be a better syntax
that still allows a case statement. I just wondered if this is a common
or useful technique.
-Kevin
Article: 131818Kevin Neilson wrote: > > parameter STATE1=1, STATE2=2, STATE3=3,... // state defs > reg [31:0] state; > if (state[STATE1]) begin > if (condition) > begin > m <= a*b; > state[STATE3] <= 1; // fork into 2 new states > state[STATE4] <= 1; > state[STATE1] <= 0; // leave current state > end > end > if (state[STATE3]) begin // DSP48 Adder Stage > p <= m+c; > state[STATE3] <= 0; // this fork dies > end > if (state[STATE4]) begin > m <= a2*b2; > state[STATE3] <= 1; // fork into 2 new states > state[STATE5] <= 1; > state[STATE4] <= 0; // leave current state > end > Sorry; there was not supposed to be a case statement here.Article: 131819
On May 2, 2:19=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On May 2, 1:28=A0pm, FP <FPGA.unkn...@gmail.com> wrote: > > > > > > > On May 2, 12:56=A0pm, austin <aus...@xilinx.com> wrote: > > > Here is is code > > procedure rand ( S1,S2 : in positive; min,max : in integer; rand : out > > real ) is > > > =A0 begin > > =A0 =A0 =A0 =A0 -- generate random number in real format > > =A0 =A0 =A0 =A0 uniform(S1,S2,rand1); -- seed values > > =A0 =A0 =A0 =A0 rand :=3D (real(min) + (rand1 * (real(max)-real(min))));= > > =A0end procedure rand; > > > =A0process > > =A0 =A0variable randOut : real; > > =A0 begin > > =A0 =A0 =A0 =A0 rand(50,10,2,20,randOut); > > =A0 =A0 =A0 =A0 wait for 5 ns; > > =A0 end process; > > > The problem with the above is, it just gives me one output. I want it > > to give me a new output every 5 ns. If I put the procedure > > functionality in the process, I get that but not when I seperate them. > > I need something to hold the pervious state.- Hide quoted text - > > Your seed values that get passed into 'uniform' (S1, S2) need to be of > type 'inout' and they need to be maintained in whatever process it is > that calls your 'rand' procedure. > > KJ- Hide quoted text - > > - Show quoted text - what do you exactly mean by maintain?Article: 131820
austin wrote:
> OK, I thought I knew something and now I am confused by your answer.
>
> A simulator will "execute" the VHDL and provide you with a verification
> (simulation) of whatever it is you are trying to do.
Sorry. I thought that mk was talking bout synthesis.
> Targeting that VHDL to a synthesis tool will use a library of hardware
> elements (in an FPGA: LUTs, CLBs, etc; or in an ASIC: gates, registers,
> flip flops, etc) and result in a hardware design that performs the
> function you desired.
That's the object.
The source may be structural or sequential.
-- Mike Treseler
Article: 131821On May 2, 3:04=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote: > austin wrote: > > OK, I thought I knew something and now I am confused by your answer. > > > A simulator will "execute" the VHDL and provide you with a verification > > (simulation) of whatever it is you are trying to do. > > Sorry. I thought that mk was talking bout synthesis. > > > Targeting that VHDL to a synthesis tool will use a library of hardware > > elements (in an FPGA: LUTs, CLBs, etc; or in an ASIC: gates, registers, > > flip flops, etc) and result in a hardware design that performs the > > function you desired. > > That's the object. > The source may be structural or sequential. > > =A0 =A0 =A0 =A0-- Mike Treseler thanks a bunch guys. It works :) KJ you are of great help as alwaysArticle: 131822
On May 2, 3:04=A0pm, FP <FPGA.unkn...@gmail.com> wrote:
> On May 2, 2:19=A0pm, KJ <kkjenni...@sbcglobal.net> wrote:
>
>
>
>
>
> > On May 2, 1:28=A0pm, FP <FPGA.unkn...@gmail.com> wrote:
>
> > > On May 2, 12:56=A0pm, austin <aus...@xilinx.com> wrote:
>
> > > Here is is code
> > > procedure rand ( S1,S2 : in positive; min,max : in integer; rand : out=
> > > real ) is
>
> > > =A0 begin
> > > =A0 =A0 =A0 =A0 -- generate random number in real format
> > > =A0 =A0 =A0 =A0 uniform(S1,S2,rand1); -- seed values
> > > =A0 =A0 =A0 =A0 rand :=3D (real(min) + (rand1 * (real(max)-real(min)))=
);
> > > =A0end procedure rand;
>
> > > =A0process
> > > =A0 =A0variable randOut : real;
> > > =A0 begin
> > > =A0 =A0 =A0 =A0 rand(50,10,2,20,randOut);
> > > =A0 =A0 =A0 =A0 wait for 5 ns;
> > > =A0 end process;
>
> > > The problem with the above is, it just gives me one output. I want it
> > > to give me a new output every 5 ns. If I put the procedure
> > > functionality in the process, I get that but not when I seperate them.=
> > > I need something to hold the pervious state.- Hide quoted text -
>
> > Your seed values that get passed into 'uniform' (S1, S2) need to be of
> > type 'inout' and they need to be maintained in whatever process it is
> > that calls your 'rand' procedure.
>
> > KJ- Hide quoted text -
>
> > - Show quoted text -
>
> what do you exactly mean by maintain?- Hide quoted text -
>
> - Show quoted text -
Below is an example of how you should be calling 'uniform'
process
variable seed1: positive :=3D 12345;
variable seed2: positive :=3D 1961;
variable Random_Number: real;
begin
...
ieee.math_real.uniform(seed1,seed2, Random_Number);
end process;
seed1 and seed2 are inouts to uniform, that procedure will change the
values of seed1 and seed2. Your code is putting a little wrapper
around this to make a new procedure called 'rand'. That procedure
needs to have inout parameters as well so that they will get passed
all the way back down to 'uniform'.
Somewhere you'll have a process that *calls* your 'rand' procedure.
That process is where the seed variables will have to be declared and
then passed down through the inout S1 and S2 parameters of 'rand'.
Kevin Jennings
Article: 131823The XCV400 is on the supported list of devices for ISE Webpack http://www.xilinx.com/ise/products/webpack_config.htm so you should not have any costs for tools. I would however wonder why this device was in the trash bin as undoubtedly some longer life products still use them. John Adair Enterpoint Ltd. On 1 May, 20:44, whygee <why...@yg.yg> wrote: > Hi ! > > I have tried to enter the FPGA league for many years and I'm about > to receive (at least ! the order was paid 6 months ago) my first > prototype board with an Actel ProASIC. > At last, I'll be able to go from the VHDL simulator > to the VHDL synthesizer. > > And today, in my favorite broker's "trash bin", i find > a pair of unused Xilinx parts that may also serve me, > but past experiences with unmounted FPGA chips make me cautious : > I have already found XC3000 parts, some in PGA packages... > Even an IKOS emulatorhttp://ygdes.com/ikos/with hundreds > of FPGAs, but that are not supported anymore :-( > > The reference of today's find : > Virtex XCV400 > HQ240AFP0241 > > So it's a 240-pin PQFP package that i can rather easily solder :-) > but the marking implies a 2002 fab date, and i don't know if it's > still possible to find SW that supports this part ... > Would it be worth it to create a small dev PCB ? > (and if the synth SW can run on Linux, that's a plus) > > A google search will give results but not tell me if it is useful, > and if there is some hope to configure it to something fun. > Because besides the 2 FPGA, i have also found a bunch of SDRAM chips > and 2MB FLASH chips :-) (plus a whole lot of things i already have) > > yg, puzzled and clueless ....Article: 131824
But why not combine these two states into one states?and let that states to do the pipline stuff? Your coding may let your design slower and may not be implemented as state machine in the final design. On May 2, 2:54=A0pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > Kevin Neilson wrote: > > > parameter STATE1=3D1, STATE2=3D2, STATE3=3D3,... // state defs > > =A0> reg [31:0] state; > > > if (state[STATE1]) begin > > =A0 if (condition) > > =A0 =A0 begin > > =A0 =A0 =A0 m =A0 =A0 =A0 =A0 =A0 =A0 <=3D a*b; > > =A0 =A0 =A0 state[STATE3] <=3D 1; =A0 =A0// fork into 2 new states > > =A0 =A0 =A0 state[STATE4] <=3D 1; > > =A0 =A0 =A0 state[STATE1] <=3D 0; =A0 =A0// leave current state > > =A0 =A0 end > > end > > if (state[STATE3]) begin =A0 =A0 // DSP48 Adder Stage > > =A0 =A0 =A0 p =A0 =A0 =A0 =A0 =A0 =A0 <=3D m+c; > > =A0 =A0 =A0 state[STATE3] <=3D 0; =A0 =A0// this fork dies > > end > > if (state[STATE4]) begin > > =A0 =A0 =A0 m =A0 =A0 =A0 =A0 =A0 =A0 <=3D a2*b2; > > =A0 =A0 =A0 state[STATE3] <=3D 1; =A0 =A0// fork into 2 new states > > =A0 =A0 =A0 state[STATE5] <=3D 1; > > =A0 =A0 =A0 state[STATE4] <=3D 0; =A0 =A0// leave current state > > end > > Sorry; there was not supposed to be a case statement here.
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