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On May 22, 9:15=A0pm, Neil Steiner <neil.stei...@east.isi.edu> wrote:
> Hi Andy,
>
> I appreciate the suggestions, but I'm afraid they don't seem to be helpin=
g.
>
> >> =A0> [xxxx@xxxx test]$ find . -exec grep -nH ForceCfg {} \;
> >> =A0> Binary file ./bin/lin/unwrapped/xdl matches
> >> =A0> Binary file ./bin/lin64/unwrapped/xdl matches
>
> >> [snipped]
>
> > You should run the set up script which comes with ISE (and the
> > corresponding one for EDK).
>
> >> . /usr/local/Xilinx/10.1/ISE/settings64.sh
>
> I've already defined everything that settings64.sh is defining, but even
> when I explicitly source it, my problems remain.
>
> Regardless, if *no* file or library in the $XILINX tree provides the
> necessary symbol (refer to find command above), I don't see how any
> amount of configuration could solve the problem.
>
> > fpga_editor is a bit harder - first you want "openmotif22" installed.
>
> >> yum install openmotif22
>
> Okay, I had openmotif-2.3.1-2.el5.x86_64 installed, but I've now added
> openmotif22-2.2.3-18.x86_64. =A0Unfortunately, it makes no difference.
>
> I should point out that I have no problem opening fpga_editor. =A0I just
> can't keep it from spontaneously dying when I try to open an NCD file.
>
> > Next there's some Xilinx weirdness which may require you to;
>
> >> export DISPLAY=3D:0
>
> I'm actually using 'ssh -Y' and my DISPLAY variable looks healthy, and
> again, there's no problem starting up the fpga_editor GUI.
Here's some config information from my centos install. Perhaps it'll
help you track down where things are going wrong.
Good luck!
[andyman@xoogle /]$ ldd -v /opt/Xilinx/10.1/ISE/bin/lin64/xdl
libdl.so.2 =3D> /lib64/libdl.so.2 (0x0000003fe1000000)
libpthread.so.0 =3D> /lib64/libpthread.so.0 (0x0000003fe1400000)
libstdc++.so.6 =3D> /opt/Xilinx/10.1/EDK/lib/lin64/libstdc++.so.
6 (0x00002b06dee03000)
libm.so.6 =3D> /lib64/libm.so.6 (0x0000003fe0c00000)
libgcc_s.so.1 =3D> /lib64/libgcc_s.so.1 (0x0000003fe5400000)
libc.so.6 =3D> /lib64/libc.so.6 (0x0000003fe0800000)
/lib64/ld-linux-x86-64.so.2 (0x0000003fdf800000)
Version information:
/opt/Xilinx/10.1/ISE/bin/lin64/xdl:
libgcc_s.so.1 (GCC_3.0) =3D> /lib64/libgcc_s.so.1
libdl.so.2 (GLIBC_2.2.5) =3D> /lib64/libdl.so.2
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
libstdc++.so.6 (GLIBCXX_3.4) =3D> /opt/Xilinx/10.1/EDK/
lib/lin64/libstdc++.so.6
libstdc++.so.6 (CXXABI_1.3) =3D> /opt/Xilinx/10.1/EDK/
lib/lin64/libstdc++.so.6
/lib64/libdl.so.2:
ld-linux-x86-64.so.2 (GLIBC_PRIVATE) =3D> /lib64/ld-
linux-x86-64.so.2
libc.so.6 (GLIBC_PRIVATE) =3D> /lib64/libc.so.6
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
/lib64/libpthread.so.0:
ld-linux-x86-64.so.2 (GLIBC_2.3) =3D> /lib64/ld-linux-
x86-64.so.2
ld-linux-x86-64.so.2 (GLIBC_2.2.5) =3D> /lib64/ld-linux-
x86-64.so.2
ld-linux-x86-64.so.2 (GLIBC_PRIVATE) =3D> /lib64/ld-
linux-x86-64.so.2
libc.so.6 (GLIBC_2.3.2) =3D> /lib64/libc.so.6
libc.so.6 (GLIBC_PRIVATE) =3D> /lib64/libc.so.6
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
/opt/Xilinx/10.1/EDK/lib/lin64/libstdc++.so.6:
libgcc_s.so.1 (GCC_3.3) =3D> /lib64/libgcc_s.so.1
libgcc_s.so.1 (GCC_3.0) =3D> /lib64/libgcc_s.so.1
libc.so.6 (GLIBC_2.3) =3D> /lib64/libc.so.6
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
/lib64/libm.so.6:
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
/lib64/libgcc_s.so.1:
libc.so.6 (GLIBC_2.4) =3D> /lib64/libc.so.6
libc.so.6 (GLIBC_2.2.5) =3D> /lib64/libc.so.6
/lib64/libc.so.6:
ld-linux-x86-64.so.2 (GLIBC_2.3) =3D> /lib64/ld-linux-
x86-64.so.2
ld-linux-x86-64.so.2 (GLIBC_PRIVATE) =3D> /lib64/ld-
linux-x86-64.so.2
[andyman@xoogle /]$ echo $LD_LIBRARY_PATH
/opt/Xilinx/10.1/EDK/lib/lin64:/opt/Xilinx/10.1/ISE/lib/lin64:/usr/
X11R6/lib:/opt/Xilinx/10.1/ISE/smartmodel/lin64/installed_lin64/lib/
linux.lib:/opt/Xilinx/10.1/ISE/smartmodel/lin64/installed_lin64/lib/
amd64.lib
Article: 140726http://nibz.googlecode.com new vga.vhd download available. Hope it helps you out at about 140 LEs. Any comments welcome. Only supports a 512*256 sub pane, as the logic is easier and has less demands on LEs. It does an indirection and so the colour table only does 2 colours per 16*8 character location. Uses 8 bit data bus. Needs to be combined with a DMA control circuit. Doing an 8*8 character format should be an easy enough conversion. The default divider to get 25MHz pixel clock is from 66.0MHz but is generic and accumulated to 11 bits precision. The indexing down supports character data in high memory if the full 1024 characters are not needed. Now I'll need to make some 16 by 8 characters for a wide font. Or some common character pair compressed font?? cheers jackoArticle: 140727
"BobW" <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote: >How did you identify that these posts are really coming from readnews.com? I did a Google-Groups search on "Usenet Monster spam" and found a discussion on news.admin.net-abuse.usenet, where there were people more knowledgeable about such things than me. >I, too, would love to kill this crap. If readnews is the problem, I will >join in the campaign. The squeaky wheel gets the grease... It's being worked on. The giveaway, apparently, was that they'd done it before and spammed via readnews.com, forging it as from usenetnow.com. http://groups.google.co.uk/group/news.admin.net-abuse.usenet/browse_frm/thread/674d586065a65090 So when the same sort of spam apparently came from Usenet Monster, it didn't take them long to finger the real culprit. http://groups.google.co.uk/group/news.admin.net-abuse.usenet/browse_frm/thread/57ec4d32d0a3a1ae And here's a mea-culpa from a readnews.com admin. http://groups.google.co.uk/group/news.admin.net-abuse.usenet/browse_frm/thread/386228f40b616fd8 -- Dave FarranceArticle: 140728
On Fri, 22 May 2009 14:20:59 -0700 (PDT), jleslie48 <jon@jonathanleslie.com> wrote: >On May 22, 5:26 pm, doug <x...@xx.com> wrote: > >> >> Only FFs have reset. >> > > >that doesn't mean anything to me. maybe I inlcuded too much code in >the snippet, the only part of the code >that is causing the issue I believe is this: > >----------------------------------------------------------------------------------- > type reg_file_type is array (2**W-1 downto 0) of > std_logic_vector(B-1 downto 0); > signal array_reg: reg_file_type; >----------------------------------------------------------------------------------- > > >the error message in question has no issue with the reset. its >complaining about <array_reg> The "warning" is just telling you that it couldn't map your "array" to memory. Doug has said the reason that couldn't be done probably was that you have some code which says: if (reset) array <= 0 or something similar. As "only ffs have reset" this "array" can't be mapped to memory. If you have code like this, remove it, add an initial statement to clear array instead and try again. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140729
Hi If anyone needs it a vga.vhd file is available from http://nibz.googlecode.com It is compact and connects via a BRQ (bus request on this cycle), the clock in is generic and can be anything above 50MHz. Exact multiples of 25MHz eliminate jitter. Has 1024 definable characters of 16*8 pixel size and 2 colours can be used per character cell. It maybe fully bit mapped by writing sequential character codes to the colour cell memory locations, and using the character definition space for the raster bitmap. It has a byte wide interface and uses 6.25MHz bus bandwidth. The low logic count is mainly due to using powers of 2. cheers jackoArticle: 140730
On May 22, 5:55 pm, Muzaffer Kal <k...@dspia.com> wrote: > On Fri, 22 May 2009 14:20:59 -0700 (PDT), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > >On May 22, 5:26 pm, doug <x...@xx.com> wrote: > > >> Only FFs have reset. > > >that doesn't mean anything to me. maybe I inlcuded too much code in > >the snippet, the only part of the code > >that is causing the issue I believe is this: > > >----------------------------------------------------------------------------------- > > type reg_file_type is array (2**W-1 downto 0) of > > std_logic_vector(B-1 downto 0); > > signal array_reg: reg_file_type; > >----------------------------------------------------------------------------------- > > >the error message in question has no issue with the reset. its > >complaining about <array_reg> > > The "warning" is just telling you that it couldn't map your "array" to > memory. Doug has said the reason that couldn't be done probably was > that you have some code which says: > > if (reset) > array <= 0 > > or something similar. As "only ffs have reset" this "array" can't be > mapped to memory. If you have code like this, remove it, add an > initial statement to clear array instead and try again. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Thank you, that makes sense. I'll have to check.Article: 140731
> How interpolate "New sample time is 64MHz / 3.5" to 3.5 to archive clock > Rate of 64MHz ? Hmm... I think you are mixing up two different things: sampling rate and the system clock rate. They don't necessarily have to be the same. Or perhaps you are asking how to produce a read enable signal for reading data out of the FIFO at 64/3.5 MHz rate. Is that what you are asking? It depends on what kind or resources is available in your FPGA. If you had Xilinx DCMs in your disposal you could probably generate such a signal using DCM FX output. /MikhailArticle: 140732
> Here's some config information from my centos install. Perhaps it'll > help you track down where things are going wrong. Unfortunately, everything matches, but the behavior is still unchanged. (Well, not everything matched at first, primarily because of path ordering. But when I source the appropriate ISE and EDK settings64.csh files, I get output identical to yours, if our differing $XILINX paths are accounted for.) I wonder if you would be so kind as to share with me your output for the following commands: ls -alF $XILINX/bin/lin64/xdl ls -alF $XILINX/bin/lin64/unwrapped/xdl openssl dgst -md5 $XILINX/bin/lin64/xdl openssl dgst -md5 $XILINX/bin/lin64/unwrapped/xdl Perhaps an md5 comparison is inappropriate, but I at least suspect our file sizes differ, considering that I'm missing a symbol that you have. My results are as follows: > [xxxx@xxxx tmp_data]$ ls -alF $XILINX/bin/lin64/xdl > -rwxr-xr-x 1 root root 19680 Sep 3 2008 /usr/local/Xilinx/10.1/ISE/bin/lin64/xdl* > [xxxx@xxxx tmp_data]$ ls -alF $XILINX/bin/lin64/unwrapped/xdl > -rwxr-xr-x 1 root root 735976 Sep 3 2008 /usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl* > [xxxx@xxxx tmp_data]$ openssl dgst -md5 $XILINX/bin/lin64/xdl > MD5(/usr/local/Xilinx/10.1/ISE/bin/lin64/xdl)= 91c292eb71b0f3eef63b72cb4f390f8a > [xxxx@xxxx tmp_data]$ openssl dgst -md5 $XILINX/bin/lin64/unwrapped/xdl > MD5(/usr/local/Xilinx/10.1/ISE/bin/lin64/unwrapped/xdl)= 0e649ebc6d2f448bd405af686f279229Article: 140733
Hi Mikhail, I have send you an email ... > Hmm... I think you are mixing up two different things: sampling rate and > the system clock rate. They don't necessarily have to be the same. Or > perhaps you are asking how to produce a read enable signal for reading > data out of the FIFO at 64/3.5 MHz rate. Is that what you are asking? Yes, exactly what I do. > It depends on what kind or resources is available in your FPGA. If you had > Xilinx DCMs in your disposal you could probably generate such a signal > using DCM FX output. There is the possibility to do so without DCM. Please read your emial, I post a PDF. Thanks. Kappa.Article: 140734
"James Harris" <james.harris.1@googlemail.com> wrote in message news:b7987197-158d-4333-8e8f-ce7621292579@s28g2000vbp.googlegroups.com... > On 22 May, 17:53, MadHatt...@myself.com wrote: >> On May 22, 6:47 am, Amal <akhailt...@gmail.com> wrote: >> >> > It is weird that these newsgroups are getting swamped with SPAM >> > recently!? I wonder if Google or whoever takes care of these >> > newsgroups can do a better job of filtering or deleting them? >> >> > -- Amal >> >> We will have peace in the Middle East before Google does anything >> about SPAM. > > Not so. I sent complaints to Google about the spam in > alt.os.development and it appears that they have not just removed the > sending accounts but also deleted the spam posts sent. > > Maybe their responsiveness is a per-newsgroup thing. Encouraged by > their apparent response I have been reporting spams in other groups to > them for the last couple of months. I can't say I've seen any definite > response yet but I've not been checking for specific messages and ids. > > Reporting spam consumes a bit of time but I presume the reason why > some groups are heavily hit with spam is that spammers have been > allowed to get away with it. They tell their friends and before you > know it the spam levels drown out the legitimate posts. > > The delay was about 6 weeks for alt.os.development. It may be worth > many folks reporting spam posts for a while to see if that encourages > a faster response. > > James . I finally got Google Groups to do something about the spam reports I sent them, but slowly enough that it looks like you then needed to wait a month from the time you start reporting each post by a certain spammer to the time you should expect any action, and you should not expect that action to include sending any email back to you. However, most of the spam I've seen for the last few days was not posted through Google Groups, and is from a very active spammer who's been able fake enough of the header lines to lie about just where it was posted. The readnews.com site (a little upsteam from that spammer) seems to be doing much of the work for handling that spammer. Robert MilesArticle: 140735
On May 21, 5:23=A0pm, CMOS <manusha1...@gmail.com> wrote: > On May 21, 9:18=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > > > > > > On Thu, 21 May 2009 09:09:24 -0700 (PDT) > > > CMOS <manusha1...@gmail.com> wrote: > > > On May 21, 3:57=A0pm, ales.gor...@gmail.com wrote: > > > > On May 21, 10:42=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > On May 21, 9:35=A0am, "Antti.Luk...@googlemail.com" > > > > > > <Antti.Luk...@googlemail.com> wrote: > > > > > > On May 21, 7:30=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > On May 21, 12:17=A0am, Tommy Thorn <tommy.th...@gmail.com> > > > > > > > wrote: > > > > > > > > > On May 20, 11:05=A0am, CMOS <manusha1...@gmail.com> wrote: > > > > > > > > > > hi all, > > > > > > > > > im planning to implement barcode scanning using a CMOS > > > > > > > > > sensor. The processing needs to happen inside a FPGA, so > > > > > > > > > im evaluating my options in choosing a > > > > > > > > > propersoftprocessor for the task. these are my > > > > > > > > > requirements. > > > > > > > > > > 1) open source and need to be able to be used in > > > > > > > > > commercial products 2) need to have good documentation > > > > > > > > > and support tools (toolchain, simulators, emulators) > > > > > > > > > 3) robust and stable > > > > > > > > > 4) need to use in an xilinx spartan 3 device with 400K > > > > > > > > > gates. > > > > > > > > > > i know aboutprocessorsOpenRISC 1000, NIOS 2 and LEON 2, > > > > > > > > > but not sure how good they are with regard to my > > > > > > > > > requirements, specially the (2), (3) and (4) above. > > > > > > > > > Please help. > > > > > > > > > > in addition, i like to here about microblaze and its > > > > > > > > > licensing fees structure > > > > > > > > > A few points: > > > > > > > > - Nios II and MicroBlaze aren't open source, but both are > > > > > > > > very good. > > > > > > > > - Is OpenRISC 1000 ok for commercial products? > > > > > > > > - I doubt LEON 2 (and maybe OpenRISC 1000) can fit in "400K > > > > > > > > gates" > > > > > > > > > You could also consider YARI (http://yari.thorn.ws). It's a > > > > > > > > bit weak in the documentation department though but has > > > > > > > > great tools. The hardware debugger still work in progress, > > > > > > > > but YARI has excellent simulation support. > > > > > > > > > Regards, > > > > > > > > Tommy > > > > > > > > thanks tommy. > > > > > > > > why do you think OpenRISC 1000 is not suitable for commercial > > > > > > > projects? > > > > > > > > thanks. > > > > > > > it doesnt fir s3-400 as a starter > > > > > > > Antti > > > > > > hi again, > > > > > > i decided to go with LEON 2 processor, but i could not find a > > > > > download location for it. Can some one point me to a link? > > > > > > thanks > > > > > MicroBlaze is nice and easy to use, but with s3-400 you won't have > > > > much space left. Since the processor could not digest data in real > > > > time, you probably need a frame buffer also, so bigger FPGA is > > > > probably inevitable. > > > > You might consider taking this imaging development kit for a > > > > start:www.optomotive.si > > > > > Cheers, > > > > > Ales > > > > Hi Ales, thanks for the info. I will have a look in to your > > > suggesstion as well. > > > > btw, i have decided to implement all algorithms in a normal PC first > > > to find out processing power requirements. If requirements are too > > > high and algorithms cannot be run inside s3-400 with required timing > > > constraints, the whole project is kind of become useless. > > > > Assuming s3-400 is capable of delivering the throughput, what i need > > > now is a processor (open source LGPL like) that fits inside this > > > device without much of a problem leaving some resources for other > > > stuff like USB core etc. This makes me to remove both OpenRISC and > > > LEON from consideration. What are the potions i have now? > > > > I had a look in to YARI, and niktech, but not sure how much software > > > development support (compilers, debuggers, etc) they have. I have als= o > > > tried MIPS based processor as well. I need your support to chose the > > > best one! > > > > thanks > > > What are you actually looking for the processor to do? =A0If you're > > implementing most of your algorithm in hardware (i.e., the point of an > > FPGA), then you should be able to get by with a fairly minimal > > softcore like a Picoblaze. =A0The tool support is, well at least they'r= e > > there. =A0It's rock stable, free for practically any use in a Xilinx > > chip, and coding in assembly builds character. =A0More to the point, yo= u > > could put several of them in an S3-400 with room to spare. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order > > this is what i thought. > im going to use the processor for all processing without any hardware > signal processing support. Assuming s3-400 is enough, im trying to > find a processor that fit it well. If you are going to use the processor for all processing then there is no point in doing the project if FPGA. But the image processing algorithms like that needed for barcode scanning can be implemented much faster in FPGA with the hardware implementation that is not the software implementation even if it is on the processor inside the FPGA. So I think as Rob said you should consider implementing much of algorithms in hardware not in processor and then have a small processor synthesized in FPGA for remaining tasks. Cheers, bishesh > > Thanks- Hide quoted text - > > - Show quoted text -Article: 140736
On 21 mai, 16:15, Andy <jonesa...@comcast.net> wrote: > Hassen, > > Putting clock (and only clock) in the sensitivity list of a non- > clocked process is pure nonsense when you (attempt to) simulate it. > > Recommending practices that categorically exclude simulation is pure > nonsense. > > Andy right :) heheArticle: 140737
Actually, to be clear, i do not recommand excluding simulation and i don't see where i did. Anyway, when considering simulation, process without sensiticvity list is possible ( talking about syntax ) ! Here we are in a case where normally no sensitivity list is required. no clocked process, nothing ! I have a question for you. will you put a sensitivity list when simulating ??? i won't ! because i need that process just for sequential issues. Now, if we put no signals in the sensitivity list when simulating, why would we put that when synthesising ? XST or other vendor synthesisers should accept such process. XST do but requires but its syntax checker don't accept process with no signals ! I didn't try that with Altera or actel or any other. but i was talking about Xilinx tools , and mentioned that since its a kind of syntax BUG , he can put any signal in the sensitivity list then just don't use it. To summerise, if i had to do that, i would simulate with no sensitivity list : process(). i would then consider putting any signal to calm down XST ! example : process (any_signal) -- any_signal added just for syntax reasons ... This would avoid putting an eventual hundred signals in the sensitivity list ( academic style ). And remember the main concern of Barme2i is time. i don't think he'd be happy with a solution that makes him put 10 lines sensitivity list... Hope you get my point .. Hassen.Article: 140738
<hassen.karray@gmail.com> wrote in message news:2e641a95-6aa1-4fb9-bb9a-> > Here we are in a case where normally no sensitivity list is required. > no clocked process, nothing ! > In your earlier posting you stated The quickest way is to put ur buses in a process, assign them normally with (bus_1 <= bus_2; in your example) then override the "except " pins at the end or the process. bus_2 is a signal (from the original post), therefore bus2 does belong in the sensitivity list. Your claim that there are no signals required in the sensitivity list, or your later nonsense about putting 'clock' into the sensitivity list is off base. bus_1 changes upon changes to bus_2, end of story. > I have a question for you. will you put a sensitivity list when > simulating ??? i won't ! because i need that process just for > sequential issues. > I'll give you the benefit of the doubt that you're not explaining what you really mean correctly. A sensitivity list should be used, and it has absolutely nothing to do with 'simulating' unless by that you're saying you don't care that your simulation model bears any relationship at all to what gets synthesized and implemented. Unless you use wait statements within the process (which can cause synthesizers to reject your code) you won't even be able to successfully compile (for synthesis or simulation). Example of a process with no sensitivity list (not necessarily recommended for designs intended to be synthesized) process begin wait until bus_2'event; bus_1 <= bus2; ... end process; Example of the equivalent but using a sensitivity list (recommended approach...and less typing to boot) process(bus_2) begin bus_1 <= bus2; ... end process; > Now, if we put no signals in the sensitivity list when simulating, why > would we put that when synthesising ? > Because you want to get a working design and you want to have a simulation model that matches the actual implementation. Debugging in a simulation environment is often times much more productive than doing so on hardware. Even if that's not your experience, what you're doing will inhibit you from being able to use a simulator to reliably do any debug. > XST or other vendor synthesisers should accept such process. XST do > but requires but its syntax checker don't accept process with no > signals ! > In the same sentence you're saying that XST does and that it doesn't accept processes with no signals. > I didn't try that with Altera or actel or any other. but i was talking > about Xilinx tools , and mentioned that since its a kind of syntax > BUG , he can put any signal in the sensitivity list then just don't > use it. > The bug is in your understanding of processes coupled with how current synthesis tools incorrectly treat processes. When you have an incomplete sensitivity list (like an empty one), the sensitivity list will generate a warning about this. The reason for the warning is that the synthesis tool is treating the process differently than the VHDL language specification requires it to do (i.e. it is violating the VHDL spec). Another tool, like a simulator, probably wouldn't blatantly violate the language specification. Since the two tools are applying two different interpretations to the same source code input, it is quite likely that the simulation will produce different results than what gets implemented in the synthesized hardware...good luck debugging problems when you intentionally allow the creation of such avoidable issues. Just because you would 'prefer' the language to be defined the way the synthesis tool is using it, doesn't mean that that's the way the language is defined. > To summerise, if i had to do that, i would simulate with no > sensitivity list : process(). > i would then consider putting any signal to calm down XST ! example : > process (any_signal) -- any_signal added just for syntax reasons ... > > This would avoid putting an eventual hundred signals in the > sensitivity list ( academic style ). > Am I to take from the above, that academics don't care whether the simulation model for something does NOT match what that real something does? Because that's exactly what you're doing with your approach. As for the "eventual hundred signals in the sensitivity list", that pretty much says that you don't do a very good job at design in the first place...but help is on the way, VHDL 2008 will allow you to an easy way to properly handle this without listing those hundred signals, and not creating differences between the sim model and reality. > And remember the main concern of Barme2i is time. i don't think he'd > be happy with a solution that makes him put 10 lines sensitivity > list... > One signal in the sensitivity list should not take 10 lines... Kevin JenningsArticle: 140739
I have tried yet another approach - I've reimplemented in VHDL the schematic diagram provided by Xilinx in the following application notes (Figure 4 in both notes): http://www.xilinx.com/support/documentation/application_notes/xapp139.pdf http://www.xilinx.com/support/documentation/application_notes/xapp188.pdf The resulting code is available on alt.sources: http://groups.google.com/group/alt.sources/browse_thread/thread/cdb15a2ac6dc3f1b# ( or look for subject "Example code for reading and writing data via BSCAN_SPARTAN3 with urJTAG and Python" on alt.sources) What's interesting, this code does not use the CAPTURE signal at all. CAPTURE is performed using only the SHIFT and DRCK signals. I hope, that it may be usefull for someone looking for a way to access his/her IP core via JTAG with BSCAN_xxxx component. -- HTH & BR, WojtekArticle: 140740
On May 22, 7:30=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 22 May 2009 11:57:36 +0100, Martin Thompson wrote: > >I noticed whilst delving with FPGA editor into Xilinx devices that > >there is a latch option within the flipflop block - have you ever used > >them? =A0Will synth tools map to them do you know? > > I've always steered clear of latches in FPGAs, for all the > standard reasons. =A0You're right, the slice FFs can be configured > as latches, and ISE uses them correctly - at least, it did with > the simple testcases I tried. =A0And ISE's static timing analysis > seems to handle them correctly, though I confess I haven't done > a really detailed examination of how all that works. > > I'm still reluctant to use latches for mainstream design, > but I guess that just shows I'm boring and unadventurous :-) > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, I have sent another email to you. Didn't you receive it yet? WengArticle: 140741
Ok , You are right guys . Hassen.Article: 140742
Sandro wrote: > > Symon, > bizarre theorem: google give hits => it can be done ;-) > Sandro, I guess it's a language problem, what I hoped to achieve was, rather than having to spend time explaining exactly how a DLL can attenuate jitter, the reader could look it up themselves. I'm sorry I was unable to explain that sufficiently to you. Symon.Article: 140743
luudee wrote: > I am just looking for a convenient way to include those directives > in to the RTL. If convenient means not changing the design, then no. > In my case the MCP is applied to data that travels from one > clock domain to another and is properly "latched" by synchronized > control logic. There are many good and bad uses for MCP ... Even the good ones can bite. -- Mike TreselerArticle: 140744
Weng, If you don't care to share your communications with the users of this group, please do not waste the bandwidth seeing if someone has received your private email. Doing so is no better than the rest of the spam on this group. AndyArticle: 140745
> On the speedbar: > =A0center-click project, > =A0right-click and hold down, speedbar, rescan-project Thanks Mike, but I just don't see the rescan-project option. Here is what I do: open a .vhd file vhdl menu, select speedbar to open up the speedbar window When I right-click, hold down, speedbar: I don't see the rescan- project option. I see a list of options starting with Update, Auto- update, .... Customise, Close, Quit. I don't quite understand your hint "center-click the project file". vhdl menu export project creates a .prj file. But this file doesn't show up in the speed bar? Is this the .prj file you are suggesting I center-click in the speedbar? Cheers AndrewArticle: 140746
luudee wrote: > > In my case the MCP is applied to data that travels from one > clock domain to another and is properly "latched" by synchronized > control logic. There are many good and bad uses for MCP ... Isn't clock domain crossing usually specified as false path not multicycle path. --KimArticle: 140747
Hi I had hard times getting one open source IP core to work with magma synthesis, I wonder if the reason is in the synthesis tool, or possible in really wrong HDL coding, the code snippet is following -------------------- process (Reset_n, Clk) begin if Reset_n = '0' then Rst_r <= '1'; Inst <= (others => '0'); -- Force NOP at reset. DidPause <= "00"; elsif Clk'event and Clk = '1' then Rst_r <= '0'; if DidPause = "00" then DidPause <= Pause; else DidPause <= std_logic_vector(unsigned(DidPause) - 1); end if; if (Pause /= "00" and DidPause = "00") or DidPause(1) = '1' then -- Pause: instruction retained elsif Rst_r = '1' or Inst_Skip = '1' then -- Skip/flush: NOP insertion Inst <= (others => '0'); else Inst <= ROM_Data; end if; end if; end process; --------- this is the original code (opencores AX8 core) this code works OK on 1) simulation 2) Xilinx FPGA 3) Actel FPGA and it works wrong-different when used with Magma synthesis sure the code is maybe not fully correct, nice, i would never write like this, but it works with 3 different type of tools, and fails with the 4th one so question is, is the code "wrong enough" to allow Magma synthesis to generate valid as per VHDL code, that doesnt work? I am guessing the problem for synthesis is that it is not so clear how to implement the empty case, either by using clock enable or feedback mux (to register or hold old value) ah, any change of the sensitivy list did not make any difference for magma the resulting bitstream failed anyway AnttiArticle: 140748
Dear all, I am very interested in the arcchitecture of FPGA of commercial product. But I have the following questions: 1. Is that all logic elements in FPGA are rectangular in shape (e.g. CLB) and why ? 2. Why DSP/ Memory are arranged in column rather than putting together? 3. Why DSP and Memory are rectangular in shape ? 4. Are there special wire connection between DSP or memory ? e.g. bus base connection. Can expert answer my questions ? Thank you very much for your help. Best regards, YuArticle: 140749
yuchiwai@gmail.com <yuchiwai@gmail.com> wrote: > Dear all, > I am very interested in the arcchitecture of FPGA of commercial > product. But I have the following questions: > 1. Is that all logic elements in FPGA are rectangular in shape (e.g. > CLB) and why ? > 2. Why DSP/ Memory are arranged in column rather than putting > together? > 3. Why DSP and Memory are rectangular in shape ? > 4. Are there special wire connection between DSP or memory ? e.g. bus > base connection. > > Can expert answer my questions ? > > Thank you very much for your help. You could try asking your teacher, or maybe some of your classmates.
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