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"wallge" <wallge@gmail.com> wrote in message news:81c40cea-8724-4748-a2d2-ca1f7011cddf@x1g2000prh.googlegroups.com... > If I wanted to have an NTSC composite output, rather than RGB > component VGA style outputs, could I repurpose one of my DACs and use > it for NTSC? Sure. > Do you think this can all be done in the digital domain, and then sent > out of the FPGA to the video DAC at the last step? Sure. It's relatively straightforward to do it in the digital domain. I didn't use an FPGA (this was over thirty years ago) but it's a fun project. > Does anyone have experience with implementing the algorithm to go from > RGB to NTSC/PAL? http://www.bbc.co.uk/rd/pubs/reports/1980s/reports1986.shtml Download RD 1986/2 Colour encoding and decoding techniques for line-locked sample PAL and NTSC television signals. C.K.P. Clarke > Does ITU-R BT.470-7 describe the algorithm in detail? No, just the signal format. > I have not been > able to find this document on the web anywhere, It's a free download from the ITU. http://www.itu.int/rec/R-REC-BT.470-7-200502-I/en Have fun PeteArticle: 141251
> Do you think this can all be done in the digital domain, and then sent > out of the FPGA to the video DAC at the last step? It's just that I > would like to be able to use a single IC to generate VGA outputs as > well as NTSC outputs (although not both at the same time). I did it with an ADV7123, although I only encoded NTSC & PAL S-Video digitally and used an FMS6410 to generate composite color. I used Keith Jack's Video Demystified as a reference. It was pretty straightforward. A phase accumulator driving a 1/4 wave sine/cosine ROM gives you the quadrature subcarrier. Some KCMs for the color space converter and LPFs. Two multipliers. Ended up being about 500 lines of VHDL. Now decoding; that was hard. CurtArticle: 141252
On Fri, 12 Jun 2009 09:10:50 -0700 (PDT), nachumk wrote: >Regarding whether the i = NUM_LOOPS is equal in synthesis to found = >1, I believe they are equal, and I don't understand the claim that >they aren't. I think both would be unrolled NUM_LOOPS time, and once i >= NUM_LOOPS is hit it should build the same logic as found = 1 and >mask out the rest of the unrolled hardware. I absolutely agree that the functionality should be the same, but I'm really not happy about synthesis of any code that modifies a for-loop counter within the body of a loop. The obvious, conservative way to think about synthesis of for-loops is that they should have constant bounds and then should be unrolled. Writing to the loop counter makes it very hard to work out what the unrolling should look like. By the way, VHDL doesn't allow you to do that - the loop counter is treated as a constant within the loop body. However, I do concede that updating the loop counter with an out-of-limit value, if that is the only such update in the loop body, is probably tractable for synthesis. I am not aware of any tools that support it, but I haven't done any kind of survey on that, so there may be some examples out there. >Declaring i as local is a good idea, and I appreciate your comments >about simulation in this regard. I write my code with synthesis in >mind, and therefore the simulation consideration was not accounted I think it's always worth remembering that both Verilog and VHDL are defined and specified as simulation languages. Synthesis can only ever support some subset of the language. I'm very aware that many people learn these languages purely from a synthesis point of view, and I fear that it leads to some unfortunate coding habits and, sometimes, misconceptions about how the language works. >I never though of doing the same thing for generate loops, but I guess >that should be valid in theory. No!!!! it's not!!!!! The point I was trying to make was this: The genvar loop counter in a generate loop REALLY IS A CONSTANT in the loop body. You absolutely cannot write to it. Consequently, a generate loop CAN easily be unrolled for synthesis. Procedural for-loops are, of course, completely general in Verilog simulation but there is no reason to suppose that all of that generality is synthesisable. >My complaint against Xilinx is that their tool doesn't support code >which is LRM valid, That in itself would be a very unfair complaint; synthesis can never support the whole of the language - as you of course are aware. > and instead of stating that XST doesn't support >this type of for loop, as they said regarding the disable keyword, >they claim that it is illegal code. Yes, that's not so good. > I would be happy to have an error >from XST stating that my code is unsupported, but synthesizing my code >wrong which is currently the case is unacceptable. Also agreed. Synthesis has a duty EITHER to create logic that works like the simulation, OR to error out. We all know that there are many cases where synth tools give warnings rather than errors if they create mismatching logic, and some of us are less than ecstatically happy about that, but there is unfortunately rather a lot of historical precedent at work :-( > Their bug cost me > many hours of debugging what turned out to be completely correct code. Sure. It happens. On the other hand, all synthesis tools - XST included - do a lot of difficult stuff right; so at some point we must go with the majority verdict, adopt a conservative coding style and move on. It's still possible to get the job done. > After modifying my code to use a while loop > everything started working correctly. As I mentioned, it would probably be a smart move to go back to using for loops with bypass logic; many synth tools don't support while loops. It's a real shame if they don't support "disable", though. That's often the cleanest way to do it. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141253
nachumk <nachumk@gmail.com> wrote: (snip) > The only thing that interests me regarding this specific code is > whether it is legal according to the Verilog LRM. Xilinx claims that > my above code is illegal, and the old XST synthesizes it wrong, > whereas the new XST doesn't support it outright. I wrote the code up > above on the fly to demonstrate, so I didn't bother declaring some > things or resetting "go". (snip) > I would love to know if the Verilog LRM fully supports my code? I want > Xilinx to fix XST to support it as I believe it should. Much legal verilog is not synthesizable. This is one that I wouldn't expect. -- glenArticle: 141254
wallge <wallge@gmail.com> wrote: < I am looking into putting a triple video DAC (eg ADV7123, ADV7125) < onto an FPGA board that I am building to do VGA component output. < If I wanted to have an NTSC composite output, rather than RGB < component VGA style outputs, could I repurpose one of my DACs and use < it for NTSC? < I know that there are some ICs that will take in bt601/bt656 and turn < it into NTSC/PAL for me, but these will typically not support the < range of VGA output resolutions that I would also like to support. If you make the bit clock a multiple of the subcarrier frequency, it takes much less logic. That trick has been used for many years, including the ever popular CGA board for the IBM PC and the Apple II. < It seems that there are quite a few signal processing stages necessary < for getting from 24-bit RGB to composite NTSC, including: RGB to YUV, < Oversampling, Multi-tap LPFs, < Quadrature subcarrier generation, channel summation. If you don't do the above, but make the ratio of dot clock to subcarrier a simple fraction, only a small sine table is needed. If you use BRAM, you can have fairly large sine tables. It is somewhat harder if you want to generate true I/Q subcarriers for NTSC, but pretty much nobody does that except broadcasters, and pretty much nobody decodes it. Why does this post come on the day that broadcast analog NTSC is gone forever (in the US)? -- glenArticle: 141255
glen herrmannsfeldt wrote: > wallge <wallge@gmail.com> wrote: > < I am looking into putting a triple video DAC (eg ADV7123, ADV7125) > < onto an FPGA board that I am building to do VGA component output. > > < If I wanted to have an NTSC composite output, rather than RGB > < component VGA style outputs, could I repurpose one of my DACs and use > < it for NTSC? <snip> > Why does this post come on the day that broadcast analog NTSC > is gone forever (in the US)? don't know.... maybe it's not for broadcast. Anyway, I just found these eBay items (I am just a customer, not a seller, and the seller is is getting rid of his stock so the prices are event better) 50 pcs. CRYSTAL# CS4955-CQ, SIX 10-BIT DACS NTSC/PAL DG http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=110290947458 (4 available, $89,99 per lot, could be a bit lower) 100 pcs. ANALOG DEVICE# ADV7175KS, DAC VIDEO ENC NTSC 4 http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=110293276171 3 available, $99.99 each, could be half less ? I have not carefully read the datasheets (I'm looking for VGA out) so I'm not sure it fits the exact purpose of the OP but at least it may help make a few prototypes :-) > -- glen yg -- http://ygdes.com / http://yasep.orgArticle: 141256
On Jun 12, 1:16=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > By the way, VHDL doesn't allow you to do that - the loop > counter is treated as a constant within the loop body. Just to reiterate this point, VHDL does that for exactly the reason that modifying the loop variable directly in a for-loop is a bad idea. If you need to modify a loop variable, use a while-loop, not a for- loop. Just beware that many synthesis tools do not allow while-loops because of non-static bounds issues. Furthermore, VHDL automatically declares a new object for the loop index, visible only within that loop. If an already visible object exists with the same name, the loop index "hides" the existing object. This may seem overly restrictive, but it only helps promote good coding practices, particularly when synthesis is involved. Think of it this way; if you could allow synthesis with a modified for- loop variable, what types of modifications would be allowed? Is backing up the index acceptable? How about bumping the index forward? Given the static unrolling of for-loops in synthesis, all of these coding tricks would make synthesis virtually impossible. It is much simpler to just draw the line at not allowing modification of the for- loop index in the first place, which is exactly what VHDL does at the LRM level. How many times has my mother told me; "Just because you can do something, doesn't mean you should." Wow, I never thought I'd quote my mom in an FPGA/HDL forum! AndyArticle: 141257
On Jun 13, 6:55=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > Why does this post come on the day that broadcast analog NTSC > is gone forever (in the US)? Perhaps: a) The USA is only a small market b) New Standards Conversion to NTSC is likely to be a major market c) NTSC/PAL are going to exist in security/automotive cameras for a very long time. -jgArticle: 141258
"LittleAlex" <alex.louie@email.com> wrote in message news:10f21b9c-2f71-4f84-9939-ac03857a7d98@d7g2000prl.googlegroups.com... On Jun 10, 5:28 pm, "zubinkumar" <zubinku...@ufl.edu> wrote: > Hi, > > I wanted to send some data from my computer to the Xilinx ML401 board > using the USB port. My restriction is that I cannot use the MircoBlaze > package to do the USB interfacing. I was using the USB3300 card to connect > the ML401 to the USB port of my computer but I did not get a VID or PID > upon connection. I wanted to know if I need some kind of VHDL code/core > initially running on the ML401 that activates the USB3300 card which will > enumerate the VID and PID and set it up for further operations? Also, is > this type of core or code available online someplace? How much effort/time > will it take to make such a code/core from scratch? > > Thanks. > Zubin. A USB3300 is a PHY. You will need to add the bit-stuffer, serializer/ deserializer, framer, FIFO and host interface. Then you get to write the host and device drivers. Good luck with that, ====== Luck isn't needed, but the USB 2.0 Device core helps. No driver is needed on the PC side if it enumerates as an audio device and you can live with isochronous limitations. Otherwise, it's quite a bit more work to get both sides working.Article: 141259
On Jun 10, 2:01=A0pm, whygee <why...@yg.yg> wrote: > Hello, > > I've been busy lately, trying to understand how to interface asynchronous= SRAMs > (like IDT 71V016, CY7C10xx or other 16-bit wide and fast parts in TSOP-II= ) > > I have found some descriptions of multicycle methods, using FSMs, but thi= s does > not fit my target because my circuits already run at "nominal speed" (8 t= o 15ns > cycles, depending on the SRAM chip). So I attempt to find how SRAM reads = and > writes can be done in one cycle, with a FPGA that can't (or shouldn't) go= faster. > (Yes I use Actel's ProASIC and I'm fine). > > I have found (through the examination of timing diagrams in several datas= heets) > that I can design a stateless async SRAM interface with this behaviour : > > Read : > =A0 on clock's rising edge : > =A0 =A0 =A0latch the address bus's value, > =A0 =A0 =A0Output Enable =3D 1, WriteEnable =3D 1, > =A0 =A0 =A0and keep data bus floating > =A0 after 1/3 of clock cycle : > =A0 =A0 =A0Output Enable =3D 0 > =A0 on next clock rising edge : > =A0 =A0 =A0latch the data bus input. > > Write : > =A0 =A0on clock rising edge : > =A0 =A0 =A0latch addres bus, OE=3D1, WriteEnable=3D1, > =A0 =A0 =A0keep data bus floating > =A0 =A0after 1/3 of clock cycle : > =A0 =A0 =A0 WriteEnable =3D 0 > =A0 =A0after 1/2 clock cycle (falling edge) > =A0 =A0 =A0 latch data output and drive the output buffer > > It's fine for me because it can be done by > correctly wiring latches to the proper control/data/clock signals > and it should work. Now comes the big question : > > How would I generate the 1/3 clock cycle signal ? > > * I don't want to use a 3x clock because the design already > fast and even though the PLL can output 350MHz, I'm not sure > that the logic and routing will follow (so making a 3-state FSM > is eventually possible but not realistic, too uncertain). > A dual-edged FSM with 1,5x clock would be another improbable chimera... > > * I have seen that the PLL can generate a 5ns (max) delayed clock > based on the main clock, so it's fine for 15ns-rated SRAMs > (I could set the delay to 2,6ns for 8ns parts) > but what happens if 20ns or slower SRAMs are to be used ? > (I have 70ns chips for example, but I don't want to make > a FSM just for a few slow parts) > Also, I would like to keep/reserve PLL outputs for other purposes. > > * In all the datasheets I have found, it is implicitly > necessary to have this 1/3 delay : > =A0 =A0- if shorter, there is a driver conflict on the data bus > =A0 =A0 =A0 if the precendent cycle was a read > =A0 =A0 =A0 =A0(data remain present up to about 1/3 of the next clock cyc= le) > =A0 =A0- if longer, the data setup time is not respected and reliability = suffers. > > Any idea ? > And are my assumption valid ? > (for those who have already designed this kind of circuitry) > > yg > --http://ygdes.com/http://yasep.org if you want todo something right, then add APB wrapper to your core then you can integrate it into Actel Smartesign abd use CoreAPBSRAM it maybe will not be the best in terms of performance but you (or better users of the yasep) will be able to use all the IP cores from the actel core offering as they all attach to APB bus AnttiArticle: 141260
On Jun 13, 9:41=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jun 10, 2:01=A0pm, whygee <why...@yg.yg> wrote: > > > > > Hello, > > > I've been busy lately, trying to understand how to interface asynchrono= us SRAMs > > (like IDT 71V016, CY7C10xx or other 16-bit wide and fast parts in TSOP-= II) > > > I have found some descriptions of multicycle methods, using FSMs, but t= his does > > not fit my target because my circuits already run at "nominal speed" (8= to 15ns > > cycles, depending on the SRAM chip). So I attempt to find how SRAM read= s and > > writes can be done in one cycle, with a FPGA that can't (or shouldn't) = go faster. > > (Yes I use Actel's ProASIC and I'm fine). > > > I have found (through the examination of timing diagrams in several dat= asheets) > > that I can design a stateless async SRAM interface with this behaviour = : > > > Read : > > =A0 on clock's rising edge : > > =A0 =A0 =A0latch the address bus's value, > > =A0 =A0 =A0Output Enable =3D 1, WriteEnable =3D 1, > > =A0 =A0 =A0and keep data bus floating > > =A0 after 1/3 of clock cycle : > > =A0 =A0 =A0Output Enable =3D 0 > > =A0 on next clock rising edge : > > =A0 =A0 =A0latch the data bus input. > > > Write : > > =A0 =A0on clock rising edge : > > =A0 =A0 =A0latch addres bus, OE=3D1, WriteEnable=3D1, > > =A0 =A0 =A0keep data bus floating > > =A0 =A0after 1/3 of clock cycle : > > =A0 =A0 =A0 WriteEnable =3D 0 > > =A0 =A0after 1/2 clock cycle (falling edge) > > =A0 =A0 =A0 latch data output and drive the output buffer > > > It's fine for me because it can be done by > > correctly wiring latches to the proper control/data/clock signals > > and it should work. Now comes the big question : > > > How would I generate the 1/3 clock cycle signal ? > > > * I don't want to use a 3x clock because the design already > > fast and even though the PLL can output 350MHz, I'm not sure > > that the logic and routing will follow (so making a 3-state FSM > > is eventually possible but not realistic, too uncertain). > > A dual-edged FSM with 1,5x clock would be another improbable chimera... > > > * I have seen that the PLL can generate a 5ns (max) delayed clock > > based on the main clock, so it's fine for 15ns-rated SRAMs > > (I could set the delay to 2,6ns for 8ns parts) > > but what happens if 20ns or slower SRAMs are to be used ? > > (I have 70ns chips for example, but I don't want to make > > a FSM just for a few slow parts) > > Also, I would like to keep/reserve PLL outputs for other purposes. > > > * In all the datasheets I have found, it is implicitly > > necessary to have this 1/3 delay : > > =A0 =A0- if shorter, there is a driver conflict on the data bus > > =A0 =A0 =A0 if the precendent cycle was a read > > =A0 =A0 =A0 =A0(data remain present up to about 1/3 of the next clock c= ycle) > > =A0 =A0- if longer, the data setup time is not respected and reliabilit= y suffers. > > > Any idea ? > > And are my assumption valid ? > > (for those who have already designed this kind of circuitry) > > > yg > > --http://ygdes.com/http://yasep.org > > if you want todo something right, then add APB wrapper to your core > then you can integrate it into Actel Smartesign abd use CoreAPBSRAM > > it maybe will not be the best in terms of performance but you (or > better > users of the yasep) will be able to use all the IP cores from the > actel > core offering as they all attach to APB bus > > Antti eh taket that all back, i wrote before morning coffee the APBSRAM core only uses internal rams, external SRAM is supported by AHB controller only :( AnttiArticle: 141261
Hello, sorry to disturb you all, but i really need an answer to this
problem..
I have a complex correlation algorithm written in VHDL and the output
of this module is a user defined type
The top level of the correlation module is
COMPONENT MainApplication IS
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
outMainappli : OUT TABLE_TYPE_1_Integerrange4096to4095);
END COMPONENT;
Where
TYPE TABLE_TYPE_1_Integerrange4096to4095 IS ARRAY(1 to 1) of Integer
range -4096 to 4095;
The application works fine and simulation produces the desired
result..
The problem arrives when i am trying to create a wrapper for this
module.. for certain reasons to interface the application with the OPB/
PLB buses, i want to convert my user defined integer array type into a
std_logic_vector..
I tried the following code in my adapter.vhd file, the adapter file
also has access to my userlibrary where the integer type is declared.
SIGNAL Tempresult1 : TABLE_TYPE_1_Integerrange4096to4095;
SIGNAL SignalConcat1 : STD_LOGIC_VECTOR (12 downto 0);
OMPONENT MainApplication IS
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
outMainappli : OUT TABLE_TYPE_1_Integerrange4096to4095);
END COMPONENT;
begin
--USER logic
myapplication : MainApplication
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Reset,
--outMainappli => outtest
outMainappli => Tempresult1
);
toto : process(Bus2IP_Clk) is
begin
SignalConcat1 <= std_logic_vector(conv_signed((Tempresult1),13));
myport <= SignalConcat1;
end process toto;
I get the following errors :
ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/
pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176.
conv_signed can not have such operands in this context.
I know that this is a syntax error.. i tried to change the code, but
then i got the same error..
I really need help for this .. my work is being blocked due to this..
and no, i cannot change the output type of my application..
Any help will be greatly appreciated..
Article: 141262Antti.Lukats@googlemail.com wrote: > On Jun 13, 9:41 am, "Antti.Luk...@googlemail.com" wrote: >> if you want todo something right, then add APB wrapper to your core >> then you can integrate it into Actel Smartesign abd use CoreAPBSRAM >> it maybe will not be the best in terms of performance but you (or >> better users of the yasep) will be able to use all the IP cores from the >> actel core offering as they all attach to APB bus >> >> Antti > > eh taket that all back, i wrote before morning coffee heh :-) me... neeed... chocolate.... > the APBSRAM core only uses internal rams, external > SRAM is supported by AHB controller only :( In fact I never looked at the APB or AHB. I remember some basics of the VCI, but in a microcontroller where the core's timing is tied to the SRAM's, performance also matters... At 64MHz, it's going to give about 16 MIPS, add a "generic memory interface" and it could drop to 10 or 5 MIPS : where's the point of using 15ns SRAMs ? Yes, I know, I'm a speed freak :-/ anyway, thanks for mentioning the AxB things, > Antti yg -- http://ygdes.com / http://yasep.orgArticle: 141263
On Sat, 13 Jun 2009 07:57:42 -0700 (PDT), iquadri wrote: > begin > SignalConcat1 <= std_logic_vector(conv_signed((Tempresult1),13)); > myport <= SignalConcat1; > end process toto; > > >I get the following errors : > >ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/ >pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176. >conv_signed can not have such operands in this context. Well, it looks more-or-less OK... You haven't told us the one really important piece of information: which packages did you "use" at the top of this entity? A typical problem might be that you have use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; and so you have conflicting definitions of conv_signed? It would be easier if you try to be A Good Person (tm): library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ... SignalConcat1 <= std_logic_vector(to_signed((Tempresult1),13)); -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141264
On Sat, 13 Jun 2009 21:03:16 +0100, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >On Sat, 13 Jun 2009 07:57:42 -0700 (PDT), iquadri wrote: >>ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/ >>pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176. >>conv_signed can not have such operands in this context. > >Well, it looks more-or-less OK... You haven't told us >the one really important piece of information: which >packages did you "use" at the top of this entity? >A typical problem might be that you have > > use ieee.std_logic_signed.all; > use ieee.std_logic_arith.all; > >and so you have conflicting definitions of conv_signed? > >It would be easier if you try to be A Good Person (tm): > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > ... > SignalConcat1 <= std_logic_vector(to_signed((Tempresult1),13)); Definitely the best library and the best approach, but given the declarations TYPE TABLE_TYPE_1_Integerrange4096to4095 IS ARRAY(1 to 1) of Integer range -4096 to 4095; and SIGNAL Tempresult1 : TABLE_TYPE_1_Integerrange4096to4095; SIGNAL SignalConcat1 : STD_LOGIC_VECTOR (12 downto 0); don't you need to extract the integer from the single element array? SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),13)); Incidentally, even though I'm a big fan of strong typing, I don't like this type name strategy; it just adds clutter as well as being incredibly fragile; if you later decide you need another bit of resolution you have a maintenance nightmare. What is the real intent of this (array containing a single)13 bit signed integer? e.g. if it is the right resolution for your raw input data, then TYPE Raw_Data IS Integer range -4096 to 4095; TYPE Raw_Data_Table IS ARRAY(1 to 1) of Raw_Data; might be more suitable. Or since you need a matching STD_LOGIC_VECTOR... subtype Raw_Word is STD_LOGIC_VECTOR (12 downto 0); TYPE Raw_Data IS Integer range (-2**Raw_Word'high) to (2**Raw_Word'high - 1); TYPE Raw_Data_Table IS ARRAY(1 to 1) of Raw_Data; ... SIGNAL SignalConcat1 : Raw_Word; SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),Raw_Word'length)); Now you can see at a glance what the intent of a signal is: raw data, processed but unrounded; processed and rounded etc, rather than having to translate back from integer ranges to design intent. And if your next board has a 14-bit ADC you only need to change the type declaration (especially after appropriate use of 'length as above); you don't have to edit every usage of it - or worse - live with misleading names which no longer reflect the actual data size! You may also consider using numeric_std.signed instead of both Integer and STD_LOGIC_VECTOR in this example; then the type conversions disappear. They may pop up elsewhere; but if you are _using_ the type system instead of fighting it, they will be few and far between. Mixing Integer and Signed (or subtypes of these) is pretty painless, and Integer is usually faster in simulation. (You may need to constrain its range, as you did, for fast compact synthesis results) - BrianArticle: 141265
On Sun, 14 Jun 2009 01:36:04 +0100, Brian Drummond wrote: >don't you need to extract the integer from the single element array? > >SignalConcat1 <= std_logic_vector(to_signed((Tempresult1(1)),13)); duh, yes. Too much haste AGAIN, sorry. <hangs head in shame> -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141266
On Jun 13, 10:03=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 13 Jun 2009 07:57:42 -0700 (PDT), iquadri wrote: > > begin > > =A0 =A0SignalConcat1 <=3D std_logic_vector(conv_signed((Tempresult1),13= )); > > =A0 =A0 myport <=3D SignalConcat1; > > end process toto; > > >I get =A0the following errors : > > >ERROR:HDLParsers:808 - "C:/QDev/FIRFilterPDR/edk_ip/MyProcessorIPLib/ > >pcores/firfilter_v1_01_a/hdl/vhdl/user_logic.vhd" Line 176. > >conv_signed can not have such operands in this context. > > Well, it looks more-or-less OK... =A0You haven't told us > the one really important piece of information: which > packages did you "use" at the top of this entity? > A typical problem might be that you have > > =A0 use ieee.std_logic_signed.all; > =A0 use ieee.std_logic_arith.all; > > and so you have conflicting definitions of conv_signed? > > It would be easier if you try to be A Good Person (tm): > > =A0 library ieee; > =A0 use ieee.std_logic_1164.all; > =A0 use ieee.numeric_std.all; > =A0 ... > =A0 SignalConcat1 <=3D std_logic_vector(to_signed((Tempresult1),13)); > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Thanks guys, it worked ..Article: 141267
On Jun 12, 9:48=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > nachumk <nach...@gmail.com> wrote: > > (snip) > > > The only thing that interests me regarding this specific code is > > whether it is legal according to the Verilog LRM. Xilinx claims that > > my above code is illegal, and the old XST synthesizes it wrong, > > whereas the new XST doesn't support it outright. I wrote the code up > > above on the fly to demonstrate, so I didn't bother declaring some > > things or resetting "go". > > (snip) > > > I would love to know if the Verilog LRM fully supports my code? I want > > Xilinx to fix XST to support it as I believe it should. > > Much legal verilog is not synthesizable. =A0This is one that I > wouldn't expect. =A0 > > -- glen I have now had a chance to check the recommended workaround of using a found variable instead of i =3D NUM_LOOPS. The found variable version is correctly synthesized with XST. Thank you for all the feedback, Nachum Kanovsky http://www.linkedin.com/in/nachumkanovsky http://ionipti.blogspot.com/Article: 141268
Hi, I recently read Altera Stratix II, III and IV device handbook and found its 3-bit addition circuit is really a genius invention. But I was surprised to find that Altera patent application "Logic Cell Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has not been approved to be a patent so far today, even though many Altera later patent applications based on the invention have been approved for U.S. patents. Is anyone knowledgable about the patent application willing to transfer the patent application context to me and disclose why it hasn't been approved as a U.S. patent. My guess is it may never be approved by U.S. Patent Office to be a patent, the reason is not its novelty violation, but its context didn't disclose enough information about the 3-bit addition circuit, a requirement for any patent application to be approved to be a U.S. patent. At least those skilled in the art cannot get the idea what is done within its circuit having an encircled '+' with 3 inputs and 2 outputs. Altera another sister patent application "Arithmetic Structure is for Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. Thank you. WengArticle: 141269
hm at least according to the publication http://portal.acm.org/citation.cfm?id=1344671.1344729&coll=GUIDE&dl=GUIDE&CFID=39563246&CFTOKEN=12028185 there is working decompiler that create netlist from s3,v2,v4.v5 bitstreams! AnttiArticle: 141270
The publication and the tools are available at ulogic.org can't say if it works, my FX20 is currently not supported and i had no time to look into that... h.e. Antti schrieb: > hm > at least according to the publication > > http://portal.acm.org/citation.cfm?id=1344671.1344729&coll=GUIDE&dl=GUIDE&CFID=39563246&CFTOKEN=12028185 > > there is working decompiler that create netlist from s3,v2,v4.v5 > bitstreams! > > AnttiArticle: 141271
On Jun 15, 12:29=A0pm, "h.e." <h...@thisisnovalidaddress.net> wrote: > The publication and the tools are available at ulogic.org > can't say if it works, my FX20 is currently not supported and i had no > time to look into that... > > h.e. > > Antti schrieb: > > > hm > > at least according to the publication > > >http://portal.acm.org/citation.cfm?id=3D1344671.1344729&coll=3DGUIDE&dl= =3DG... > > > there is working decompiler that create netlist from s3,v2,v4.v5 > > bitstreams! > > > Antti right I assumed debit is dead and vanished, but discovered ulogic website is still online :) sometimes i am slow... when i did read the publication i did not think it is about debit tools the article looked so PRO while the status of debit wasnt so when i last looked at it sure the authors name sounded familiar :) but i really could not join the article to debit my mistake AnttiArticle: 141272
On Jun 14, 1:21=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I recently read Altera Stratix II, III and IV device handbook and > found its 3-bit addition circuit is really a genius invention. But I > was surprised to find that Altera patent application "Logic Cell > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > not been approved to be a patent so far today, even though many Altera > later patent applications based on the invention have been approved > for U.S. patents. > > Is anyone knowledgable about the patent application willing to > transfer the patent application context to me and disclose why it > hasn't been approved as a U.S. patent. > > My guess is it may never be approved by U.S. Patent Office to be a > patent, the reason is not its novelty violation, but its context > didn't disclose enough information about the 3-bit addition circuit, a > requirement for any patent application to be approved to be a U.S. > patent. At least those skilled in the art cannot get the idea what is > done within its circuit having an encircled '+' with 3 inputs and 2 > outputs. > > Altera another sister patent application "Arithmetic Structure is for > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > Thank you. > > Weng I don't know why Altera wouldn't disclose info on the structure being used in a device. It is relatively inexpensive to reverse engineer a chip, so if it is not disclosed in a patent, it is not protected and is vulnerable to being copied. What exactly *does* the patent claim? Maybe the design inside the circled + is not really novel and only the design around the circle is novel enough to be patented? In general, I think a three in put adder is *very useful*. I've never seen such a circuit, I guess the carry chain has multiple bits, eh? RickArticle: 141273
I am using Virtex4 FPGA. I have 32 bit data packets running at 200MHz and would like to convet that into 64 bit data packets running at 100MHz. This is not at the FPGA I/O but needs to be done inside the FPGA fabric. I have done this conversion myself in verilog but I just wanted to see how you all do this. Here is how I have done it (1) I used PMCD to divide the 200MHz clock by 2 (100MHz). I am assuming that the 200MHz and 100MHz clocks are completely phase aligned. (2) Latch the 32 bit packets on both positive and negative edges of the clocks. This give me 64 bits of data but it is not phase aligned to one another. (3) Latch the 64 bits of data on posedge of 100MHz clock (4) If the first valid data after reset started out on the posedge of the 100MHz clock then latch the data again at posedge of 100MHz clock and use it. At this point the data is posedge aligned to 100MHz clock (5) If the first valid data after reset stated out on the negedge of the 100MHz clock then on posedge of 100MHz clock, latch the upper 32 bits from step2 and lower 32 bits from step3. This will give the posedge aligned 64 bits of data. There are other sideband signal that go with this also. I am trying to use the same scheme but I am not sure if this can run into timing isues in Virtex4 FPGA. There is not much decoding needed to do thus it helps from that standpoint. But main concern I have is that I am latching the data on neg edge of 100MHz clock and then latching the same data on posedge of 100MHz clock. I am not sure if there is any timing concerns if I do not have much combinatorial logic in the path. Your opinions will be very helpful to me. Thanks. cpArticle: 141274
On Jun 15, 4:36=A0am, rickman <gnu...@gmail.com> wrote: > On Jun 14, 1:21=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > I recently read Altera Stratix II, III and IV device handbook and > > found its 3-bit addition circuit is really a genius invention. But I > > was surprised to find that Altera patent application "Logic Cell > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has > > not been approved to be a patent so far today, even though many Altera > > later patent applications based on the invention have been approved > > for U.S. patents. > > > Is anyone knowledgable about the patent application willing to > > transfer the patent application context to me and disclose why it > > hasn't been approved as a U.S. patent. > > > My guess is it may never be approved by U.S. Patent Office to be a > > patent, the reason is not its novelty violation, but its context > > didn't disclose enough information about the 3-bit addition circuit, a > > requirement for any patent application to be approved to be a U.S. > > patent. At least those skilled in the art cannot get the idea what is > > done within its circuit having an encircled '+' with 3 inputs and 2 > > outputs. > > > Altera another sister patent application "Arithmetic Structure is for > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate. > > > Thank you. > > > Weng > > I don't know why Altera wouldn't disclose info on the structure being > used in a device. =A0It is relatively inexpensive to reverse engineer a > chip, so if it is not disclosed in a patent, it is not protected and > is vulnerable to being copied. > > What exactly *does* the patent claim? =A0Maybe the design inside the > circled + is not really novel and only the design around the circle is > novel enough to be patented? > > In general, I think a three in put adder is *very useful*. =A0I've never > seen such a circuit, I guess the carry chain has multiple bits, eh? > > Rick- Hide quoted text - > > - Show quoted text - Hi Rick, Here is a link to Stratix IV Device Handbook Volumn 1 and page 43 shows the invention circuit: http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it describes two applications: multiplication and correlation function. Any other applications? With multiplier hardware structure specially introduced in FPGA, is multiplication circuit still used for multiplication? Weng
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