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Symon wrote: >> The sort of thing that if it was C software, you'd do it easily with >> #includes, #defines and >> #ifdefs, but for reasons I can't understand, VHDL doesn't have anything >> like these simple >> preprocessor functions. >> Although HDLs are very different from programming languages, a >> preprocessor would be equally useful >> & it seems ridiculous that nobody thought to include one in the standard. >> A number of people explained how to use the VHDL's native constructs. >> Is there a simple way to 'add' a C style preprocessor to the build >> process? > Yes. Use a "C" pre-processor. I didn't try it myself in part because I don't use VHDL and Verilog has "`include", "`define", etc. A lot of people use cpp to pre-process for example assembly sources. Why not VHDL? It should handle the #includes, #defines, etc. and leave the rest intact. -Alex.Article: 141976
AR32929 " Description Keywords: Virtex-6, issues, LXT, SXT, FXT, CXT " i would assume 6FXT has some hard processor core? or is it all typos in Xilinx web? AnttiArticle: 141977
Hi, i have downloaded WebPack 10.1 for Linux, and have it installed. But, I can't seem to find the isim function. It shows a process for Modelsim, but Modelsim is not provided for Linux hosts. I am specifically wanting to use 10.1, as it supports Coolrunner 2 and Spartan 2E, which I still use. Anybody know what I'm doing wrong? (This is a 32-bit X86 system.) Is isim really missing, do you have to install it separately, or is it just that I can't find the right button to bring it up? Any hints gratefully appreciated. JonArticle: 141978
On Jul 16, 7:24=A0pm, rickman <gnu...@gmail.com> wrote: > What do the rest of you prefer? =A0Do you have both? =A0Do you still need > to rely on your books or do you pretty well have the language down > pat? > Rick Google. :-) I have the Ashenden book on my desk, but I rarely look at it. 95% of the time I'll look in source code for other projects I've worked on. The other 5% of the time I'll find it on Google.Article: 141979
"Jon Elson" <jmelson@wustl.edu> wrote in message news:OPWdnfbIUPPzZPnXnZ2dnUVZ_vKdnZ2d@giganews.com... > Hi, > > i have downloaded WebPack 10.1 for Linux, and have it installed. But, I > can't seem to find the isim function. It shows a process for Modelsim, > but Modelsim is not provided for Linux hosts. I am specifically wanting > to use 10.1, as it supports Coolrunner 2 and Spartan 2E, which I still > use. Anybody know what I'm doing wrong? (This is a 32-bit X86 system.) > Is isim really missing, do you have to install it separately, or is it > just that I can't find the right button to bring it up? > > Any hints gratefully appreciated. You really should read the getting started guides, Jon. Just this once: select ISIM as the simulator in the project options. In the drop down list above the project files, select pre- or post-synthesis simulation. Select the simulation top module in the project modules list. Select simulate.Article: 141980
On Jul 20, 4:23=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > AR32929 > > " > Description > > Keywords: Virtex-6, issues, LXT, SXT, FXT, CXT > " > > i would assume 6FXT has some hard processor core? > > or is it all typos in Xilinx web? > > Antti Hi Antti, It is a typo. There is no FXT for the Virtex-6 family. Thanks DuthArticle: 141981
On Jul 20, 10:38=A0am, Charles Gardiner <inva...@invalid.invalid> wrote: > Mike Harrison schrieb: > > > I'm doing a project in Lattice ISPLever ( which bears uncanny similarit= ies to Xilinx ISE), which may > > end up having several product variants, and was wondering how people ty= pically handle compile-time > > build variants for different product functionalities? > > Hi Mike, > > I have had to do this in a number of situations. Typical case: if I do a > PCIe design for a customer, I evaluate on the the Lattice PCIe Demo > board (ECP2M/50) but the customer often uses a different device > (ECP2M/20 or ECP2M/35) > > I haven't found a way of assigning top-level generics at synthesis time > in ispLever (I'm not saying there isn't a way). I have gotten that to work, but only with integers. It definitely does not work with enumerated and I don't recall if it will work with SLV and I know I haven't tried that. The nice thing about doing at the top is that you don't need to edit any files if you are using configuration control. > So I do all the > configuration one level below. Each 'variant' has it's own top-level > entity and architecture, everything else is common. I generate the > project files (*.syn) under Linux (java script) so it's very easy to > keep them all in sync if I change the structure a bit during > development. Essentially, the *.syn files differ only in the package > chosen and in the files read in as top-level entity/architecture. I put > the pinning as 'LOC' attributes in the top-level entity btw. > > The top-level entity/architecture has all busses split into single > signals and takes care of any polarity inversion for active-low signals, > enables for bidirectionals etc. The only module instanced in the > top-level architecture is my 'core' unit. It is essentially the same as > the top-level unit except: > > - input / output polarity is always active high (makes viewing of > simulation traces easier - if it's true it's a one) > > - no bidirectional ports > > - busses are declared as std_logic_vector, occasionally as records > > - contains generic ports passed into the design below. I use these to > configure things like FIFO sizes, no. of DMA channels, whatever > > If needed, I have a separate constraint file for each variant. Each > variant has it's own script sub-directory (if there are differences). To > synthesise, I just copy the project (*.syn), constaint (*.lpf), ispVM > (*.xcf) and possibly environment (*.sty) into my ispLever work directory > and let it run. Works a treat.Article: 141982
On Jul 20, 4:51=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > I'm doing a project in Lattice ISPLever ( which bears uncanny similaritie= s to Xilinx ISE), which may > end up having several product variants, and was wondering how people typi= cally handle compile-time > build variants for different product functionalities? > > The sort of thing that if it was C software, you'd do it easily with #inc= ludes, #defines and > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything l= ike these simple > preprocessor functions. > Although HDLs are very different from programming languages, a preprocess= or would be equally useful > & it seems ridiculous that nobody thought to include one in the standard. > > Is there a simple way to 'add' a C style preprocessor to the build proces= s? You should also look up GENERATE. That is how to do actual code "defines". GENERICS only get you parameters. RickArticle: 141983
MikeWhy wrote: >> Any hints gratefully appreciated. > > You really should read the getting started guides, Jon. Just this once: > select ISIM as the simulator in the project options. In the drop down > list above the project files, select pre- or post-synthesis simulation. > Select the simulation top module in the project modules list. Select > simulate. > > I really DID try to find it in the getting started guide, but I couldn't find this important tidbit! Thanks much for the help. I've been using Ise 4.2i from the dark ages, and have just moved up to a more modern version. I couldn't find anywhere where they mention making that setting in the project options. It SHOULDN'T default to ModelSim, or even allow you to make that setting, as that sim is NOT supported on Linux! So thanks very much, I can now do sim! JonArticle: 141984
On Jul 20, 9:22=A0pm, rickman <gnu...@gmail.com> wrote: > On Jul 20, 4:51=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > > > I'm doing a project in Lattice ISPLever ( which bears uncanny similarit= ies to Xilinx ISE), which may > > end up having several product variants, and was wondering how people ty= pically handle compile-time > > build variants for different product functionalities? > > > The sort of thing that if it was C software, you'd do it easily with #i= ncludes, #defines and > > #ifdefs, but for reasons I can't understand, VHDL doesn't have anything= like these simple > > preprocessor functions. > > Although HDLs are very different from programming languages, a preproce= ssor would be equally useful > > & it seems ridiculous that nobody thought to include one in the standar= d. > > > Is there a simple way to 'add' a C style preprocessor to the build proc= ess? > > You should also look up GENERATE. =A0That is how to do actual code > "defines". =A0GENERICS only get you parameters. > > Rick I may have mixed up DEFINE and something else. It has been awhile since it did C coding. GENERATE allows you to conditionally include sections of code, not just set values in contstants. GENERATE also lets you iterate on code to build multiple instances, etc. RickArticle: 141985
Unfortunately it is illegal (still) in 2008 revision. Jim SynthWorks VHDL TrainingArticle: 141986
> > FYI I've just been playing with the FT2232H for outputting from the PC to an FPGA, and this will > sustain 20MBytes/second one-way. > This is in parallel sync mode - the async modes are constrained by the async bus timing. That does sound very useful. Unfortunately I'm working on a dev board that has an RJ45 port and a PHY, so I am just writing a very simple UDP packet sender to test it all out. Bit of a hack way, but this is just for testing the FPGA image processing, the final board will have a PCI bridge to a processor, so a UDP approach should suffice for nowArticle: 141987
Charles Gardiner wrote: > So I do all the > configuration one level below. Each 'variant' has it's own top-level > entity and architecture, everything else is common. (snip) > The only module instanced in the > top-level architecture is my 'core' unit. This is _exactly_ what I did for a project that we prototyped on an eval board, and then migrated to the real hardware once it was developed. I also have a whole suite of "hobby" projects that have been ported to several different physical boards. Each "target" (PCB) has its own top-level and that instantiates the core plus a few target-specific modules for handle I/O, SDRAM, sound etc. I've also introduced a set of packages that are specific to each target(PCB), so-called platform (emulated hardware) and so-called project (software running on that hardware). It's a bit of a chore to setup for the 1st time, but it makes it _very_ easy to port projects that conform to the architecture between targets (PCBs). Less "wholesale" differences like minor build options are handled by either generics in the top-level or core modules, or alternatively in via constants in a global package. Then I use if-generate in the code. FWIW to prevent "debug" options from inadvertently creeping into production builds, I generally have a "DEBUG_BUILD" constant defined, and all (debug) build options are defined as "BUILD_OPT_X := DEBUG_BUILD and true/false". I've seriously considered using a C pre-processor for VHDL in the past. The really annoying thing is that if-generate code is always parsed, regardless if it's included or not, so you can't use it to exclude obsolete/experimental/irrelevant code without it passing elaboration for example. And if you instantiate an entity without a component declaration, then it needs to be compiled into the work library - ughh! Purists (KJ?) will of course proclaim that you shouldn't need to do such things, and that a pre-processor is entirely unnecessary. OTOH my colleague describes my coding style as "pack-rat" because I'm loathe to actually delete lines of code. Regardless, IMHO VHDL would only benefit (greatly) from such directives. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 141988
On Jul 19, 4:12=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > http://groups.google.com/group/antti-brain?hl=3Den > > uploaded ready to test bit file for spartan3a kit > (need put small wire into SMA for antenna) > > Antti ____________________________________________ hi, may i get source code of this as i want to download it to spartan2 .. and some material to study .so that i can do project on this. plz do the needful.. regards udayArticle: 141989
JimLewis wrote: > Unfortunately it is illegal (still) in 2008 revision. And can anyone explain to me - why???? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 141990
On Jul 18, 3:50=A0am, AndreasWallner <Andreas.Wallner.et...@fh- joanneum.at> wrote: > On Jul 15, 1:04=A0pm, Fridolin <googlegro...@47110815.com> wrote: > > > > > On Jul 14, 10:46=A0pm, AndreasWallner <Andreas.Wallner.et...@fh- > > > joanneum.at> wrote: > > > Hi, > > > > I have a Problem getting the System ACE Controller to work. > > > I try it on a Spartan 3A DSP 1800 Board, to which I connected a > > > SystemACE Module from AVNet. > > > > If I format the CF Card completly, and do not create any partitions > > > (the drive then only contains the FAT16). > > > > If I try to create two partitions (with linux fdisk, one 64MB > > > Partition, and the second spanning the remaining card), format the > > > first one to FAT16 and copy the exact same files to the card the > > > System ACE board only displays an error and does not load the design. > > > > Are there any special points to take into consideration? > > > > Regards, > > > Andreas > > > Hi Andreas, > > > look onhttp://www.xilinx.com/products/boards/ml403/reference_designs.ht= m > > near the end of the page there is a image for the CF card with a DOS > > and Linux partition. > > (CF Card Image (DOS and Linux Partition)) > > You can download it and view it with a Disk Editor or Uedit in binary > > mode. > > > Maybe you find the diffs to the Linux fdisk tool. > > > Have Fun > > Florian > > Hi, > > I analysed the partition table of both, my self created and the one in > the image. The rest of the MBR also looked fine (as fine as a > bootloader which is not there can look ;-) ) > After not finding a difference (except the size-dependent parts) I > copied the partition table from the image onto my CF card, formatted > the first partition, and tried that one out. It also did not work. So > I tried only creating one partition, which also did not work... > > The commands I'm using: > mkdosfs -F 16 -R 1 -I /dev/sdc (for the whole disk) > mkdosfs -F 16 -R 1 /dev/sdc1 (for the partition) > > If I create the partition table I use linux fdisk, and change the type > of the partition to 0x06. > > I also tried axplicitly specifying different sector-per-cluster sizes, > which also did not change anything. (sector-per-cluster size /=3D 1) > -> mkdosfs -F 16 -R 1 -s 4 > > Using dd (which is btw. also available for windows) I wrote the image > Fridolin mentioned to the CF card. Then I deleted all files from the > card and copied my design onto it. This time it worked, it's a way to > start, but I really don't think it's a way to do it all the time... > > Tomorrow I will try out wheter my VHDL implementation for the MPU bus > works or not, if it does I will tell you the current values of the > status/error/fatstat registers. But it would be really great if you > could tell me how you partition/format you CF card (linux would be > fine, but I would also be grateful for a windows way) > > Thanks > Andreas Hi Andreas, my costumer wrote some scripts. The partition table is copied with dd.exe. There is only one partition foe FAT16. Then they call mkdosfs without any parameter (except drive letter of course). That's all. Why do you call "mkdosfs -F 16 -R 1 -I /dev/sdc (for the whole disk)" ? May be it overwrite the partition table. I think you have to format only the /dev/sdc1. I hope this will help you. Have fun FlorianArticle: 141991
On Jul 21, 10:51=A0am, Fridolin <googlegro...@47110815.com> wrote: > On Jul 18, 3:50=A0am, AndreasWallner <Andreas.Wallner.et...@fh- > > > > joanneum.at> wrote: > > On Jul 15, 1:04=A0pm, Fridolin <googlegro...@47110815.com> wrote: > > > > On Jul 14, 10:46=A0pm, AndreasWallner <Andreas.Wallner.et...@fh- > > > > joanneum.at> wrote: > > > > Hi, > > > > > I have a Problem getting the System ACE Controller to work. > > > > I try it on a Spartan 3A DSP 1800 Board, to which I connected a > > > > SystemACE Module from AVNet. > > > > > If I format the CF Card completly, and do not create any partitions > > > > (the drive then only contains the FAT16). > > > > > If I try to create two partitions (with linux fdisk, one 64MB > > > > Partition, and the second spanning the remaining card), format the > > > > first one to FAT16 and copy the exact same files to the card the > > > > System ACE board only displays an error and does not load the desig= n. > > > > > Are there any special points to take into consideration? > > > > > Regards, > > > > Andreas > > > > Hi Andreas, > > > > look onhttp://www.xilinx.com/products/boards/ml403/reference_designs.= htm > > > near the end of the page there is a image for the CF card with a DOS > > > and Linux partition. > > > (CF Card Image (DOS and Linux Partition)) > > > You can download it and view it with a Disk Editor or Uedit in binary > > > mode. > > > > Maybe you find the diffs to the Linux fdisk tool. > > > > Have Fun > > > Florian > > > Hi, > > > I analysed the partition table of both, my self created and the one in > > the image. The rest of the MBR also looked fine (as fine as a > > bootloader which is not there can look ;-) ) > > After not finding a difference (except the size-dependent parts) I > > copied the partition table from the image onto my CF card, formatted > > the first partition, and tried that one out. It also did not work. So > > I tried only creating one partition, which also did not work... > > > The commands I'm using: > > mkdosfs -F 16 -R 1 -I /dev/sdc (for the whole disk) > > mkdosfs -F 16 -R 1 /dev/sdc1 (for the partition) > > > If I create the partition table I use linux fdisk, and change the type > > of the partition to 0x06. > > > I also tried axplicitly specifying different sector-per-cluster sizes, > > which also did not change anything. (sector-per-cluster size /=3D 1) > > -> mkdosfs -F 16 -R 1 -s 4 > > > Using dd (which is btw. also available for windows) I wrote the image > > Fridolin mentioned to the CF card. Then I deleted all files from the > > card and copied my design onto it. This time it worked, it's a way to > > start, but I really don't think it's a way to do it all the time... > > > Tomorrow I will try out wheter my VHDL implementation for the MPU bus > > works or not, if it does I will tell you the current values of the > > status/error/fatstat registers. But it would be really great if you > > could tell me how you partition/format you CF card (linux would be > > fine, but I would also be grateful for a windows way) > > > Thanks > > Andreas > > Hi Andreas, > > my costumer wrote some scripts. > > The partition table is copied with dd.exe. > There is only one partition foe FAT16. > Then they call mkdosfs without any parameter (except drive letter of > course). > That's all. > > Why do you call "mkdosfs -F 16 -R 1 -I /dev/sdc (for the whole > disk)" ? > May be it overwrite the partition table. I think you have to format > only the /dev/sdc1. > > I hope this will help you. > Have fun > Florian What version of mkdosfs do you use? FlorianArticle: 141992
On Mon, 20 Jul 2009 11:36:00 -0700 (PDT), luudee wrote: >Sounds like a timing problem. Intermediate failures are usually >timing related. Absolutely. >Where is the clock coming from, the DSP ? Do you cancel out the >clock buffer delay before you use it for the LED register ? Painful recollections of a recent customer project which had a clocked external interface - nothing too fast, about 40MHz or so - output from FPGA, fed into the streaming data interface of some microcontroller. Something hard-to-fathom was going wrong. We scratched heads, fooled around with timing constraints in a desperate effort to get the clock edges (at the FPGA registers) exactly lined up with the centre of the data window. Static timing analysis and oscilloscope measurements both said we had it just right.... and the nearer we got to "just right", the less reliable the data transfer. Angry project managers, much consumption of coffee and discussion. Finally I gave up in disgust and - after a struggle - got a copy of the microcontroller software from the programmer folk. The micro's interface control registers had been set up for falling-edge clocking of the interface, but all the specifications said rising-edge. So the closer I got to centre-aligning the clock rise in the data window, the worse the timing became! Just one bit wrong in one *&&^% control register. Just because one programmer couldn't read a spec. Grrr. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141993
luudee wrote: > On Jul 20, 6:20 pm, maverick <sheikh.m.far...@gmail.com> wrote: >> Hi, I have a Spartan3AN xc3s1400AN FPGA board. There are externally >> ... > > Sounds like a timing problem. Intermediate failures are usually > timing related. Did you verify the timing of write data, internal > write enable and clock signals ? Remember that ChipScope might > not be of a lot of help with timing errors. It will in most cases > hide that type of error. Actually running Chipscope at a higher multiple of the clock is very good at seeing timing errors. Ideal if you have a spare DCM!Article: 141994
Hi http://www.xilinx.com/support/answers/32929.htm this AR seems to mention V-6 FXT and CXT devices? any info what exactly are the V-6 FXT? AnttiArticle: 141995
On Jul 21, 2:42=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > http://www.xilinx.com/support/answers/32929.htm > > this AR seems to mention V-6 FXT and CXT devices? > > any info what exactly are the V-6 FXT? > > Antti d*** the message was shown as vanished from google groups sorry for reposting, i also did NOT see the replies, maybe getting bling? yes, i know so far there have been no marks of 6FXT ever coming thats why i asked, funny the Xilinx AR dont answer but create new questions... AnttiArticle: 141996
Antti.Lukats@googlemail.com wrote: > > the message was shown as vanished from google groups > Do yourself a favour :-) http://www.google.com/search?q=list+of+free+news+servers HTH., Syms.Article: 141997
On Jul 21, 8:22=A0am, uday <uda...@ymail.com> wrote: > On Jul 19, 4:12=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > >http://groups.google.com/group/antti-brain?hl=3Den > > > uploaded ready to test bit file for spartan3a kit > > (need put small wire into SMA for antenna) > > > Antti > > ____________________________________________ > hi, > > =A0 =A0may i get source code of this as i want to download it to > spartan2 .. and some material to study .so that i can do project on > this. plz do the needful.. > =A0 =A0regards > =A0 =A0uday the design uses DCM's and runs at 210mhz so it would not work in S-2 AnttiArticle: 141998
On Jul 21, 2:53=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > Antti.Luk...@googlemail.com wrote: > > > the message was shown as vanished from google groups > > Do yourself a favour :-) > > http://www.google.com/search?q=3Dlist+of+free+news+servers > > HTH., Syms. sorry, I did give up using news servers many years ago the setup of them was just really painful, :( but the gg spam is enorm, and messages are disordered too and reformetted :(.. AnttiArticle: 141999
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323328-3244583-1248178792=:6493 Content-Type: TEXT/PLAIN; charset=ISO-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE On Fri, 17 Jul 2009, A. Wallner wrote: |------------------------------------------------------------------------| |"[..] | |> | |> What do the rest of you prefer? =A0Do you have both? =A0Do you still nee= d | |> to rely on your books or do you pretty well have the language down | |> pat?" | |------------------------------------------------------------------------| Memorizing things (whether for VHDL or something else) is pointless. |------------------------------------------------------------------------| |"> Is the IEEE VHDL standard available in e-book format? [..]" | |------------------------------------------------------------------------| Yes. |------------------------------------------------------------------------| |"In my case it really depends. | | | |I really like all three things...paper books and e-books | | | |I think reading is much better on paper than on a PC monitor. (Here | |the Kindle sounds interesting, but in Austria it is not available). So | |I really prefer a book if I'm about to read a whole lot (e.g. book to | |learn a new programming language). It also has the advantage that you | |can have the book open, and read there while working on you code (I | |have two monitors, and most of the time when I'm programming VHDL or C+ | |+ I use both monitors, so having a book is a real advantage) | | | |But If I just have to refresh my memory about something (syntax, etc.) | |I prefer PDFs because of their searchability. I have the few book I | |use the most in both forms (paper and electronic) and choose depending | |on mood/what I want to do which to use." | |------------------------------------------------------------------------| Yes, it is good to have both for different contexts. At home I do not want to waste money on electricity for a computer and a visual display unit if all I am doing with the text is reading it. In the office, copying and pasting or searching is more convenient with a computer. --8323328-3244583-1248178792=:6493--
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