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On Nov 7, 12:39=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 7, 6:10=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > pricing is when you look the order pages, from 12 to 16$ qty 1, > > cypress online shop > > but only 3 devices are shipping, so most of the devices do not have > > price visible > > Correct, and when you ratio their other sample prices, to their medium > volume prices, you get an indication of $6-8+ - a price that is > getting up there... > -jg got the starterkit, and free samples too http://www.youtube.com/watch?v=3DEQwUWk7dTp4 and, I was so dumb that I could not get the starterkit to get started without reading the manual! I pushed all buttons (1 out of 1 total) changed all jumpers (2 out of 2) but nothing, until i looked at the manual well its more clear in the video review Antti and no, I have not yet downloaded any own compiled verilog into the part, but i hope i check it soon enouughArticle: 144051
glen herrmannsfeldt wrote: > > I agree with the phase accumulator. I would have thought > of a look-up table for the sin/cos, though. If one big > table is too big, then a smaller table and linear interpolation > using either another table or a mutliplier. > > -- glen Also, you only need a quarter of a cycle in the LUT. The other four quandrants can be generated by inverting addresses and/or sign. CurtArticle: 144052
On 8 Nov., 18:24, doug <x...@xx.com> wrote: > DDS and analog filter on the msb. And when the quantization noise isn't noise but spectral lines inside the bandwidth of the analog filter you'll need some dithering.Article: 144053
On Nov 9, 11:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Nov 7, 12:39=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > On Nov 7, 6:10=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > pricing is when you look the order pages, from 12 to 16$ qty 1, > > > cypress online shop > > > but only 3 devices are shipping, so most of the devices do not have > > > price visible > > > Correct, and when you ratio their other sample prices, to their medium > > volume prices, you get an indication of $6-8+ - a price that is > > getting up there... > > -jg > > got the starterkit, and free samples too > > http://www.youtube.com/watch?v=3DEQwUWk7dTp4 > > and, I was so dumb that I could not get the starterkit to get started > without reading the manual! > I pushed all buttons (1 out of 1 total) changed all jumpers (2 out of > 2) but nothing, until i looked at the manual > well its more clear in the video review > > Antti > and no, I have not yet downloaded any own compiled verilog into the > part, but i hope i check it soon enouugh Is it just Verilog or does it work with VHDL as well. Seems odd to only support one. RickArticle: 144054
On Nov 9, 7:54=A0pm, rickman <gnu...@gmail.com> wrote: > On Nov 9, 11:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Nov 7, 12:39=A0am, -jg <jim.granvi...@gmail.com> wrote: > > > > On Nov 7, 6:10=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > pricing is when you look the order pages, from 12 to 16$ qty 1, > > > > cypress online shop > > > > but only 3 devices are shipping, so most of the devices do not have > > > > price visible > > > > Correct, and when you ratio their other sample prices, to their mediu= m > > > volume prices, you get an indication of $6-8+ - a price that is > > > getting up there... > > > -jg > > > got the starterkit, and free samples too > > >http://www.youtube.com/watch?v=3DEQwUWk7dTp4 > > > and, I was so dumb that I could not get the starterkit to get started > > without reading the manual! > > I pushed all buttons (1 out of 1 total) changed all jumpers (2 out of > > 2) but nothing, until i looked at the manual > > well its more clear in the video review > > > Antti > > and no, I have not yet downloaded any own compiled verilog into the > > part, but i hope i check it soon enouugh > > Is it just Verilog or does it work with VHDL as well. =A0Seems odd to > only support one. > > Rick I am not sure yet, I did see some verilog files, so it sure can do verilog the synthesis is done by Cypress WARP synthesis tool AnttiArticle: 144055
On Nov 9, 9:55=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > Alexey <trenk...@gmail.com> writes: > > Hello, > > > Is there a readily available IP that implements an interconnection of > > MicroBlaze processors, i.e. in a 2D-Mesh or Torus network? > > Just hang a bunch of FSL buses off the FSLs of the Microblazes. > > Copy and paste in the MHS file is less hassle than the XPS GUI in my > experience ;) > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html Thanks for the info, Martin. Will try the FSL busses. Alexey.Article: 144056
> > Standard answer for severely memory-limited application: use a > phase accumulator and CORDIC to calculate sin/cos from the > phase angle. =A0Needs quite a lot of FPGA fabric resource, but a > fully pipelined implementation is very convenient since it > needs no dedicated memory at all (each pipeline stage uses > one fixed value from an arctan lookup table, and this value > will end up being hard-wired). =A0Note that CORDIC gives you > both cos and sin outputs with no extra effort, which is > likely to be useful for your downconverter. > > If your target technology has some spare hardware multipliers, > CORDIC may not be the optimal solution. =A0But it's easy to > implement and well-understood. =A0If you have access to a clock > that's some exact multiple of your 16.758MHz sample rate, > then you can make the hardware more compact too. > > -- > Jonathan Bromley Jonathan, my clock is a multiple of the sample rate. I forgot to mention that. Thanks for your help, Guy.Article: 144057
On Nov 9, 6:05=A0pm, Curt Johnson <curt.john...@dicombox.net> wrote: > glen herrmannsfeldt wrote: > > > I agree with the phase accumulator. =A0I would have thought > > of a look-up table for the sin/cos, though. =A0If one big > > table is too big, then a smaller table and linear interpolation > > using either another table or a mutliplier. =A0 > > > -- glen > > Also, you only need a quarter of a cycle in the LUT. The other four > quandrants can be generated by inverting addresses and/or sign. > > Curt Thanks for your suggestions, Glen and Curt. I think I need to do more research on this before I discard the LUT-based solution. Guy.Article: 144058
If you're using makefiles, you might want to investigate xflow, which is the xilinx flow manager. It takes a text file which has all the options for all the backend tools, runs the tools in order, checking the status of the previous step before running the next step. It's similar to a makefile flow but more flexible I'd say. Outside of some vendor training classes I've never actually run the ISE gui. I do however use the synplify GUI, both for synthesis and to drive P&R. That's how I found out about xflow. --steve "Oscar Almer" <o.almer@gmail.com> wrote in message news:20091106130119.19849884@hummingbird... : : I, at least, gave up on the ise wrapper about a year and a half ago - : it just didn't do it, anymore. Instead I drive the flow (xst, map, par, : etc) from a single makefile, and a short one at that - maybe 20 lines. :Article: 144059
On Nov 9, 3:56=A0pm, rickman <gnu...@gmail.com> wrote: > On Nov 8, 5:15=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > > > > On Nov 9, 2:59=A0am, Guy Eschemann <guy.eschem...@gmail.com> wrote: > > > > Assuming a 16.758 MHz sample rate, what's the best way to generate a > > > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > > > since the least common multiple of both frequencies is very high, and > > > I have only limited memory, this is surely not optimal. The sampled > > > sinewave for a down-conversion application. > > > DDS is one way, but if you only want one =A0frequency, you should also > > check the humble VCO. > > The assumed ratio is 7.182 ( uses 2.333333' ) > > You can get that with a VCO and 4.3KHz compare Freq, > > or you can get within 25ppm, with a 212126.58 compare Freq. > > (/79; *11), and that's only 11 flipflops.. > > > -jg > > When you say VCO, are you suggesting that the OP use a PLL to generate > the a multiple of the 2.333... frequency and then use a much smaller > sine table? =A0That's not a bad idea actually. =A0But that would put the > samples in the new clock domain and I believe the OP needs the samples > in the 16.758 MHz clock domain. =A0I suppose a multirate filter could be > used to convert the sample rate, but I expect that would be a lot more > logic than the CORDEC approach. > > Rick Rick, as you guessed it, I do need to have the samples in the 16.758 MHz domain. Guy.Article: 144060
Guy Eschemann wrote: > Assuming a 16.758 MHz sample rate, what's the best way to generate a > 2.333333 MHz sine wave in an FPGA? I could use a look-up table, but > since the least common multiple of both frequencies is very high, and > I have only limited memory, this is surely not optimal. The sampled > sinewave for a down-conversion application. > > Many thanks, > Guy. Why not just output a square wave at the frequency you want then filter outside? You can get cheap sharp filters that should do the trick. at ~16Mhz the first harmonic is 3*16 = 48Mhz and is already 1/3 of the fundamental. http://www.fairchildsemi.com/sitesearch/fsc.jsp?command=eq&attr1=AAAFamily&attr2=Analog+Filters+and+Buffers If you really want to do it in FPGA maybe you can use a table with interpolation which would reduce the memory footprint at a cost of cycles. The more precise the interpolation the more cycles. Similarly, http://www.research.scea.com/research/pdfs/RGREENfastermath_GDC02.pdf Remember that the sin/cos are symmetric so you only have to calcuate 1/2 the table. In fact one can use any fractional part of the table and calculate the reet using the angle identity formulas: http://mathworld.wolfram.com/Multiple-AngleFormulas.htmlArticle: 144061
On Mon, 2009-11-09 at 11:11 -0500, MM wrote: > "Antti" <antti.lukats@googlemail.com> wrote in message > news:95de46f5-319d-480d-bb38- > > > you can sometimes enable "early access" support, by changing some things > > in the EDK, > > or just be adding the new family to the MPD files > > Antti, > > Have you actually tried this approach of "porting" MB to V6? I wonder how > much time I will have to spend and whether I will be able to estimate > performance this way... > > > Thanks, > /Mikhail > > I suggest to generate the XPS project for older FPGA like V5 or S3A first. You can change the FPGA in project settings then. JanArticle: 144062
On Nov 10, 6:58=A0am, Antti <antti.luk...@googlemail.com> wrote: > > I am not sure yet, I did see some verilog files, so it sure can do > verilog > the synthesis is done by Cypress WARP synthesis tool Does that mean ABEL is also in there, hiding in a corner somewhere? -jgArticle: 144063
Some time ago I managed to get (under NDA) the programming info from Xilinx so now I can program one of their coolrunners via JTAG with my toolchain (the CPLD on this design is reprogrammable over the net, i.e. the board CPU does its JTAG access etc.). I am now getting to what should be the easy part - writing the CPLD source to produce some (very simple) logic in a jedec file, after which I am fine. I got the current xilinx software, started it under windows and got really scared. Last time I used a not-in-house written logic compiler tool it was the PHDL thing for the Philips coolrunner (before I had my tool working). It was blindingly obvious how to use it and I don't remember having to discover much if anything about it, I just used it. Did not waste an hour. I already wasted a few hours with the new xilinx tool. It looks like because I want to hit a nail - and I do know how to use a hammer quite well - I have to hire a farm of robots so one will drive another to the shop where they will pick a truck of hammers and bring them back for another robot to choose the right hammer, then they'l put together a table onto which the operation will be performed and eventrually the talk robot will be telling me how to proceed with which hammer so I can hit my nail while holding my arms to protect me from injuring myself. Just terrific. Can someone please suggest something simpler? Which is my fastest way? I am not interested in learning all about their tools, I just want my logic into a jedec file (normally a 10 minutes' task here for what this is with my old coolrunner tools, but now I want to use a xcr3128xl part). There is some ABEL thing, is it usable in a way similar to more sane CPLD tools? (I gather it gets translated into vhdl to be processed but I guess I can live with that for now). Or their schematic entry, can it be usable? I wasted an hour until I **began to** figure out how to assign pins to things (far from having mastered that yet - not bad for a guy who has written his own toolchains for such stuff while having to do some reverse enginnering on the way, eh...). Thanks, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/Article: 144064
On Nov 6, 11:35=A0am, Mike Santarini <mike.santar...@gmail.com> wrote: > Hi folks, we just finished publishing the fall edition of Xcell > Journal, which has a cover story focus on the expanding role of FPGAs > in the Global Information Grid. The issue also has a lot of great > methodology and how-to content. We're now making it available in a one- > click download as well as in the Ceros (flash) format. I hope you > enjoy it.http://www.xilinx.com/publications/xcellonline/index.htm Hi Mike, I want to be a subscriber of hardcopy of Xcell. Does Xilinx still provide hardcopy of Xcell for free? I couldn't find the subject in the Xcell website so that I think Xilinx may have canceled it long ago? Thank you. WengArticle: 144065
On Nov 10, 3:14=A0am, Didi <d...@tgi-sci.com> wrote: > Some time ago I managed to get (under NDA) the programming info > from Xilinx so now I can program one of their coolrunners via JTAG > with my > toolchain (the CPLD on this design is reprogrammable over the net, > i.e. the > board CPU does its JTAG access etc.). > > =A0I am now getting to what should be the easy part - writing the CPLD > source > to produce some (very simple) logic in a jedec file, after which I am > fine. > > =A0I got the current xilinx software, started it under windows and got > really > scared. > =A0Last time I used a not-in-house written logic compiler tool it was > the PHDL > thing for the Philips coolrunner (before I had my tool working). It > was blindingly > obvious how to use it and I don't remember having to discover much if > anything > about it, I just used it. Did not waste an hour. > > =A0I already wasted a few hours with the new xilinx tool. > > =A0It looks like because I want to hit a nail - and I do know how to use > a hammer quite > well - I have to hire a farm of robots so one will drive another to > the shop > where they will pick a truck of hammers and bring them back for > another > robot to choose the right hammer, then they'l put together a table > onto > which the operation will be performed and eventrually the talk robot > will > be telling me how to proceed with which hammer so I can hit my nail > while > holding my arms to protect me from injuring myself. > Just terrific. > > Can someone please suggest something simpler? Which is my fastest way? > I am not interested in learning all about their tools, I just want my > logic > into a jedec file (normally a 10 minutes' task here for what this is > with my > old coolrunner tools, but now I want to use a xcr3128xl part). There > is some > ABEL thing, is it usable in a way similar to more sane CPLD tools? (I > gather > it gets translated into vhdl to be processed but I guess I can live > with that for > now). Or their schematic entry, can it be usable? I wasted an hour > until I > **began to** figure out how to assign pins to things (far from having > mastered > that yet - not bad for a guy who has written his own toolchains for > such stuff > while having to do some reverse enginnering on the way, eh...). > > Thanks, > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff =A0 =A0 =A0 =A0 =A0 =A0 =A0 Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------http://www.flickr.c= om/photos/didi_tgi/sets/72157600228621276/ I wonder :) why so complicated.. JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it under NDA the jedec bitmap info is not so public, but i did RE it withing a few days :) as of "doing something" 1) use schematic for design entry 2) use the graphical tool to assign pins it works, you should get leds blinking withing hours from there go as want, use VHDL or verilog both work ok AnttiArticle: 144066
On Nov 10, 2:14=A0pm, Didi <d...@tgi-sci.com> wrote: > There is some > ABEL thing, is it usable in a way similar to more sane CPLD tools? (I > gather it gets translated into vhdl to be processed but I guess I can li= ve > with that for now). ABEL is a good tool flow for CPLD, and especially good if you want to keep close to the JED file. AFAIK, the Xilinx ABEL flow still works, and as you say, it converts into spagetti VHDL for the rest of the tool chains, and timing. Xilinx used to include some .abl source examples - if you search for .abl, what do you find ? The fitters can report (.rpt) Boolean Eqns in ABEL format, so you can correlate that with the source code, and track polarity fuses, and macrocell config fuses etc. Those report files also have some fuse-level matrix tables, that you can use to trace small changes. What happen in-between you can pretty much ignore :) Somewhere in the depths, I think the fitters still swallow PLA files/ BLIF formats, and if you are adept at tools, you could even create an assembler that output BLIF files for the fitters... A compact Xilinx CPLD flow would be nice to see :) -jgArticle: 144067
http://www.altera.com/technology/embedded/news/emb-news-events.html there is small print that is important: NIOS II/e IS FREE VIC, it seems similar to Cortex NVIC, it DOES reduce the clock cycles wasted with interrupts, a feature that is not yet available for MicroBlaze/PPC where interrupts take forever Antti http://www.youtube.com/AnttiBrainArticle: 144068
Hi Group, In the past when I have wanted to use a script with ISE I have always simply run the flow using the gui first and then created a batch file using the command lines printed in the individual reports from xst, ngdbuild, etc. Seemed to work quite well especially when using the errorlevel returns (in Windows) to catch errors. I am aware of the xflow system and that something can also no doubt be done using tcl and I am wondering what the "best" method is. What do you use and why? One key feature I want to include in the design I'm starting now is automatic build number increments by way of automatically increasing an integer generic supplied to XST. This will be used to set the reset value of a register in the VHDL. I am guessing a tcl script would be best for this but can this also be done using xflow? Many thanks for your time.Article: 144069
Hi, MicroBlaze works fine in V6 and has so for some time now. EDK will only make cores officially supported for an architecture if we have proven the core in real hardware with production status of the speed files. By setting "Early access" for IP catalog in the XPS preferences, you will see MicroBlaze in the IP catalog when you have selected V6 or S6, provided that you have a ISE installation that supports V6/S6. However BSB will not generate V6 or S6 systems yet since the cores needs official approval first for BSB. But just generate a system for V5 board in BSB and then change the architecture to S6 or V6. Remember that packages and pinout will most likely differ so you might need to modify the system.ucf file if you want to create a bitfile. Don't do this for MPMC based system since plenty of placement constraints are architecture and board specific. MicroBlaze in V6 runs at least one speed grade faster than in V5. G=F6ran Bilski Jan Pech wrote: > On Mon, 2009-11-09 at 11:11 -0500, MM wrote: > > "Antti" <antti.lukats@googlemail.com> wrote in message > > news:95de46f5-319d-480d-bb38- > > > > > you can sometimes enable "early access" support, by changing some thi= ngs > > > in the EDK, > > > or just be adding the new family to the MPD files > > > > Antti, > > > > Have you actually tried this approach of "porting" MB to V6? I wonder h= ow > > much time I will have to spend and whether I will be able to estimate > > performance this way... > > > > > > Thanks, > > /Mikhail > > > > > > I suggest to generate the XPS project for older FPGA like V5 or S3A > first. You can change the FPGA in project settings then. > > JanArticle: 144070
hi group, In following page, in what order should I start to learn about Virtex 4 ? http://www.xilinx.com/support/documentation/virtex-4_user_guides.htm Thanks, AmitArticle: 144071
In comp.arch.fpga Antti <antti.lukats@googlemail.com> wrote: > JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it > under NDA There are no 1532 BSDL files in the Xilinx/11.1/ISE/xpla3/data/ directory, so NDA is probably needed. ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 144072
Antti <antti.lukats@googlemail.com> wrote: > http://www.altera.com/technology/embedded/news/emb-news-events.html > there is small print that is important: > NIOS II/e IS FREE > VIC, it seems similar to Cortex NVIC, it DOES reduce the clock cycles > wasted with interrupts, a feature that is not yet available for > MicroBlaze/PPC where interrupts take forever Is HDL available? It is allowed to retarget to X/L/... ? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 144073
What are peoples' experiences of power supplies to sensitive analog rails in FPGAs? For example, the guideline for both Xilinx and Altera all recommend the use of linear regulators to supply such things as high speed transceivers and PLLs. But does this really help? Is a linear reg really any better than using switchers and good local filtering? Does the linear reg actually filter out any noise itself, or is it only as good as its input (which is quite probably another switcher!)? Thanks, NickArticle: 144074
On Nov 10, 1:08=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Antti <antti.luk...@googlemail.com> wrote: > >http://www.altera.com/technology/embedded/news/emb-news-events.html > > there is small print that is important: > > NIOS II/e IS FREE > > VIC, it seems similar to Cortex NVIC, it DOES reduce the clock cycles > > wasted with interrupts, a feature that is not yet available for > > MicroBlaze/PPC where interrupts take forever > > Is HDL available? It is allowed to retarget to X/L/... ? > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- LOL I think you can answer those questions yourself :) sure it would be cool but i bet no, it is not the case Antti http://www.techbites.com/lukats/
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