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On Apr 30, 11:16=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Both clocks are driven from a > PLL. I want to tell Synplify that the two clocks can be in different cloc= k > groups for timing and so have a false path between them. Not to be a noodge, but declaring paths between two clock domains to be 'false paths' is not the proper approach. By *declaring* them to be false paths, you're allowing any crazy logic that connects the two clock domains to be acceptable for timing analysis...which it most certainly is not. You should be - Finding each and every clock domain crossing (the timing analyzer will find them) - Verifying that the logic connecting the two domains is appropriate handshaked - Individually specify that each identified logic path is multi- cycle. Wildcarding should be kept to a minimum, like only for collectively identifying the bits of a bus If you wildcard at a higher level you run the risk that some future (or current) design change will fit the wildcard spec and thus not get analyzed, but not be appropriate clock domain crossing logic so in reality the design will fail. Declaring all paths between clock domains to be false paths as you said you'd like to do is exactly the same as wildcarding everything and is a mistake waiting to come and bite you. Kevin JenningsArticle: 147551
I am using an asynchronous fifo to cross the two clock domains so I would think that as long as I respect the fifo flags on each side then crossing from one domain to the next should not be a problem. At the moment because the clocks from the pll are related ISE is trying to analyise the paths between them but is failing to meet the very small period of 1ns. So I would think that I need to tell ISE to ignore the paths between each domain otherwise the design will never P&R. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147552
On May 1, 10:47=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I am using an asynchronous fifo to cross the two clock domains so I would > think that as long as I respect the fifo flags on each side then crossing > from one domain to the next should not be a problem. Only those signals that cross the clock domain that you are absolutely sure are done correctly should be flagged as being multi-cycle...So that might be the data and control signals for the fifo, not everything that crosses from one domain to the other. > So I > would think that I need to tell ISE to ignore the paths between each doma= in And what if you inadvertantly have some clock domain crossnig that is not done correctly? Now timing analysis won't flag that for you...it's also far too easy to convince yourself that you've done things correctly...only to find out later that you were wrong. Kevin JenningsArticle: 147553
On May 1, 3:42=A0am, Andrew Pichler <And...@yahoo.com> wrote: > Hi > > I wanna give some student a tutorial about FPGA programming and > I wonder if there are any cheap FPGA evaluation kits out there > that I could get? Needs to be nothing special, just a small board > with some LEDS would be fun. > > THanks for any useful links, > Andrew The Digilent Basys (www.digilentinc.com) has 8 switches, 4 buttons, 8 discrete LEDs, a 4 digit LED 7 segment display, VGA, PS/2 keyboard, 4 6 pin connectors, and has a built-in USB programmer / data transfer port. $80 USD. (If the use is "academic" then only $60.) Writing code to do the multiplexing for the 7 segment display is a fun little project. You can also buy add-on modules (they call them PMODs) that plug into the 6 pin connectors (4 data pins, power and ground). They have all sorts of different PMODs. For your purposes, the one with a little breadboard on it for $15 might be fun. They also have a lot of other FPGA boards. At my company, we've probably bought 30 or 40 of the Nexys and Nexys2 boards, and we use them in the lab to control various things. The only downside I know of is that Digilent's programming and data transfer software doesn't support Linux. (On windows, you can use their DLL to transfer data to/ from the board.) Regards, PatArticle: 147554
On May 1, 8:42=A0pm, Andrew Pichler <And...@yahoo.com> wrote: > Hi > > I wanna give some student a tutorial about FPGA programming and > I wonder if there are any cheap FPGA evaluation kits out there > that I could get? Needs to be nothing special, just a small board > with some LEDS would be fun. > > THanks for any useful links, > Andrew Then there are CPLD board ? This is sub$20 http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,798&Prod=3DC= MOD (needs a pgmr link) This one is more complete, and a larger device, with LCD http://www.latticesemi.com/products/developmenthardware/developmentkits/isp= mach4000zepicodevkit.cfm or this http://www.latticesemi.com/products/developmenthardware/developmentkits/mac= hxominidevelopmentkit.cfm?source=3Dsidebar or this ? http://search.digikey.com/scripts/dksearch/dksus.dll?Detail?name=3DATF15XX-= DK3-NDArticle: 147555
Patrick Maupin wrote: > On May 1, 3:42 am, Andrew Pichler <And...@yahoo.com> wrote: >> I wanna give some student a tutorial about FPGA programming and >> I wonder if there are any cheap FPGA evaluation kits out there >> that I could get?[ ... ] > > The Digilent Basys (www.digilentinc.com) has 8 switches, 4 buttons, 8 > discrete LEDs, a 4 digit LED 7 segment display, VGA, PS/2 keyboard, 4 > 6 pin connectors, and has a built-in USB programmer / data transfer > port. $80 USD. (If the use is "academic" then only $60.) This looks good. Sparkfun has a couple of boards: <http://www.sparkfun.com/commerce/product_info.php?products_id=8458> <http://www.sparkfun.com/commerce/product_info.php?products_id=8596> but that exhausts their range. One Spartan3 and one Altera. Digilent seems more committed. In my own case, I followed Sparkfun and got the Spartan3 board, but I'm so far out of luck because the only development tools I've been able to get are Altera. When I click the download button on the Xilinx web page, the site ignores it completely. Since I'm really a microcontroller firmware developer who's trying to keep his vocabulary up to date, I leave this mostly on the back burner. Thanks to the OP for raising this question. Mel.Article: 147556
On May 1, 4:42=A0am, Andrew Pichler <And...@yahoo.com> wrote: > Hi > > I wanna give some student a tutorial about FPGA programming and > I wonder if there are any cheap FPGA evaluation kits out there > that I could get? Needs to be nothing special, just a small board > with some LEDS would be fun. > > THanks for any useful links, > Andrew I have a couple of evaluation boards that I bought when they were first released with the introductory pricing, generally significantly lower than the normal price. Generally these kits are subsidized by the chip manufacturer to get new design wins. I would keep my eye out for new introductory offers if you can afford to wait. Of course I don't qualify for the educational discount which can also be considerable for some board families. Another thing to note is that Lattice has the habit of labeling some of their FPGA's as CPLD's to try to gain CPLD replacement design-ins. Make no mistake about it, the MachXO is an FPGA. The larger ones like those in the MachXO Mini Development Kit even have block RAM and phase-locked loops. Good luck, GaborArticle: 147557
Andrew Pichler <Andrew@yahoo.com> writes: > I wanna give some student a tutorial about FPGA programming and > I wonder if there are any cheap FPGA evaluation kits out there > that I could get? Needs to be nothing special, just a small board > with some LEDS would be fun. The BeMicro at $49 could fit that description: http://www.arrownac.com/offers/altera-corporation/bemicro/ It contains an Altera Cyclone III Petter -- .sig removed by request.Article: 147558
On May 1, 1:42=A0am, Andrew Pichler <And...@yahoo.com> wrote: > Hi > > I wanna give some student a tutorial about FPGA programming and > I wonder if there are any cheap FPGA evaluation kits out there > that I could get? Needs to be nothing special, just a small board > with some LEDS would be fun. > > THanks for any useful links, > Andrew For training classes, I'm a big fan of Digilent products, primarly all Xilinx. They are relatively inexpensive and have plenty of available add-on peripheral modules to support a variety of applications. The BASYS II board is probably more than you need, but it's only $59 to academic customers. http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,790&Prod=3DB= ASYS2 There is also a more capable version version called NEXYS II that sells for $99 to academic customers. http://www.digilentinc.com/Products/Detail.cfm?NavTop=3D2&NavSub=3D451&Prod= =3DNEXYS2 Another option, although a bit more complicated, is the Spartan-3A Low- Cost Evaluation Kit from Avnet/Silica. It sells for $49 and also includes a Cypress PSoC companion chip. http://www.silica.com/index.php?id=3D1193 http://www.em.avnet.com/evk/home/0,1719,RID%253D%2526CID%253D46501%2526CAT%= 253D0%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526SRT%253D1%2526L= ID%253D32232%2526PRT%253D0%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CT= P%253DEVK,00.html If you swing the other way, TerASIC has some nice kits for Altera. You can order directly from the company in Taiwan and they have some of the kits through Digi-Key. MAX II CPLD Micro Kit ($69) http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&Catego= ryNo=3D64&No=3D215 They also have a nice Cyclone III board for $79 for academic customers. http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=3DEnglish&Catego= ryNo=3D56&No=3D364 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Steven K. Knapp Prevailing Technology, Inc. Web: www.prevailing-technology.comArticle: 147559
Hi guys,
I'm porting my LatticeMico32 SoC across to a different FPGA board which
uses a Xilinx Spartan3A (XC3S700A; the board is an Enterpoint Drigmorn2).
I've got most of it moved across, but the Boot ROM is being difficult.
This was implemented using the Altera ROM generator and a MIF file, but
obviously isn't an option on the Xilinx platform.
The ROM is 32 bits wide, and stores 2048 words.
What I've done is this:
// Boot ROM logic
reg [31:0] BOOTROM_MEM [0:2047];
reg [31:0] BOOTROM_Q;
assign BOOTROM_DATA_OUT = BOOTROM_Q;
// Only update DQ register on clock edge
always @(posedge MCLK) begin
BOOTROM_Q <= BOOTROM_MEM[BOOTROM_ADDR[12:2]];
end
// Init memory array from firmware image
initial $readmemh("firmware/boot0.vmem", BOOTROM_MEM, 0, 2047);
// WISHBONE ACK generation logic goes here
I'm using SRec to generate the VMEM file:
srec_cat -Output boot0.vmem -VMem 32 boot0.bin -binary -generate 0 8192
-difference -over boot0.bin -binary -b-e-const 0x34000000 4
The first few lines of the VMEM file are:
/* http://srecord.sourceforge.net/ */
@00000000 98000000 D0000000 78010000 38210000 D0E10000 F800003B 34000000
@00000007 34000000 91203800 34E70020 C0E00000 34000000 34000000 34000000
@0000000E 34000000 34000000 91203800 34E70040 C0E00000 34000000 34000000
If I try and build this code in ISE11.1, I get this error:
ERROR:Xst:2354 - "lm32_soc_top.v" line 430: Value 78313372 found at line
1 is not hexadecimal in call of system task $readmemh.
If I remove the starting comment from the VMEM file, I get this instead:
ERROR:Xst:2352 - "lm32_soc_top.v" line 430: Address -1 found at line 1 is
invalid in call of system task $readmemh.
I can't see anything obviously wrong with the code, nor can I find
anything on Xilinx's website or the XST manuals that explains these
errors... What am I doing wrong here?
Thanks,
--
Phil.
usenet09@philpem.me.uk
http://www.philpem.me.uk/
Article: 147560
Hi,
I have some problems to let the FPGA generate an interrupt and to detect
this interrupt on the computer (via PCI).
Below you find a part of the VHDL-code from the PCI core generated by
Xilinx Core Generator. Everytime data is written on the PCI bus the
interrupt (INTR_N) will be asserted.
Beneath that there is a part of the c-code from the device driver file I
made in Linux (Ubuntu). So everytime it detects an interrupt from the FPGA,
it will add one to the counter (IRQ_count).
The problem I have is that the counter remains 0. Someone knows what could
be wrong? Is there a problem with the code or am I using the wrong
interrupt signal? I hope someone can help me. I can send data to the FPGA
via the pc so I presume there is no problem with the connection between
both hardware devices.
Thanks in advance!
--------------------------------------
--- PCI CORE / IO32 Implementation ---
--------------------------------------
WRITE_MY_IO_REG:
process(RST, CLK)
begin
if RST = '1' then my_io_reg <= "00010000000100000001000000010000";
intr_n_reg <= '0';
elsif (CLK'event and CLK = '1') then
if S_DATA_VLD = '1' and bar0_wr_cs = '1' then
intr_n_reg <= '1';
if S_CBE(0) = '0' then my_io_reg( 7 downto 0) <= ADIO( 7 downto
0);
end if;
if S_CBE(1) = '0' then my_io_reg(15 downto 8) <= ADIO(15 downto
8);
end if;
if S_CBE(2) = '0' then my_io_reg(23 downto 16) <= ADIO(23 downto
16);
end if;
if S_CBE(3) = '0' then my_io_reg(31 downto 24) <= ADIO(31 downto
24);
end if;
else intr_n_reg <= '0';
end if;
end if;
end process;
INTR_N <= intr_n_reg;
oe_io_reg <= bar0_rd_cs and S_DATA;
ADIO <= my_io_reg when (oe_io_reg = '1') else (others=>'Z');
---------------------------------------
--- Linux Device Driver / Interrupt ---
---------------------------------------
irqreturn_t pci_interrupt_handler(int irq, void *dev_id)
{
irq_count = irq_count + 1;
printk(KERN_INFO "Virtex 2 PRO Interrupt detected %i\n", irq_count);
return IRQ_HANDLED;
}
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 147561"Ghostboy" <Ghostboy@n_o_s_p_a_m.n_o_s_p_a_m.dommel.be> wrote: >Hi, > >I have some problems to let the FPGA generate an interrupt and to detect >this interrupt on the computer (via PCI). > >Below you find a part of the VHDL-code from the PCI core generated by >Xilinx Core Generator. Everytime data is written on the PCI bus the >interrupt (INTR_N) will be asserted. Aren't there 4 interrupt pins on a PCI slot (INT_A through INT_D)? Maybe you're triggering the wrong pin. You should also be able to see the interrupt count in /proc/interrupts -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 147562
On May 3, 2:33=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote:
> Hi guys,
>
> I'm porting my LatticeMico32 SoC across to a different FPGA board which
> uses a Xilinx Spartan3A (XC3S700A; the board is an Enterpoint Drigmorn2).
> I've got most of it moved across, but the Boot ROM is being difficult.
> This was implemented using the Altera ROM generator and a MIF file, but
> obviously isn't an option on the Xilinx platform.
>
> The ROM is 32 bits wide, and stores 2048 words.
>
> What I've done is this:
> // Boot ROM logic
> reg [31:0] BOOTROM_MEM [0:2047];
> reg [31:0] BOOTROM_Q;
> assign BOOTROM_DATA_OUT =3D BOOTROM_Q;
>
> // Only update DQ register on clock edge
> always @(posedge MCLK) begin
> =A0 =A0 =A0 =A0 BOOTROM_Q <=3D BOOTROM_MEM[BOOTROM_ADDR[12:2]];
> end
>
> // Init memory array from firmware image
> initial $readmemh("firmware/boot0.vmem", BOOTROM_MEM, 0, 2047);
> // WISHBONE ACK generation logic goes here
>
> I'm using SRec to generate the VMEM file:
> =A0 srec_cat -Output boot0.vmem -VMem 32 boot0.bin -binary -generate 0 81=
92
> -difference -over boot0.bin -binary -b-e-const 0x34000000 4
>
> The first few lines of the VMEM file are:
> /*http://srecord.sourceforge.net/*/
> @00000000 98000000 D0000000 78010000 38210000 D0E10000 F800003B 34000000
> @00000007 34000000 91203800 34E70020 C0E00000 34000000 34000000 34000000
> @0000000E 34000000 34000000 91203800 34E70040 C0E00000 34000000 34000000
>
> If I try and build this code in ISE11.1, I get this error:
> ERROR:Xst:2354 - "lm32_soc_top.v" line 430: Value 78313372 found at line
> 1 is not hexadecimal in call of system task $readmemh.
>
> If I remove the starting comment from the VMEM file, I get this instead:
> ERROR:Xst:2352 - "lm32_soc_top.v" line 430: Address -1 found at line 1 is
> invalid in call of system task $readmemh.
>
> I can't see anything obviously wrong with the code, nor can I find
> anything on Xilinx's website or the XST manuals that explains these
> errors... What am I doing wrong here?
>
> Thanks,
> --
> Phil.
> usene...@philpem.me.ukhttp://www.philpem.me.uk/
Xilinx's support of $readmemh is pretty brain-dead. Here's the
rules that have worked for me:
1) No addresses in the hex file. Sorry - not supported.
2) Exactly one value per line of text.
3) No comments.
4) Size of the initialization data must exactly match the size
of the memory array it initializes. Partial initialization of
an array results in no initialization (entire array reverts to
its default of all zeroes).
Xilinx does have other means of initializing instantiated memory
using "init" properties, and .coe file for initializing CoreGen
memories. However if you can live with the rules for initializing
inferred memories it should be more portable.
HTH,
Gabor
Article: 147563On Mon, 03 May 2010 14:08:30 -0700, Gabor wrote: > 1) No addresses in the hex file. Sorry - not supported. 2) Exactly one > value per line of text. 3) No comments. > 4) Size of the initialization data must exactly match the size of the > memory array it initializes. Partial initialization of an array results > in no initialization (entire array reverts to its default of all > zeroes). OK, it seems it's even more braindead than that... WARNING:Xst:1781 - Signal <BOOTROM_MEM> is used but never assigned. Tied to default value. This is despite the 'initial' block telling it what to load and from where... Does Xst log of the initial contents of inferred ROMs anywhere? That is, can I actually see what's in the ROM without either running the HDL under a simulator or using a logic analyser / data generator to test it? And for extra bonus points: INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal <cacheline_data>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time. Ho hum. Quartus inferred an M4K blockram for that. I did wonder why the gatecount was off in the stratosphere somewhere. Why do I suddenly get the feeling I've been catapulted back to the dark ages? -- Phil. usenet09@philpem.me.uk http://www.philpem.me.uk/ If mail bounces, replace "09" with the last two digits of the current year.Article: 147564
On May 3, 6:59=A0pm, Philip Pemberton <usene...@philpem.me.uk> wrote: > On Mon, 03 May 2010 14:08:30 -0700, Gabor wrote: > > 1) No addresses in the hex file. =A0Sorry - not supported. 2) Exactly o= ne > > value per line of text. 3) No comments. > > 4) Size of the initialization data must exactly match the size of the > > memory array it initializes. =A0Partial initialization of an array resu= lts > > in no initialization (entire array reverts to its default of all > > zeroes). > > OK, it seems it's even more braindead than that... > > WARNING:Xst:1781 - Signal <BOOTROM_MEM> is used but never assigned. Tied > to default value. > > This is despite the 'initial' block telling it what to load and from > where... Does Xst log of the initial contents of inferred ROMs anywhere? > That is, can I actually see what's in the ROM without either running the > HDL under a simulator or using a logic analyser / data generator to test > it? > > And for extra bonus points: > > INFO:Xst:738 - HDL ADVISOR - 1024 flip-flops were inferred for signal > <cacheline_data>. You may be trying to describe a RAM in a way that is > incompatible with block and distributed RAM resources available on Xilinx > devices, or with a specific template that is not supported. Please review > the Xilinx resources documentation and the XST user manual for coding > guidelines. Taking advantage of RAM resources will lead to improved > device usage and reduced synthesis time. > > Ho hum. Quartus inferred an M4K blockram for that. I did wonder why the > gatecount was off in the stratosphere somewhere. Why do I suddenly get > the feeling I've been catapulted back to the dark ages? > > -- > Phil. > usene...@philpem.me.ukhttp://www.philpem.me.uk/ > If mail bounces, replace "09" with the last two digits of the current > year. XST is pretty finicky about inferring memory. You should look at the recommended templates in the XST Manual. Also from the original topic I didn't realize you were defining a ROM rather than just initial values for a RAM. XST also has problems with block RAM used as ROM. I haven't tried this myself, but I've seen a number of threads here where the solution is to give your "ROM" a write port. I have had good luck with initializing RAM using the initial block and $readmemh once I found its limitations, though. Good Luck, GaborArticle: 147565
Hi Guys What could be the optimal buffer for an asynchronous FIFO with the source clock at 50 MHz and the Read clock is 25 MHz Data is clming as 8 bits with each clock write . There is no idle cycle. We have to keep the synchronization latancy also into account. Thanks VipsArticle: 147566
Hi All
What could be the optimal buffer for an asynchronous FIFO with the
Write clock at 50 MHz and the Read clock is 25 MHz
Data is coming as 8 bits with each clock write . There is no idle
cycle. We have to keep the synchronization latency also into account.
Thanks
Vips
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From: Paul Uiterlinden <puiterl@notaimvalley.nl>
Subject: Re: I'd rather switch than fight!
Newsgroups: comp.lang.vhdl,comp.arch.fpga,comp.lang.verilog
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Alan Fitch wrote:
> On 28/04/2010 11:56, Brian Drummond wrote:
>>
>> If VHDL is to adopt a conditional operator I hope it can do better than
>> that! Something less surprising, and generalisable to other discrete
>> types or at least other enums.
>
> And VHDL 2008 provides various matching operators that allow std_logic,
> bit and so on to be interpreted as Boolean - see
>
http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/
>
> If you're interested in VHDL 2008, I recommend the book "VHDL 2008 -
> Just the New Stuff" by Peter Ashenden and Jim Lewis.
Indeed: highly recommended.
> Now if only the tools supported ...
Again: indeed. I asked Mentor Graphics when to expect full support for VHDL
2008 in ModelSim/QuestaSim. This was their answer:
> There isn't a set date/revision for full support for VHDL 2008
> at this point. Some of the reasons are due ambiguity in the
> spec and and the resulting work between customers and the
> standards committee, and the priority/usefulness/convenience of
> the still to-do features. I see some are not scheduled until
> 6.7 towards the end of the year and no doubt some will come
> later than that.
Seems it is going to take a while....
I sent in my wish list, highest priority first:
> - generic types
> - generic lists in packages
> - generic lists in subprograms
> - generic subprograms
> - local packages
> - context declarations
> - unconstrained element types
> - signal expressions in port maps
> - all signals in sensitivity list
> - std_logic_1164: std_logic_vector is a subtype of std_ulogic_vector
> - if and case generate
> - condition operator ("??")
> - matching relational operators ("?=", "?/=", "?<", ...)
> - matching case statements ("case?")
The matching operators are low in the list, as I'm mainly interested in
improvements in the area of behavioral VHDL for verification
(testbenches/testcases/BFMs).
--
Paul Uiterlinden
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Article: 147567Hello, While using Qurtus II with a design that has only one section where timing is critical I got on the classical timing analyzer the relevant warnings about what it finds and that is absolutely fine and as expected. However on the remaining part of the design, (some quasi static configurations etc) that runs very slowly and have its signals driven by software with an external microcontroller, I have hundreds of warnings of things that might not operate as expected and fail for all sorts of reasons, this is related with stupid sequences behaviours and operations that will never happen as this is a software controlled thing, and those operations are well defined and do work obviously as expected while properly commanded by software. Surely I don't blame the timing analyzer to check those... of course... but... Question: How can I instruct quartus II to do not perform those timing checks for a number of selected paths/signals ? This is annoying and unnecessary time consumption and a major distraction to the real things I'm worried and try to get working well on this design. Any help ? Thanks. Luis C.Article: 147568
The data sheet of the PCI core says that you can use INTR_N from within the user application to make an interrupt. But I must admit that I can't see a connection to the bus. There is indeed also INTR_A but I can't find a way to connect it to INTR_N. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147569
On May 4, 2:29=A0am, Vips <thevipulsi...@gmail.com> wrote: > Hi All > > What could be the optimal buffer for an asynchronous FIFO with the > Write clock at 50 MHz and the Read clock is 25 MHz > > Data is coming as 8 bits with each clock write . There is no idle > cycle. We have to keep the synchronization latency also into account. > > Thanks > > Vips If I understand correctly you're asking how to calculate the depth of the FIFO required for your application? When you say "there is no idle cycle" I assume you mean that data is written to the input on every clock cycle. For how long? Obviously for this FIFO to work indefinitely, you would need to adjust the output bandwidth to exceed the input bandwidth or else its depth would need to be infinite. For a fixed input packet length you can calculate the depth as the size of the packet minus the number of words read from the FIFO while the packet was being written. In your case, assuming the FIFO read enable is always active when the FIFO is not empty, there would only be a short delay for flag synchronization, then one word read for every two words written. So the depth would need to be half the packet size plus the number of input clock cycles required to start up the readout. HTH, GaborArticle: 147570
>Hello, > >Question: > >How can I instruct quartus II to do not perform those timing checks for >a number of selected paths/signals ? > >This is annoying and unnecessary time consumption and a major >distraction to the real things I'm worried and try to get working well >on this design. > >Any help ? > >Thanks. > > >Luis C. > check out AN481 Applying Multicycle exceptions in the TimeQuest timing analyzer --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147571
On Tue, 04 May 2010 11:50:10 +0100, LC <cupidoREMOVE@mail.ua.pt> wrote: >Hello, > >While using Qurtus II with a design that has only >one section where timing is critical I got on the classical timing >analyzer the relevant warnings about what it finds and that is >absolutely fine and as expected. > >However on the remaining part of the design, (some quasi static >configurations etc) that runs very slowly and have its signals >driven by software with an external microcontroller, I have hundreds of >warnings of things that might not operate as expected and fail for all >sorts of reasons, this is related with stupid sequences behaviours and >operations that will never happen as this is a software controlled >thing, and those operations are well defined and do work obviously as >expected while properly commanded by software. >Surely I don't blame the timing analyzer to check those... of course... >but... > >Question: > >How can I instruct quartus II to do not perform those timing checks for >a number of selected paths/signals ? > >This is annoying and unnecessary time consumption and a major >distraction to the real things I'm worried and try to get working well >on this design. > >Any help ? You can use set_false_path or a command like set_case_analysis. But the latter is for things which really don't change during functional mode (ie you need a reset after changing the value etc.) and the former can be really dangerous; even if it's constant for long periods of time, it needs to change at some point and there maybe functional issues at that point of change. You need to guarantee that your design will not go into an unrecoverable mode when you change one of these configuration bits. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 147572
On 4 Mai, 08:27, Vips <thevipulsi...@gmail.com> wrote: > Hi Guys > > What could be the optimal buffer for an asynchronous FIFO with the > source clock > > at 50 MHz and the Read clock is 25 MHz > > Data is clming as 8 bits with each clock write . There is no idle > cycle. We have to keep the synchronization latancy also into account. If you want to run that for one year 772 TByte FIFO should be enough. (The FIFO content will grow with 25MByte/s) Should fit in a single rack enclosure without problems. KoljaArticle: 147573
"Kolja Sulimma" <ksulimma@googlemail.com> wrote in message news:501b9be9-de49-49b2-8ac7-2749b575f0d0@o11g2000yqj.googlegroups.com... > On 4 Mai, 08:27, Vips <thevipulsi...@gmail.com> wrote: >> Hi Guys >> >> What could be the optimal buffer for an asynchronous FIFO with the >> source clock >> >> at 50 MHz and the Read clock is 25 MHz >> >> Data is clming as 8 bits with each clock write . There is no idle >> cycle. We have to keep the synchronization latancy also into account. > > If you want to run that for one year 772 TByte FIFO should be enough. > (The FIFO content will grow with 25MByte/s) > Should fit in a single rack enclosure without problems. > > Kolja Actually if it is to run for a year then 394TB should be adequate - half the amount. It only needs to fill for 6 months, it will take the other 6 months to unload it before the system turns off. Also only half a rack enclosure required. PhilArticle: 147574
On May 4, 2:43=A0pm, "Phil Jessop" <p...@noname.org> wrote: > "Kolja Sulimma" <ksuli...@googlemail.com> wrote in message > > news:501b9be9-de49-49b2-8ac7-2749b575f0d0@o11g2000yqj.googlegroups.com... > > > > > On 4 Mai, 08:27, Vips <thevipulsi...@gmail.com> wrote: > >> Hi Guys > > >> What could be the optimal buffer for an asynchronous FIFO with the > >> source clock > > >> at 50 MHz and the Read clock is 25 MHz > > >> Data is clming as 8 bits with each clock write . There is no idle > >> cycle. We have to keep the synchronization latancy also into account. > > > If you want to run that for one year 772 TByte FIFO should be enough. > > (The FIFO content will grow with 25MByte/s) > > Should fit in a single rack enclosure without problems. > > > Kolja > > Actually if it is to run for a year then 394TB should be adequate - half = the > amount. It only needs to fill for 6 months, it will take the other 6 mont= hs > to unload it before the system turns off. Also only half a rack enclosure > required. > > Phil Thank you Phil. You just saved the OP a ton of money :-)
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