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Nico Coesel <nico@puntnl.niks> wrote: > Jay <jpt03002@engr.uconn.edu> wrote: > >> Gabor <gabor@alacron.com> wrote: >>> On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: >>>> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: >>>> >>>>> Hey all. >>>> >>>>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx's >>>>> documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested >>>>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protect >>>>> the port from reverse current damage. However, instill might face logic >>>>> high problems as read from the avr. What would you suggest for a (small >>>>> footprint if possible) logic level converter? >>>> >>>>> Thanks in advance. >>>> >>>> There are so many chips for level shifting that the best fit >>>> will really depend on your particular design. How many >>>> signals do you connect between the FPGA and the 5V >>>> micro? How many are inputs to the FPGA, how many >>>> outputs from the FPGA and how many are bidirectional? >>>> Going from 3V to 5V, you probably want to look at 74ACT >>>> series or something similar that can work with a 5V supply >>>> but has "TTL" compatible Vih and Vil specs. Going from >>>> 5V to 3V you could use the resistor (unidirectional). For >>>> bidirectional signals there are some parts with dual power >>>> supply that can provide active drive to both sides. If the >>>> signals are relatively slow, then you can use "Quickswitch" >>>> style FET switches and pullup resistors to do level shifting >>>> bidirectionally without any added control signals. >>>> >>>> Regards, >>>> Gabor >>> >>> One more point I forgot to add. The resistor trick doesn't >>> work with the newer Spartan 3A and 3AN series parts. >>> Those FPGA's don't have clamp diodes to Vcco. >>> >>> -- Gabor >> Yeah in saw that. I'm not using the 3a, but i do need bi directional IO. >> There will be a total of 13 pins to the uC that need this treatment. > > Use resistors and 3.3V zeners. I think after looking at some part finders, I'm going to use a couple 74lcx245's to give me 14 bidirectional ios. It'll keep my board layout a bit nicer, too.Article: 150601
Whenever I see internal tool errors like that I first suspect a quota/full disk type problem. --steve "Michael" <michael_laajanen@yahoo.com> wrote in message news:8qajvpF1l4U1@mid.individual.net... > Hi, > > I am trying a design that is from ISE 9.2 on the latest 12.4 using CentOS > 64 bit and receive the following error, I can't find anything > on Xilinx that refers to it. > > Anyone seen the same and know a solution? > > > > INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes > peeked > does not match number of bytes requested. Corrupted file?Article: 150602
rickman wrote:
> This is the first project I've done in Verilog in many years. With a
> long history in VHDL I have a new perspective and am seeing Verilog in
> a different way. I am finding some of the differences to be pretty
> interesting actually.
>
> I've already commented on the lack of the wildcard sensitivity only to
> find that VHDL has recently added this. Now I am learning how Verilog
> allows hierarchical path references to signals for test benches. This
> is awesome!!! I would love to have had this in Verilog. It is such a
> PITA to have to bring every generic or debug signal to the top of a
> design just to support a test bench.
If you're using ModelSim, there's a library "modelsim_lib" that has a
function called "SignalSpy". With that you can access any signal in your
design from a test bench. Use it like this:
library modelsim_lib;
use modelsim_lib.util.all;
-- entity, architecture, signal declarations skipped
-----------------------------------------------------------------------------
-- spy process
-----------------------------------------------------------------------------
sig_spy : process is
begin
init_signal_spy("/DUT/submodule1/submodule2/interesting_signal",
"tb_sig", 1);
wait;
end process sig_spy;
This connects "interesting_signal" to your test bench signal "tb_sig".
This is not synthesizable and you have to consider ModelSim's built in
optimization, which might optimize away the signal you want to look at
during elaboration, but it's a start and works with older VHDL releases.
Doesn't work for GENERICs, though...
HTH,
Sean
Article: 150603On Jan 27, 4:18=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > On Wed, 26 Jan 2011 12:40:54 -0800 (PST), Lou <lciot...@gmail.com> wrote: > >OK. =A0I finally got the display working. =A0WOOO HOOO... > > >Now my understanding is that to get characters on the display I have > >to create a character rom, and a frame buffer. =A0The character rom I > >understand. =A0I plan on making a rom that bisically contains 1's where > >ever a pixel is on for each character. =A0I plan on a 8x8 font. =A0This > >should give me 34 lines with 60 characters. > > >I am a little confused on the frame buffer portion. =A0Any pointers on > >where to look for information on this? > > Your frame buffer holds the character for each display position. Typicall= y using dual port BlockRAM > - a read port feeding data to the display and a write port to update the = display contents. Use > initialisation data to put something in it to start with so you can get t= he display part working > before worrying about the writing to it. > > The buffer read address is derived from your X/Y character position count= s, and the output goes to > the address input of your character ROM to select the character displayed= at each position. The > lower-order addresses of X/Y determine the address within each character = definition. > . Hmmm...I am still lost. All this digital stuff is new to me, and I am trying to learn this as fast as possible. (BTW I am not a student, this is just my hobby, if you can call this a hobby... lol, so I am not looking for homework answers lol... Only been playing with FPGAs for about 1 month) So lets see... I dicided to go with a 6x8 font.. that will give me 80 characters across rather than the 60. (Tell me if this complicates things) My understanding is that the frame buffer will contain all the data for each pixel. So with 480x272 TFT, that is a total of 130560 pixels or bits I have to somehow load into memory. I have a working block for the Character Rom, basically organized as an array of std_logic_vector values for each character, accessed by an address value corresponding to 1 row of pixels (6 bits). Now to get this into the FrameBuffer, I need the following to somehow map these rows of pixels to the correct location. I just can't picture how to store this in RAM, and be easily addressable.Article: 150604
> > First replace the FPGA in this chain with a Cat5 crossover cable >(i.e. >remove the FPGA from the circuit and replace it with the cable (between the >two switches) and see if the packet loss still occurs. If yes, you need to >talk to the switch maintainer(s) to fix their switch (possibly allocating >more buffer space to your ports) and/or check the network settings on the >PCs to make sure they match the settings on the switch (usually auto). If >the loss doesn't occur then you are sure your board is the problem. Next >thing to check is the PHY and switch port configurations. Likely the switch >ports are in auto which means your boards PHYs need to be set to auto. If >the switches are set auto and your board is (of instance) manual 100 full >duplex (i.e. autonegotiation is disabled) then this can happen as the >switches may choose half duplex (they usually get the speed right) which >will cause the packet loss you are seeing. Another good thing to try is ask >the switch owner to check what the ports to the FPGA have negotiated with >the FPGA board in place. That should match what the PHY on your FPGA is set >for or has negotiated (although unless the PHY has status lights it may be >difficult to determine what it has negotiated). In short I think this is >more likely a network configuration problem than an FPGA one. >One last thought, check the settings on the network cards of the two PCs as >well, since they could be set to manual instead of auto (especially if your >board is also set to manual) and work but break when the switches are >added. > >Peter Van Epp > >--------------------------------------- >Posted through http://www.FPGARelated.com > ok i think i have diagnosed the problem to some extent. I captured the packets on chipscope and what i saw was a little surprising at least for me. My rx_data_valid signal coming from PHY was not going low, rather it stayed high. When i googled the gigabit ethernet specs, i came to know about this thing they call " frame burst". In this mode, the transmitter doesn't relinquish the line and keeps on sending some frames back to back. Which makes sense with the thing i am facing i.e. rx_data_valid not going low, which in turn doesn't make my state machines change states, counters not resetting and packets dropping. I maybe wrong, but this is what i have concluded. Any hints would be highly appreciated on this issue. Thanks with warm regards --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150605
Hi, On 01/27/11 07:47 PM, Steve Ravet wrote: > Whenever I see internal tool errors like that I first suspect a quota/full > disk type problem. > > --steve > Dont top post on Usenet. http://www.caliburn.nl/topposting.html Then you should have a better control of your server I think and keep track of usage per day or so. There are tools that can monitor diskuage and alert when you are reaching a critical level. > > "Michael"<michael_laajanen@yahoo.com> wrote in message > news:8qajvpF1l4U1@mid.individual.net... >> Hi, >> >> I am trying a design that is from ISE 9.2 on the latest 12.4 using CentOS >> 64 bit and receive the following error, I can't find anything >> on Xilinx that refers to it. >> >> Anyone seen the same and know a solution? >> >> >> >> INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24 - Number of bytes >> peeked >> does not match number of bytes requested. Corrupted file? > > /michaelArticle: 150606
> I've always thought that it would be nice if FPGA synthesis tools > supported the hierarchical path names too. > i.e. if you wanted to debug a core with chipscope, you could do > > assign trig0[0] = my_core.some_internal_block.troublesome_node; VHDL: I've successfully used signals in packages (global signals) in synthesis (synplify). Declare a signal in a package (I used std_ulogic to try to catch multiple drivers at compile time, but the error(s) came at elaboration...). So at the top entity you "use debug_pkg" and get access to the debug_signal. Just drive it to your output, i.e. debug_pin <= debug_signal; In the lower level entity, also "use debug_pkg" and send your troublesome_node to the debug_signal: debug_signal <= troublesome_node; HTH -- PontArticle: 150607
Lou <lciotti1@gmail.com> wrote: (snip) > So lets see... I dicided to go with a 6x8 font.. that will give me 80 > characters across rather than the 60. (Tell me if this complicates > things) > My understanding is that the frame buffer will contain all the data > for each pixel. So with 480x272 TFT, that is a total of 130560 pixels > or bits I have to somehow load into memory. Tradition, going back many years now, is to do the character ROM lookup on the fly, storing the character codes in RAM. When your PC starts up it will usually be in a character display mode that works that way. > I have a working block for the Character Rom, basically organized as > an array of std_logic_vector values for each character, accessed by an > address value corresponding to 1 row of pixels (6 bits). If you need both characters and graphics on the screen at the same time, though, it is usual to store the character pixels in display RAM. > Now to get this into the FrameBuffer, I need the following to somehow > map these rows of pixels to the correct location. I just can't > picture how to store this in RAM, and be easily addressable. -- glenArticle: 150608
I'm trying to simulate the GTX SerDes, I've tried both NCverilog and Questa. The outputs of the GTXE1 model are all tristate, is there a trick to simulating the V6 SerDes models?Article: 150609
On Thu, 27 Jan 2011 06:22:19 -0800 (PST), rickman wrote:
> Now I am learning how Verilog
>allows hierarchical path references to signals for test benches. This
>is awesome!!!
Not as awesome as the ability to call tasks
(procedures) in a module, from another module.
That's just the neatest thing ever, for
stimulus generation. This little example
should give you a flavour of what you can do:
`timescale 1ns/1ns
module simulatedUartTransmitter(output reg TxD);
time bitTime;
//
task setBitTime(input time newBitTime);
bitTime = newBitTime;
endtask
task sendChar(input [7:0] char);
begin
// send start bit
TxD = 0;
// send eight data bits, LSB first
repeat (8) begin
#(bitTime) TxD = char[0];
char = char >> 1;
end
// send stop bit
#(bitTime) TxD = 1;
#(bitTime);
end
endtask
//
initial TxD = 1; // line idles in "Mark" state
//
endmodule
module justTryThisOne;
// connections
wire serial_TxD;
// stimulus generator instance
simulatedUartTransmitter txGenerator(.TxD(serial_TxD));
//
// There's no DUT in this example, but you can still
// see the signal generator at work.
//
// code to generate some stimulus
initial begin
txGenerator.setBitTime(104000); // 9600Bd, roughly
#1_000_000; // idle awhile before starting
txGenerator.sendChar("h"); // ask the sig-gen...
txGenerator.sendChar("i"); // ...to send some data
txGenerator.sendChar("!"); // ...at our request
#1_000_000; // idle awhile at the end
end
endmodule
Utterly fantastic when you want to do stuff like
mimicking the behaviour of a CPU in your testbench.
Just write a module that can generate read or write
cycles on a bus, then connect an instance of it to
your DUT and get it to do accesses in the same way
you'd expect your CPU to behave.
Apologies if this is stuff you've seen already.
It's so useful that I couldn't resist sharing
the example (again).
--
Jonathan Bromley
Article: 150610On Thu, 27 Jan 2011 08:18:26 -0800, "Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:e2k1k61umef17laprla8cmb0j7garppgdj@4ax.com... >> Here, severance is voluntary on the employer's part; one week per year >> is common but not mandatory. > >My (limited) experienced is that for "regular" employees, one week per year is >common... but for "executives" often six months to one year is common, despite >their tenure and despite how much they personally were responsible for fouling >things up. :-) At IBM the common rule was one week per year, up to 26 weeks, with a minimum of eight weeks. At one time, depending on the layoff, it was one or two weeks per year and up to two years (that ended pretty quickly, though). I got the 26 weeks when I left. ...in addition to the pension. Bastards wouldn't give me unemployment, though. ;-) In my current job the severance is zero. >> Employees usually don't het severance if >> they quit, and may not if they are fired for cause. > >Heck, some scummy employers tend to hold onto an employee's last paycheck if >the employee leaves under bad terms; they know that most employees are gonig >to be busy looking for another job and likely won't have the time and/or money >to pursue getting it in court. In many states there is no need to go to court. The state labor board will thump them *hard* for pulling that crap. >> We are required to >> pay an employee for any unused vacation time. > >Right, since it's "their" time. AIUI this is the reason many companies cap >vacation time at, e.g., 4 weeks -- they don't want employees building up a >little $100k "vacation cash" fund that tends to look bad on the books. Exactly. That "fund" also gets any raises. We're only allowed to roll over eleven days.Article: 150611
Hi, I am using Xilinx Virtex II Pro device to generate some programmable delays which can be as close to each other as possible with good linearity between the delays obtained against the input setting. For each increment in the input setting, the delay blocks are designed such that the return path of the signal is delayed by two MUX and two inverters each time. Each of my delay block contains one inverter in upper path and closes the loop to the previous stage with one inverters and and one MUX in its feedback stage. The following picture illustrates that. http://picasaweb.google.com/pratap.iisc/Pravas#5567043899536627202 Now the problem I am facing is that, when i do the P&R of the circuit of 10 stages, it places the individual delay stages all around the FPGA board resulting in huge delays between adjacent digital control codes along with non-linearity in the out put delays. If I could some how instruct the tool to place the delay cells(I feel each of them being so small can be fit into a single slice) adjacent to each other in slice level I hope to get lesser delay and better linearity. Can anybody help me with how exactly to go about it? I saw some options like RLOC which can help in placing a single net into a particular slice in FPGA. But am not sure whether it can help me in placing all my ten delay element blocks adjacent to each other? Hoping for some constructive solution, Thanks in advance. PratapArticle: 150612
Newb question: suppose I want to create a shift register that's clocked from an external source (like an SPI slave device). My impression (correct me if I'm confused) is that if the external clock is slow WRT some other clock on the FPGA (e.g. a 1MHz external clock and a 50MHz fast clock), I can sync both clock and data to the fast clock and proceed from there, using the fast clock along with an edge detected signal for further processing. The fast clock is mapped to low-skew clock lines which are designed for the purpose, so things are good. But what if the clock is not slow WRT the fast clock? What if the external clock is too fast to reliably sync with the fast clock? e.g. a 20MHz clock and a 50MHz fast clock. In that case it seems that the external clock needs to be used directly, but won't there be potential clock skew problems using a regular input as a clock? I'd appreciate insight on how such problems are dealt with, if indeed they are even problems at all. MikeArticle: 150613
Pratap <pratap.iisc@gmail.com> wrote: > Hi, > I am using Xilinx Virtex II Pro device to generate some programmable > delays which can be as close to each other as possible with good > linearity between the delays obtained against the input setting. For > each increment in the input setting, the delay blocks are designed > such that the return path of the signal is delayed by two MUX and two > inverters each time. Each of my delay block contains one inverter in > upper path and closes the loop to the previous stage with one > inverters and and one MUX in its feedback stage. The following picture > illustrates that. > http://picasaweb.google.com/pratap.iisc/Pravas#5567043899536627202 > Now the problem I am facing is that, when i do the P&R of the circuit > of 10 stages, it places the individual delay stages all around the > FPGA board resulting in huge delays between adjacent digital control > codes along with non-linearity in the out put delays. If I could some > how instruct the tool to place the delay cells(I feel each of them > being so small can be fit into a single slice) adjacent to each other > in slice level I hope to get lesser delay and better linearity. Can > anybody help me with how exactly to go about it? > I saw some options like RLOC which can help in placing a single net > into a particular slice in FPGA. But am not sure whether it can help > me in placing all my ten delay element blocks adjacent to each other? > Hoping for some constructive solution, > Thanks in advance. > Pratap Assuming you are using ISE, you can use the post synthesis floor planning tool to create location constraints. This is a quick and dirty way that I've used in the past.Article: 150614
Pratap <pratap.iisc@gmail.com> wrote: (snip) > Now the problem I am facing is that, when i do the P&R of the circuit > of 10 stages, it places the individual delay stages all around the > FPGA board resulting in huge delays between adjacent digital control > codes along with non-linearity in the out put delays. If I could some > how instruct the tool to place the delay cells(I feel each of them > being so small can be fit into a single slice) adjacent to each other > in slice level I hope to get lesser delay and better linearity. Can > anybody help me with how exactly to go about it? There used to be an option called RPM, Relationally Placed Macros. You describe a block of CLBs and their connections. P&R places the whole block, including the routes defined in the block, and then routes to and from the block, as needed. I don't know if newer tools support it, though. -- glenArticle: 150615
On 27 Jan 2011 22:19:01 GMT, General Schvantzkoph <schvantzkoph@yahoo.com> wrote: >I'm trying to simulate the GTX SerDes, I've tried both NCverilog and >Questa. The outputs of the GTXE1 model are all tristate, is there a trick >to simulating the V6 SerDes models? Are you resetting it? Is the clock input good? Is the data input good? -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150616
On Jan 27, 10:12=A0pm, KK6GM <mjsi...@scriptoriumdesigns.com> wrote: > > But what if the clock is not slow WRT the fast clock? =A0What if the > external clock is too fast to reliably sync with the fast clock? =A0e.g. > a 20MHz clock and a 50MHz fast clock. =A0In that case it seems that the > external clock needs to be used directly, but won't there be potential > clock skew problems using a regular input as a clock? =A0I'd appreciate > insight on how such problems are dealt with, if indeed they are even > problems at all. > They are a problem that in many cases is dealt with using a dual clock fifo. KJArticle: 150617
On 28 Jan., 04:12, KK6GM <mjsi...@scriptoriumdesigns.com> wrote: > Newb question: suppose I want to create a shift register that's > clocked from an external source (like an SPI slave device). =A0My > impression (correct me if I'm confused) is that if the external clock > is slow WRT some other clock on the FPGA (e.g. a 1MHz external clock > and a 50MHz fast clock), I can sync both clock and data to the fast > clock and proceed from there, using the fast clock along with an edge > detected signal for further processing. =A0The fast clock is mapped to > low-skew clock lines which are designed for the purpose, so things are > good. > > But what if the clock is not slow WRT the fast clock? =A0What if the > external clock is too fast to reliably sync with the fast clock? =A0e.g. > a 20MHz clock and a 50MHz fast clock. =A0In that case it seems that the > external clock needs to be used directly, but won't there be potential > clock skew problems using a regular input as a clock? =A0I'd appreciate > insight on how such problems are dealt with, if indeed they are even > problems at all. > > Mike Hi Mike, you asked "...how such problems are dealt with,...". The answer is : "Very carefully.". :-) When it happens that a design really needs some clock routed trough ordinary routing ressources, the problems you mentioned apply. So the designer has to make sure that the net stays as small as possible, and tries to controll it with tight timing constraints. If you take a look at some DDR Memory controller implementation you will see how it's done. There you have a strobe signal, that's used to clock the data from the RAM into the FPGA FFS (here mostly IDDR2 FFs inside the IOBs) Now this really happens at high speed. But the next FF stage already works with the internal clock. and then it's business as usual. Have a nice synthesis EilertArticle: 150618
I must constrain also the input FF, must I? Is it written in the holy bible? why should I add other constraints to create confusion when the IO are already constrained with OFFSET I/O and in the unconstrained timing report there is no sign of one of this i/Os already constrained? Suppose that I constrain each and every I/O FF and it does not work. which is the next advice? Try to constrain AREA of each block? Xilinx says: constrain the design as less as possible, thus I think that add more constraints is the wrong way until I don't have figured out what the hell is going on here. I will repeat to myself my questions, here, just to keep then in mind: IF the period/offset constraint are MET, WHY should I constrain also the INPUT FF PATH? WHY if I modify slightly the code, or the ISE properties, the system CHANGE BEHAVIOUR? WHY in another projects (SPARTAN 2 SPARTAN 3A) my VHDL style of programming is working correctly WITHOUT ANY CONSTRAIN AT THE SAME CLOCK SPEED? Best EmanueleArticle: 150619
On Thu, 27 Jan 2011 11:57:18 -0800 (PST), Lou <lciotti1@gmail.com> wrote: >On Jan 27, 4:18 am, Mike Harrison <m...@whitewing.co.uk> wrote: >> On Wed, 26 Jan 2011 12:40:54 -0800 (PST), Lou <lciot...@gmail.com> wrote: >> >OK. I finally got the display working. WOOO HOOO... >> >> >Now my understanding is that to get characters on the display I have >> >to create a character rom, and a frame buffer. The character rom I >> >understand. I plan on making a rom that bisically contains 1's where >> >ever a pixel is on for each character. I plan on a 8x8 font. This >> >should give me 34 lines with 60 characters. >> >> >I am a little confused on the frame buffer portion. Any pointers on >> >where to look for information on this? >> >> Your frame buffer holds the character for each display position. Typically using dual port BlockRAM >> - a read port feeding data to the display and a write port to update the display contents. Use >> initialisation data to put something in it to start with so you can get the display part working >> before worrying about the writing to it. >> >> The buffer read address is derived from your X/Y character position counts, and the output goes to >> the address input of your character ROM to select the character displayed at each position. The >> lower-order addresses of X/Y determine the address within each character definition. >> . > >Hmmm...I am still lost. All this digital stuff is new to me, and I am >trying to learn this as fast as possible. (BTW I am not a student, >this is just my hobby, if you can call this a hobby... lol, so I am >not looking for homework answers lol... Only been playing with FPGAs >for about 1 month) > >So lets see... I dicided to go with a 6x8 font.. that will give me 80 >characters across rather than the 60. (Tell me if this complicates >things) > >My understanding is that the frame buffer will contain all the data >for each pixel. So with 480x272 TFT, that is a total of 130560 pixels >or bits I have to somehow load into memory. > >I have a working block for the Character Rom, basically organized as >an array of std_logic_vector values for each character, accessed by an >address value corresponding to 1 row of pixels (6 bits). > >Now to get this into the FrameBuffer, I need the following to somehow >map these rows of pixels to the correct location. I just can't >picture how to store this in RAM, and be easily addressable. You need to decide if you just want a text display, or text+graphics. The latter needs much more buffer RAM, possibly more than you have in the FPGA, so I suggest starting with the former. For text only, the RAM buffer would be 34x60 bytes. It will make things easier if you round this up to binary multiples, e.g. 64x64 and have some unused areas. Similarly if your font data is stored as 8x8 it will simplify addressing, as you can split the address bus between character number and row/pixel within the character. Most FPGA Blockram/ROM can be configured as different widths on each port - configuring the output port as 1 bit wide means it does the pixel serialisation for you. Assuming your character ROM has 256 8x8 characters, that needs a 256x8x8 x1 bit ROM, which will have 14 address inputs. These would be allocated as follows A0..2 : from horizontal counter bits 0..2 A3..5 : from row counter bits 0..2 A6..13 character number from display RAM data out Data out is your pixel data Assuming a 64x64 x8 bit character RAM buffer, this has 12 address lines A0-5 from horizontal counter bits 3..8 A6..11 from row counter bits 3..8 Note this assumes row,column counters start at 0,0 for first pixel - this makes things easier, so it's worth juggling the sync generation to make it work like that. Alternatively use seperate counters for addressing and sync generationArticle: 150620
FYI : xilinx grenoble is ( was ) involved with XST software xilinx bought IST in 99, which was founded 20 years ago, for its synthesis tool knowledge http://www.techfocusmedia.net/archives/articles/20110104-elephant/ On Jan 28, 1:24=A0am, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> wrote: > On Thu, 27 Jan 2011 08:18:26 -0800, "Joel Koltner" > > <zapwireDASHgro...@yahoo.com> wrote: > >"John Larkin" <jjlar...@highNOTlandTHIStechnologyPART.com> wrote in mess= age > >news:e2k1k61umef17laprla8cmb0j7garppgdj@4ax.com... > >> Here, severance is voluntary on the employer's part; one week per year > >> is common but not mandatory. > > >My (limited) experienced is that for "regular" employees, one week per y= ear is > >common... but for "executives" often six months to one year is common, d= espite > >their tenure and despite how much they personally were responsible for f= ouling > >things up. :-) > > At IBM the common rule was one week per year, up to 26 weeks, with a mini= mum > of eight weeks. =A0At one time, depending on the layoff, it was one or tw= o weeks > per year and up to two years (that ended pretty quickly, though). =A0I go= t the > 26 weeks when I left. =A0...in addition to the pension. =A0Bastards would= n't give > me unemployment, though. =A0;-) > > In my current job the severance is zero. > > >> Employees usually don't het severance if > >> they quit, and may not if they are fired for cause. > > >Heck, some scummy employers tend to hold onto an employee's last paychec= k if > >the employee leaves under bad terms; they know that most employees are g= onig > >to be busy looking for another job and likely won't have the time and/or= money > >to pursue getting it in court. > > In many states there is no need to go to court. =A0The state labor board = will > thump them *hard* for pulling that crap. > > >> We are required to > >> pay an employee for any unused vacation time. > > >Right, since it's "their" time. =A0AIUI this is the reason many companie= s cap > >vacation time at, e.g., 4 weeks -- they don't want employees building up= a > >little $100k "vacation cash" fund that tends to look bad on the books. > > Exactly. =A0That "fund" also gets any raises. =A0We're only allowed to ro= ll over > eleven days.Article: 150621
I would of thought that coregen would create a simulation testbench for you which would just work. Have you not tried that? Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150622
Thank you for the information.
So this is what I have for the Character ROM (Contains each character
pixel information)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity CharacterRom is
port (clk : in std_logic;
address : in std_logic_vector(10 downto 0);
data: out std_logic_vector (7 downto 0));
end CharacterRom;
architecture Behavioral of CharacterRom is
signal addr_reg: std_logic_vector(10 downto 0);
type rom_type is array (0 to 2047)
of std_logic_vector(7 downto 0);
constant ROM : rom_type := ( X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", -- Char 000
------------------------------------- BIG SNIP
---------------------------------------------------------------------------------------------------------
X"00", X"00",
X"00", X"3C", X"3C", X"3C", X"3C", X"00", -- Char 254
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); --
Char 255
begin
process (clk)
begin
if (clk'event and clk = '1') then
addr_reg <= address;
end if;
end process;
data <= ROM(to_integer(unsigned(addr_reg)));
end Behavioral;
Am I on the right track?
Article: 150623On Jan 27, 10:12=A0pm, KK6GM <mjsi...@scriptoriumdesigns.com> wrote: > Newb question: suppose I want to create a shift register that's > clocked from an external source (like an SPI slave device). =A0My > impression (correct me if I'm confused) is that if the external clock > is slow WRT some other clock on the FPGA (e.g. a 1MHz external clock > and a 50MHz fast clock), I can sync both clock and data to the fast > clock and proceed from there, using the fast clock along with an edge > detected signal for further processing. =A0The fast clock is mapped to > low-skew clock lines which are designed for the purpose, so things are > good. > > But what if the clock is not slow WRT the fast clock? =A0What if the > external clock is too fast to reliably sync with the fast clock? =A0e.g. > a 20MHz clock and a 50MHz fast clock. =A0In that case it seems that the > external clock needs to be used directly, but won't there be potential > clock skew problems using a regular input as a clock? =A0I'd appreciate > insight on how such problems are dealt with, if indeed they are even > problems at all. > > Mike 20 MHz and 50 MHz are totally compatible in this regard. The "slow" is not too fast until it is 1/2 the rate of the fast clock or more. As long as you can sample at least once, both the high and the low value of the clock you should be able to detect the edge. You do need a little more margin than exactly 2X because of the variability in timing between the clock and the data. So this needs to be modified to say that the sample that detects the active edge of the clock has to be assured to happen when data is valid too. That will depend on the setup and hold times of the incoming data. If you don't have compatibility in clock rates, then you need to capture the incoming data using the incoming clock and once you have done the work of serializing it, the resulting data sample rate is much slower and can be transferred using the standard techniques to cross clock domains. The use of a FIFO is required only when you need to cross clock domains that are nearly equal or the FROM domain is faster than the TO domain (Even then the FIFO is only needed if the data rate is more than 1/2 the TO domain clock rate). I tend to avoid using FIFOs just because they are a bit heavy handed. The other techniques are much smaller and simpler. I honestly can't remember the last time I used a FIFO just to cross clock domains. RickArticle: 150624
On Jan 28, 3:07=A0am, Emanuele83 <emanuele83katam...@googlemail.com> wrote: > I must constrain also the input FF, must I? Is it written in the holy bib= le? > why should I add other constraints to create confusion when the IO are al= ready constrained with OFFSET I/O and in the unconstrained timing report th= ere is no sign of one of this i/Os already constrained? > Suppose that I constrain each and every I/O FF and it does not work. whic= h is the next advice? Try to constrain AREA of each block? > Xilinx says: constrain the design as less as possible, thus I think that = add more constraints is the wrong way until I don't have figured out what t= he hell is going on here. > > I will repeat to myself my questions, here, just to keep then in mind: > IF the period/offset constraint are MET, WHY should I constrain also the = INPUT FF PATH? > WHY if I modify slightly the code, or the ISE properties, the system CHAN= GE BEHAVIOUR? > WHY in another projects (SPARTAN 2 SPARTAN 3A) my VHDL style of programmi= ng is working correctly WITHOUT ANY CONSTRAIN AT THE SAME CLOCK SPEED? > > Best > Emanuele How do you know that your problem is a timing constraint problem? There are many, many problems that can cause the symptoms you are seeing. How do you know that it is not a hardware problem? You've already found one hardware problem. How do you know it isn't a design problem such as a bad clock domain crossing? Why are you so focused on the idea that the tools are messing up your design? So far I can't tell that you have tried any of my other advice. Rick
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