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PovTruffe <PovTache@gaga.invalid> wrote: > "Allan Herriman" <allanherriman@hotmail.com> a ?crit : > > - A USB to JTAG programming dongle built-in, probably using something > > like an FT2232H or FT232H. > > - Open source host driver software for the built-in JTAG programming > > hardware, with binaries available for at least WinXP, Win7 and major > > flavours of Linux. > What are the advantages of using this chip compared to using the > manufacturer USB cable ? Better behaviour of the connections at high speed, no ringing caused by the connecting cable. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 151401
On Apr 1, 12:43=A0am, allen <ayho...@gmail.com> wrote: > Hey guys, > > I work in the FPGA development kit sector, and I was just looking to > see if you guys had any ideas regarding what would be your MUST HAVE > features on an FPGA dev kit? > > Thanks in advance! > Allen Keep the number of JTAG devices to three or less. FPGA, PROM and maybe something else (CPLD or other FPGA?). The free jtag software limits you to 3 JTAG devices, so i have to pay after that. Thanks! RichArticle: 151402
Maybe it is possible to get a brochure or a photo with explanations? "John Adair" <g1@enterpoint.co.uk> wrote in message news:4880f1b1-b7f2-42c4-93e8-e365e06cf37e@x1g2000yqb.googlegroups.com... Much delayed but will hopefully be actually be on show at ESC Silicon Valley in May our Raggedstone3 will have most of this for you. John Adair Enterpoint Ltd.Article: 151403
On Mar 31, 10:12=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > I've run into a bit of a problem. A camera module I would like to use > has a MIPI CSI-2 interface. The SoC I want to connect to only has a > parallel camera interface. How difficult would it be to use an FPGA in > between? Or are there already MIPI to parallel converters? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- As far as I know, the only thing that prevents you of using the CSI-2 protocol is the clocking frequency of the serial lane. CSI-2 has quite a lot of generic features that are defined. All of them need not be supported. If your clocking is within 300MHz, I think a Xilinx FPGA can easily de-serialize this stream. Each lane in the CSI-2 specification serializes a byte and transmits to the receiver. So the first thing which one would require is a clock recovery on the clock lane which can be implemented using a DDR flop(IDELAY) can be used to centre the clocking to the data and a de-serializer working at line rate. Post serialization, that has to be a packet processing/parsing state machine which runs on a byte wise basis which shall run at a frequency equal to ([line rate / 8]*Lane Width). Hence the internal processing logic always runs at much slower speed as compared to CSI-2 serial lines. Then there are packet formats that are to be supported. Some of them have the SOF. EOF, SOL, EOL packet headers aligned to generate precise HS and VS timing signals. Some of the CSI-2 specs do not. If the timing signals are not defined by these SOF EOF SOL EOL fields, then a frame buffer might be required to video rendering. In a simplest set-up these signals can be directly used as HS and VS signals for display driving!. CSI-2 also specifies virtual channels to interleave video data, which when used again requires frame buffering since it spoils HS VS timing in the incoming data stream. Additionally, the CSI-2 interface also consists of a CCI (Camera Configuration Interface) which is used to configure the camera parameters. This interface is just a simple I2C bus interface which are used to program configuration registers of the camera. The register bit map can be easily found from the camera datasheet. On the whole, I do not think it is a difficult task to implement the receiver in the FPGA if you have a relatively good FPGA(as far as timing and logic is concerned). Thanks ShyamArticle: 151404
Not much I can disclose at the point other than it will be the same theme as our Xilinx based Raggedstone1 and Raggedstone2. It's a logical extension of the family so no real secrets there. If all goes to schedule there will be a formal announcement a couple days before ESC along with everything else for the show that we manage to complete before then. John Adair Enterpoint Ltd. On Apr 2, 11:29=A0pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > Maybe it is possible to get a brochure or a photo with explanations? > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:4880f1b1-b7f2-42c4-93e8-e365e06cf37e@x1g2000yqb.googlegroups.com... > Much delayed but will hopefully be actually be on show at ESC Silicon > Valley in May our Raggedstone3 will have most of this for you. > > John Adair > Enterpoint Ltd.Article: 151405
On Apr 2, 2:25=A0pm, Rich <r.newk...@juno.com> wrote: > On Apr 1, 12:43=A0am, allen <ayho...@gmail.com> wrote: > > > Hey guys, > > > I work in the FPGA development kit sector, and I was just looking to > > see if you guys had any ideas regarding what would be your MUST HAVE > > features on an FPGA dev kit? > > > Thanks in advance! > > Allen > > Keep the number of JTAG devices to three or less. =A0FPGA, PROM and > maybe something else (CPLD or other FPGA?). =A0The free jtag software > limits you to 3 JTAG devices, so i have to pay after that. > > Thanks! > Rich Rich, I dont understand this requirement. The PCBs will be tested before you get them. Probably with JTAG/Boundary-scan. Then all you need is the FPGA software, which is free, to program the development kit, and vendor JTAG pod. Regards, JoeArticle: 151406
shyam <mail.ghanashyam.prabhu@gmail.com> wrote: >On Mar 31, 10:12=A0pm, n...@puntnl.niks (Nico Coesel) wrote: >> I've run into a bit of a problem. A camera module I would like to use >> has a MIPI CSI-2 interface. The SoC I want to connect to only has a >> parallel camera interface. How difficult would it be to use an FPGA in >> between? Or are there already MIPI to parallel converters? >> >> -- > >As far as I know, the only thing that prevents you of using the CSI-2 >protocol is the clocking frequency of the serial lane. > >CSI-2 has quite a lot of generic features that are defined. All of >them need not be supported. If your clocking is within 300MHz, I think >a Xilinx FPGA can easily de-serialize this stream. Each lane in the >CSI-2 specification serializes a byte and transmits to the receiver. >So the first thing which one would require is a clock recovery on the >clock lane which can be implemented using a DDR flop(IDELAY) can be >used to centre the clocking to the data and a de-serializer working at >line rate. I guess using the DPLL and use the clock delay line is also an option. I'm surprised Xilinx has no appnote on MIPI. >Post serialization, that has to be a packet processing/parsing state >machine which runs on a byte wise basis which shall run at a frequency >equal to ([line rate / 8]*Lane Width). Hence the internal processing >logic always runs at much slower speed as compared to CSI-2 serial >lines. >On the whole, I do not think it is a difficult task to implement the >receiver in the FPGA if you have a relatively good FPGA(as far as >timing and logic is concerned). If only I had access to the MIPI specs before paying the fee... I'd hate to findout I wasted thousands of dollars for nothing. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151407
Hm, any plans with Altera FPGAs? "John Adair" <g1@enterpoint.co.uk> wrote in message news:ba2f7258-d9ee-4da0-9438-320636c71fb8@s33g2000vbb.googlegroups.com... Not much I can disclose at the point other than it will be the same theme as our Xilinx based Raggedstone1 and Raggedstone2. It's a logical extension of the family so no real secrets there. If all goes to schedule there will be a formal announcement a couple days before ESC along with everything else for the show that we manage to complete before then. John Adair Enterpoint Ltd. On Apr 2, 11:29 pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > Maybe it is possible to get a brochure or a photo with explanations? > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:4880f1b1-b7f2-42c4-93e8-e365e06cf37e@x1g2000yqb.googlegroups.com... > Much delayed but will hopefully be actually be on show at ESC Silicon > Valley in May our Raggedstone3 will have most of this for you. > > John Adair > Enterpoint Ltd.Article: 151408
Raggedstone3 is Altera based. John Adair Enterpoint Ltd. On Apr 3, 6:06=A0pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > Hm, any plans with Altera FPGAs? > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:ba2f7258-d9ee-4da0-9438-320636c71fb8@s33g2000vbb.googlegroups.com... > Not much I can disclose at the point other than it will be the same > theme as our Xilinx based Raggedstone1 and Raggedstone2. It's a > logical extension of the family so no real secrets there. If all goes > to schedule there will be a formal announcement a couple days before > ESC along with everything else for the show that we manage to complete > before then. > > John Adair > Enterpoint Ltd. > > On Apr 2, 11:29 pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > > > Maybe it is possible to get a brochure or a photo with explanations? > > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > >news:4880f1b1-b7f2-42c4-93e8-e365e06cf37e@x1g2000yqb.googlegroups.com... > > Much delayed but will hopefully be actually be on show at ESC Silicon > > Valley in May our Raggedstone3 will have most of this for you. > > > John Adair > > Enterpoint Ltd.Article: 151409
Great, can't wait to see! :) "John Adair" <g1@enterpoint.co.uk> wrote in message news:59aa7f47-7ab5-4dbd-9e9a-6d8b05ee1b52@d19g2000yql.googlegroups.com... Raggedstone3 is Altera based. John Adair Enterpoint Ltd.Article: 151410
On Apr 3, 10:09=A0am, n...@puntnl.niks (Nico Coesel) wrote: > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > >On Mar 31, 10:12=3DA0pm, n...@puntnl.niks (Nico Coesel) wrote: > >> I've run into a bit of a problem. A camera module I would like to use > >> has a MIPI CSI-2 interface. The SoC I want to connect to only has a > >> parallel camera interface. How difficult would it be to use an FPGA in > >> between? Or are there already MIPI to parallel converters? > > >> -- > > >As far as I know, the only thing that prevents you of using the CSI-2 > >protocol is the clocking frequency of the serial lane. > > >CSI-2 has quite a lot of generic features that are defined. All of > >them need not be supported. If your clocking is within 300MHz, I think > >a Xilinx FPGA can easily de-serialize this stream. Each lane in the > >CSI-2 specification serializes a byte and transmits to the receiver. > >So the first thing which one would require is a clock recovery on the > >clock lane which can be implemented using a DDR flop(IDELAY) can be > >used to centre the clocking to the data and a de-serializer working at > >line rate. > > I guess using the DPLL and use the clock delay line is also an option. > I'm surprised Xilinx has no appnote on MIPI. > Basically it is a paid specification, so Xilinx would not disclose things on its app notes. Xilinx has IDELAY primitives which are very effective in centering data and controlling calculated skew/ delay on data/clocking lines. (it has both fine grain and coarse grain adjustments I suppose) at around 7.5 may be. Not really sure. (256 taps on a 200MHz clock) > >Post serialization, that has to be a packet processing/parsing state > >machine which runs on a byte wise basis which shall run at a frequency > >equal to ([line rate / 8]*Lane Width). Hence the internal processing > >logic always runs at much slower speed as compared to CSI-2 serial > >lines. > >On the whole, I do not think it is a difficult task to implement the > >receiver in the FPGA if you have a relatively good FPGA(as far as > >timing and logic is concerned). > > If only I had access to the MIPI specs before paying the fee... I'd > hate to findout I wasted thousands of dollars for nothing. > If you have the camera receiver, I do not think you ll require MIPI specification. You just have to build the receiver according to the datasheet information from the MIPI trasmitter :) I have the specification but I cannot share it with you > -- > Failure does not prove something is impossible, failure simplymanaging > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > --------------------------------------------------------------Article: 151411
shyam <mail.ghanashyam.prabhu@gmail.com> wrote: >On Apr 3, 10:09=A0am, n...@puntnl.niks (Nico Coesel) wrote: >> shyam <mail.ghanashyam.pra...@gmail.com> wrote: >> >On Mar 31, 10:12=3DA0pm, n...@puntnl.niks (Nico Coesel) wrote: >> >> I've run into a bit of a problem. A camera module I would like to use >> >> has a MIPI CSI-2 interface. The SoC I want to connect to only has a >> >> parallel camera interface. How difficult would it be to use an FPGA in >> >> between? Or are there already MIPI to parallel converters? >> >> >> -- >> >> >As far as I know, the only thing that prevents you of using the CSI-2 >> >protocol is the clocking frequency of the serial lane. >> >> >CSI-2 has quite a lot of generic features that are defined. All of >> >them need not be supported. If your clocking is within 300MHz, I think >> >a Xilinx FPGA can easily de-serialize this stream. Each lane in the >> >CSI-2 specification serializes a byte and transmits to the receiver. >> >So the first thing which one would require is a clock recovery on the >> >clock lane which can be implemented using a DDR flop(IDELAY) can be >> >used to centre the clocking to the data and a de-serializer working at >> >line rate. >> >> I guess using the DPLL and use the clock delay line is also an option. >> I'm surprised Xilinx has no appnote on MIPI. >> > >Basically it is a paid specification, so Xilinx would not disclose >things on its app notes. Xilinx has IDELAY primitives which are very >effective in centering data and controlling calculated skew/ delay on >data/clocking lines. (it has both fine grain and coarse grain >adjustments I suppose) at around 7.5 may be. Not really sure. (256 >taps on a 200MHz clock) IIRC thats Virtex or Spartan 6. >> >Post serialization, that has to be a packet processing/parsing state >> >machine which runs on a byte wise basis which shall run at a frequency >> >equal to ([line rate / 8]*Lane Width). Hence the internal processing >> >logic always runs at much slower speed as compared to CSI-2 serial >> >lines. >> >On the whole, I do not think it is a difficult task to implement the >> >receiver in the FPGA if you have a relatively good FPGA(as far as >> >timing and logic is concerned). >> >> If only I had access to the MIPI specs before paying the fee... I'd >> hate to findout I wasted thousands of dollars for nothing. >> >If you have the camera receiver, I do not think you ll require MIPI >specification. You just have to build the receiver according to the >datasheet information from the MIPI trasmitter :) I have the Any pointers to such datasheets? I have the datasheet for the camera module but its author had a really lazy day. >specification but I cannot share it with you I know, but maybe you know an unofficial source. Many specifications have leaked onto the internet. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151412
On Apr 3, 9:55=A0am, JoeP <joe.parke...@yahoo.com> wrote: > On Apr 2, 2:25=A0pm, Rich <r.newk...@juno.com> wrote: > > > > > > > On Apr 1, 12:43=A0am, allen <ayho...@gmail.com> wrote: > > > > Hey guys, > > > > I work in the FPGA development kit sector, and I was just looking to > > > see if you guys had any ideas regarding what would be your MUST HAVE > > > features on an FPGA dev kit? > > > > Thanks in advance! > > > Allen > > > Keep the number of JTAG devices to three or less. =A0FPGA, PROM and > > maybe something else (CPLD or other FPGA?). =A0The free jtag software > > limits you to 3 JTAG devices, so i have to pay after that. > > > Thanks! > > Rich > > Rich, > I dont understand this requirement. =A0The PCBs will be tested before > you get them. =A0Probably with JTAG/Boundary-scan. =A0Then all you need i= s > the FPGA software, which is free, to program the development kit, and > vendor JTAG pod. > > Regards, > Joe- Hide quoted text - > > - Show quoted text - Joe, I know the boards are tested. I use these boards for development and validation of small re-usable IP blocks. The IP blocks have internal JTAG accessible registers. The free JTAG software I'm using is from: http://www.intellitech.com/jtag/free-jtag-software-ijtag.asp . It lets me describe the registers and I can make TCL/TK scripts to operate the IP via JTAG. It's commercial quality software like their $15K packages, just they limit you to three devices in the chain for the free version. This enough for me and to provide a free jtag tool to my customers when the project is complete. It only works with Xilinx USB cable and VCS. Unfortunately I dont use VCS as that is outside of my budget too. There is a nice tutorial on the link using the Xilinx spartan starter kit. Enjoy! RichArticle: 151413
On Apr 4, 10:42=A0am, Rich <r.newk...@juno.com> wrote: > On Apr 3, 9:55=A0am, JoeP <joe.parke...@yahoo.com> wrote: > > > > > > > On Apr 2, 2:25=A0pm, Rich <r.newk...@juno.com> wrote: > > > > On Apr 1, 12:43=A0am, allen <ayho...@gmail.com> wrote: > > > > > Hey guys, > > > > > I work in the FPGA development kit sector, and I was just looking t= o > > > > see if you guys had any ideas regarding what would be your MUST HAV= E > > > > features on an FPGA dev kit? > > > > > Thanks in advance! > > > > Allen > > > > Keep the number of JTAG devices to three or less. =A0FPGA, PROM and > > > maybe something else (CPLD or other FPGA?). =A0The free jtag software > > > limits you to 3 JTAG devices, so i have to pay after that. > > > > Thanks! > > > Rich > > > Rich, > > I dont understand this requirement. =A0The PCBs will be tested before > > you get them. =A0Probably with JTAG/Boundary-scan. =A0Then all you need= is > > the FPGA software, which is free, to program the development kit, and > > vendor JTAG pod. > > > Regards, > > Joe- Hide quoted text - > > > - Show quoted text - > > Joe, > I know the boards are tested. =A0I use these boards for development and > validation of small re-usable IP blocks. =A0The IP blocks have internal > JTAG accessible registers. =A0The free JTAG software I'm using is from:ht= tp://www.intellitech.com/jtag/free-jtag-software-ijtag.asp. > It lets me describe the registers and I can make TCL/TK scripts to > operate the IP via JTAG. =A0 It's commercial quality software like their > $15K packages, just they limit you to three devices in the chain for > the free version. This enough for me and to provide a free jtag tool > to my customers when the project is complete. > It only works with Xilinx USB cable and VCS. =A0Unfortunately I dont use > VCS as that is outside of my budget too. > There is a nice tutorial on the link using the Xilinx spartan starter > kit. > > Enjoy! > Rich- Hide quoted text - > > - Show quoted text - OK, thanks Rich. I havent done anything like that, but I am taking a look at the JTAG Spartan starter kit step-by-step document they have. I think we are off topic at this point, but thanks, I learned something new. JoeArticle: 151414
On Mon, 20 Aug 2007 13:49:01 +0000, young wrote: "Patrick Dubois" <prdub...@gmail.com> writes: > Just to come back on the subject of Scons for a minute... Any input on > that tool? Or does anyone have another suggestion for a make > alternative? > > In a very-belated follow up: I've been using SCons for building projects in Xilinx ISE (12.2), and I find it to be pretty suitable. Tasks like extracting build options and dependencies from project files are quite manageable, at least with the newer XML-based .xise files. I've uploaded an example SConstruct on Github here: https://github.com/ewa/xilinx-build-scripts . I'd love to see people use and improve it. Cheers, EricArticle: 151415
On Apr 4, 7:29=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > >On Apr 3, 10:09=3DA0am, n...@puntnl.niks (Nico Coesel) wrote: > >> shyam <mail.ghanashyam.pra...@gmail.com> wrote: > >> >On Mar 31, 10:12=3D3DA0pm, n...@puntnl.niks (Nico Coesel) wrote: > >> >> I've run into a bit of a problem. A camera module I would like to u= se > >> >> has a MIPI CSI-2 interface. The SoC I want to connect to only has a > >> >> parallel camera interface. How difficult would it be to use an FPGA= in > >> >> between? Or are there already MIPI to parallel converters? > > >> >> -- > > >> >As far as I know, the only thing that prevents you of using the CSI-2 > >> >protocol is the clocking frequency of the serial lane. > > >> >CSI-2 has quite a lot of generic features that are defined. All of > >> >them need not be supported. If your clocking is within 300MHz, I thin= k > >> >a Xilinx FPGA can easily de-serialize this stream. Each lane in the > >> >CSI-2 specification serializes a byte and transmits to the receiver. > >> >So the first thing which one would require is a clock recovery on the > >> >clock lane which can be implemented using a DDR flop(IDELAY) can be > >> >used to centre the clocking to the data and a de-serializer working a= t > >> >line rate. > > >> I guess using the DPLL and use the clock delay line is also an option. > >> I'm surprised Xilinx has no appnote on MIPI. > > >Basically it is a paid specification, so Xilinx would not disclose > >things on its app notes. Xilinx has IDELAY primitives which are very > >effective in centering data and controlling calculated skew/ delay on > >data/clocking lines. (it has both fine grain and coarse grain > >adjustments I suppose) at around 7.5 may be. Not really sure. (256 > >taps on a 200MHz clock) > > IIRC thats Virtex or Spartan 6. > > >> >Post serialization, that has to be a packet processing/parsing state > >> >machine which runs on a byte wise basis which shall run at a frequenc= y > >> >equal to ([line rate / 8]*Lane Width). Hence the internal processing > >> >logic always runs at much slower speed as compared to CSI-2 serial > >> >lines. > >> >On the whole, I do not think it is a difficult task to implement the > >> >receiver in the FPGA if you have a relatively good FPGA(as far as > >> >timing and logic is concerned). > > >> If only I had access to the MIPI specs before paying the fee... I'd > >> hate to findout I wasted thousands of dollars for nothing. > > >If you have the camera receiver, I do not think you ll require MIPI > >specification. You just have to build the receiver according to the > >datasheet information from the MIPI trasmitter :) I have the > > Any pointers to such datasheets? I have the datasheet for the camera > module but its author had a really lazy day. > Google search should give you some datasheets! > >specification but I cannot share it with you > > I know, but maybe you know an unofficial source. Many specifications > have leaked onto the internet. > I am not sure about unofficial sources. > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > --------------------------------------------------------------Article: 151416
> Joe, > I know the boards are tested. I use these boards for development and > validation of small re-usable IP blocks. The IP blocks have internal > JTAG accessible registers. The free JTAG software I'm using is from: > http://www.intellitech.com/jtag/free-jtag-software-ijtag.asp . > It lets me describe the registers and I can make TCL/TK scripts to > operate the IP via JTAG. It's to allow this sort of access I designed the 1 pin interface ... http://www.1pin-interface.com/ I've found this invaluable for my own FPGA and board debug but haven't managed to sell the idea very well. Nial.Article: 151417
On Apr 1, 12:43=A0am, allen <ayho...@gmail.com> wrote: > Hey guys, > > I work in the FPGA development kit sector, and I was just looking to > see if you guys had any ideas regarding what would be your MUST HAVE > features on an FPGA dev kit? > > Thanks in advance! > Allen Hi Allen, As some of the other replies indicate, "MUST HAVE" depends on who you're asking. Based on our experience, a growing number of designs these days require external DDR2 memory, which is why you're seeing hard memory controllers added to FPGAs. With this in mind we created xPOD. This is the first in a series of modularized FPGA boards from FACEbyte (www.fpgaapps.com) that is geared for production. Because of the production volumes, these boards are relatively cheap and will get cheaper as more volume kicks in. So one suggestion is to take advantage of xPOD and design "companion" boards with a variety of peripherals and features. You might want to modularize the peripherals and features too, like Digilent has done with their pmod line. We're doing this with our 'companion' board to xPOD we call DOC. With our next gen, 28nm version (and other roadmap products) you'll be able to snap in an FPGA upgrade extending the life of your board thereby making it more attractive to your end customers. We'd be glad to work with you and others on companion boards that use xPOD and would even promote them at shows we attend, websites, collateral, etc. Modularization is one way to have an answer for everyone you ask the "MUST HAVE" question. Regards, MikeArticle: 151418
On 4/4/2011 5:51 PM, Eric Anderson wrote: > On Mon, 20 Aug 2007 13:49:01 +0000, young wrote: > > "Patrick Dubois"<prdub...@gmail.com> writes: >> Just to come back on the subject of Scons for a minute... Any input on >> that tool? Or does anyone have another suggestion for a make >> alternative? >> >> > In a very-belated follow up: > > I've been using SCons for building projects in Xilinx ISE (12.2), and > I > find it to be pretty suitable. Tasks like extracting build options > and > dependencies from project files are quite manageable, at least with > the > newer XML-based .xise files. > > I've uploaded an example SConstruct on Github here: > https://github.com/ewa/xilinx-build-scripts . I'd love to see people > use > and improve it. > > Cheers, > Eric Thanks for sharing, I have not looked at your files yet but did you use a customer "builder"? And if so, can it be tailored for other FPGA tools. Thanks ChrisArticle: 151419
I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees. I'm using Xilinx's new SDC support which does not have the -
phase option that Altera includes. I cannot find ANY worthwhile
documentation on how to specify my edge list for the edge_shift
option. Can someone please help me out? I currently have the
following which may or may not be correct:
create_generated_clock \
-name my_new_clock \
-divide_by 2 \
-edges { 1 3 5 } \ <-- also divides the clock by 2, so the
divide_by option is not really necessary
-edge_shift { 1 1 1 } \ <-- not really sure about this part ...
wondering if this is correct
-source [get_pins source_clock] \
[get_nets {new_clock}]
I know most of the above constraint is correct, but I don't know if I
have specified the edge_shift correctly. Remember, I want to divide
the source_clock by 2 and then shift it by 90 degrees.
The best documentation I can find with Google is on Altera's site.
http://www.altera.com/support/software/timequest/clock/tq-generate-clock.html#note1
The site provides the following example:
# Creates a divide-by-2 clock independent of the master clock's duty
cycle now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
edge_shift 0 5 0 } [get_registers clkdivB|clkreg]
The above example corresponds to Figure 2 on the linked web page. I
don't entirely understand this example or how the edge_shift is {0 5
0}. It would be great if someone could explain that as well.
Thanks for any help.
James
Article: 151420On Apr 5, 11:22=A0am, fpgaace <mikegulo...@gmail.com> wrote: > Hi Allen, > As some of the other replies indicate, "MUST HAVE" depends on who > you're asking. =A0Based on our experience, a growing number of designs > these days require external DDR2 memory, which is why you're seeing > hard memory controllers added to FPGAs. =A0With this in mind we created > xPOD. =A0This is the first in a series of modularized FPGA boards from > FACEbyte (www.fpgaapps.com) that is geared for production. =A0Because of > the production volumes, these boards are relatively cheap and will get > cheaper as more volume kicks in. > > So one suggestion is to take advantage of xPOD and design "companion" > boards with a variety of peripherals and features. =A0You might want to > modularize the peripherals and features too, like Digilent has done > with their pmod line. =A0We're doing this with our 'companion' board to > xPOD we call DOC. =A0With our next gen, 28nm version (and other roadmap > products) you'll be able to snap in an FPGA upgrade extending the life > of your board thereby making it more attractive to your end > customers. =A0We'd be glad to work with you and others on companion > boards that use xPOD and would even promote them at shows we attend, > websites, collateral, etc. > > Modularization is one way to have an answer for everyone you ask the > "MUST HAVE" question. > > Regards, > Mike Thats a nice idea; cheap and modular. I hope you have success with it and are able to expand the range of products available. I like the Pmod interfacing. A Pmod is simple enough that I could design make my own Pmods at home with my level of electronics and hobbyist PCB making equipment. I'm really a beginner with FPGAs and have started out by buying a few cheap dev kits on ebay. My next step would be to go for something like this xPOD. RupertArticle: 151421
Hello all, I am trying to understand whether it is possible to extract a clock from the serial stream and use it as reference for the PMA PLL. According to what I read so far it is not customary, sources are either externl FPGA clock, internal FPGA clock or clock from adjacent transceiver. How then can a remote radio head use synchronize to a high precision base station clock? According to CPRI standard the RE should have a clock 'traceable' to the RE clock. Best regards, EArticle: 151422
Hi all, I am new to the world of FPGA. I want to communicate my Virtex 4 XC4VSX35 FPGA to PC using Tri-mode Ethernet MAC IP core. Please give me any suggestion how to start... Also recommend some basic documentation which helps me understand. Or if there is any better alternative, plz do share it with me... Regards, Hassoo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151423
My understanding is that the recovered clock from the RX side has too much = jitter to be used for pretty much anything other than a transfer to a stabl= e clock domain. i.e. I don't even think it can drive the FPGA fabric PLLs, = let alone the transceiver PLL. The usual way this is handled is to drive a PLL (not the internal FPGA PLLs= , but an external discrete PLL) with a reference derived from the recovered= clock. Then use the clock output of the PLL to drive the TX side of the tr= ansceiver. The PLL attenuates the jitter and you're good to go. Disclosure: I know nothing about CPRI, but work with transceivers in an unr= elated application. ChrisArticle: 151424
On Apr 5, 3:53=A0pm, James <jmos1...@gmail.com> wrote:
> I want to use create_generated_clock to generate a clock that is half
> the frequency of the source clock and also phase shifted by 90
> degrees. =A0I'm using Xilinx's new SDC support which does not have the -
> phase option that Altera includes. =A0I cannot find ANY worthwhile
> documentation on how to specify my edge list for the edge_shift
> option. =A0Can someone please help me out? =A0I currently have the
> following which may or may not be correct:
>
> create_generated_clock \
> =A0 =A0 -name my_new_clock \
> =A0 =A0 -divide_by 2 \
> =A0 =A0 -edges { 1 3 5 } \ =A0 <-- also divides the clock by 2, so the
> divide_by option is not really necessary
> =A0 =A0 -edge_shift { 1 1 1 } \ =A0<-- not really sure about this part ..=
.
> wondering if this is correct
> =A0 =A0 -source [get_pins source_clock] \
> =A0 =A0 =A0 =A0 =A0 =A0 [get_nets {new_clock}]
>
> I know most of the above constraint is correct, but I don't know if I
> have specified the edge_shift correctly. =A0Remember, I want to divide
> the source_clock by 2 and then shift it by 90 degrees.
>
> The best documentation I can find with Google is on Altera's site.http://=
www.altera.com/support/software/timequest/clock/tq-generate-cl...
> The site provides the following example:
>
> # Creates a divide-by-2 clock independent of the master clock's duty
> cycle now 50%)
> create_generated_clock -source [get_ports clk] -edges { 1 1 5 } -
> edge_shift =A00 5 0 } [get_registers clkdivB|clkreg]
>
> The above example corresponds to Figure 2 on the linked web page. =A0I
> don't entirely understand this example or how the edge_shift is {0 5
> 0}. =A0It would be great if someone could explain that as well.
>
> Thanks for any help.
> James
The SDC constraints can be used to describe timing relationships (as
well as other design constraints such as placement locations) for use
by the timing analyzer. They cannot be used to drive the tools to
create a physical clock condition as it appears you are attempting.
You should use the clocking wizard in CoreGen as a starting point.
Ed McGettigan
--
Xilinx Inc.
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