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On 4/30/2017 12:38 AM, Tim Wescott wrote: > On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>> >>>> I don't recall where, but there was a conversation recently about >>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>> >>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>> embedded-processing/risc-v >>> >>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >> >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. I haven't seen any indication this exists, >> but it is hard to find this type of info. Or I'm just not looking in >> the right places. > > Googling RISC-V FPGA implementation got lots of hits. Too many, with all that I checked having little value. I've never understood why people go to all the trouble of designing modules and making them publicly available without significant documentation that explains what was done and why. In some 10 or 12 links I was not able to find a single overview of what the project is about, where it is currently and where it is headed. Whatever. I don't have a strong interest in it at the moment. I have some ideas of my own I want to pursue which is also back burner. -- Rick CArticle: 159926
On 4/30/2017 12:35 AM, Tim Wescott wrote: > On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>> >>>> I don't recall where, but there was a conversation recently about >>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>> >>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>> embedded-processing/risc-v >>> >>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >> >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. I haven't seen any indication this exists, >> but it is hard to find this type of info. Or I'm just not looking in >> the right places. > > They claim to have a minimal variant of the instruction set, which would > presumably be an FPGA-ish sort of thing. But I only read about 20 pages > into the instruction set document. I found reference to there being as many as three variants implemented in FPGAs, but I don't think any are intended for use in FPGAs. Rather I believe these are just test designs along the road to the ASIC which would seem to be out and available on a board for not too much money. > It's OPEN SOURCE! You could get cracking and make one!! (Well, so could > I, theoretically, if I were insane). If I wrote one it would be a very simple implementation which would likely require lots of clock cycles to complete anything. But then maybe my impression of the design is not very accurate. I picture it as something very much more complex than the simple and fast stack processors I am used to working with. -- Rick CArticle: 159927
rickman <gnuarm@gmail.com> wrote: > I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places. A basic RV32I (the minimal 32 bit user-mode instruction set) is very simple. Here's one that's about 400 lines of SystemVerilog, that was designed by a student over a few weeks as a summer project: https://github.com/ucam-comparch/clarvi TheoArticle: 159928
rickman <gnuarm@gmail.com> wrote: > Too many, with all that I checked having little value. I've never > understood why people go to all the trouble of designing modules and > making them publicly available without significant documentation that > explains what was done and why. In some 10 or 12 links I was not able > to find a single overview of what the project is about, where it is > currently and where it is headed. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf is the manifesto. TheoArticle: 159929
On Sun, 30 Apr 2017 01:50:42 -0400, rickman wrote: > On 4/30/2017 12:35 AM, Tim Wescott wrote: >> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >> >>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>> >>>>> I don't recall where, but there was a conversation recently about >>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>> >>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>> embedded-processing/risc-v >>>> >>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>> >>> I don't know how small the RISC-V can be made. I know there is a >>> version designed in an ASIC that can compete with the ARM CPUs and >>> there are more than one version for FPGAs. I would hope they had a >>> version similar to the ARM CM-1 which is specifically targeted to >>> programmable logic and not overly large. I haven't seen any >>> indication this exists, but it is hard to find this type of info. Or >>> I'm just not looking in the right places. >> >> They claim to have a minimal variant of the instruction set, which >> would presumably be an FPGA-ish sort of thing. But I only read about >> 20 pages into the instruction set document. > > I found reference to there being as many as three variants implemented > in FPGAs, but I don't think any are intended for use in FPGAs. Rather I > believe these are just test designs along the road to the ASIC which > would seem to be out and available on a board for not too much money. > > >> It's OPEN SOURCE! You could get cracking and make one!! (Well, so >> could I, theoretically, if I were insane). > > If I wrote one it would be a very simple implementation which would > likely require lots of clock cycles to complete anything. But then > maybe my impression of the design is not very accurate. I picture it as > something very much more complex than the simple and fast stack > processors I am used to working with. I would at least hope that the result would be on the level of gate usage as a Cortex M1. OTOH, since Day 1, the RISC architecture has been about getting the most bang for your logic buck -- and you can always leave out the bells and whistles like branch prediction and pipelines and whatnot. If they did their job right, you'll find that much of the "logic" can be coded as static wires -- that's why they do things like always have information fields (like register addresses, or immediate data) appearing in the same spots. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159930
On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > On 4/30/2017 12:38 AM, Tim Wescott wrote: >> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >> >>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>> >>>>> I don't recall where, but there was a conversation recently about >>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>> >>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>> embedded-processing/risc-v >>>> >>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>> >>> I don't know how small the RISC-V can be made. I know there is a >>> version designed in an ASIC that can compete with the ARM CPUs and >>> there are more than one version for FPGAs. I would hope they had a >>> version similar to the ARM CM-1 which is specifically targeted to >>> programmable logic and not overly large. I haven't seen any >>> indication this exists, but it is hard to find this type of info. Or >>> I'm just not looking in the right places. >> >> Googling RISC-V FPGA implementation got lots of hits. > > Too many, with all that I checked having little value. I've never > understood why people go to all the trouble of designing modules and > making them publicly available without significant documentation that > explains what was done and why. In some 10 or 12 links I was not able > to find a single overview of what the project is about, where it is > currently and where it is headed. That's typical of open-source projects: functionality is fun; good documentation is at least as time-consuming as good code (HDL or software), and documentation-writing isn't nearly as fun. For cutting-edge open-source stuff the key to success is to find the web forum or mailing list that covers the subject, and to start asking questions. I suppose that if I won the lottery and didn't get seduced by Tahiti I'd pick a project and just write documentation. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159931
On 30/04/17 16:39, Tim Wescott wrote: > On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >>> >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>>> >>>>>> I don't recall where, but there was a conversation recently about >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>>> >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>>> embedded-processing/risc-v >>>>> >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>>> >>>> I don't know how small the RISC-V can be made. I know there is a >>>> version designed in an ASIC that can compete with the ARM CPUs and >>>> there are more than one version for FPGAs. I would hope they had a >>>> version similar to the ARM CM-1 which is specifically targeted to >>>> programmable logic and not overly large. I haven't seen any >>>> indication this exists, but it is hard to find this type of info. Or >>>> I'm just not looking in the right places. >>> >>> Googling RISC-V FPGA implementation got lots of hits. >> >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > That's typical of open-source projects: functionality is fun; good > documentation is at least as time-consuming as good code (HDL or > software), and documentation-writing isn't nearly as fun. > > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation. > Or you find a company (ideally run by at least some of the people behind the open source project) that will provide you with support, documentation, demos, point-and-click installations (especially for Windows), etc. - all for a bit of money. When it works well, it can give you all the benefits of a good open source project, /and/ all the benefits of a good commercial project, for a price somewhere in between. I don't know if there is such commercial support available for RISC-V - but if it gets popular enough, then I am sure there will be.Article: 159932
An older version of the Risc V processor generator is here: https://github.com/ucb-bar/riscv-sodor This is the 1 stage version: https://github.com/ucb-bar/riscv-sodor/tree/master/src/rv32_1stage A more recent version by the same group seems to be this BOOM Risc V which is synthesizable. https://github.com/ucb-bar/riscv-boom This presentation seems to cover all versions: https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf The CPU is implemented in Chisel which is a scala library that compiles to Verilog or C++. https://chisel.eecs.berkeley.edu/2.2.0/getting-started.html On Sunday, April 30, 2017 at 6:13:37 PM UTC+3, David Brown wrote: > On 30/04/17 16:39, Tim Wescott wrote: > > On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > > > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: > >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >>> > >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: > >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: > >>>>> > >>>>>> I don't recall where, but there was a conversation recently about > >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. > >>>>>> > >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ > >>>>> embedded-processing/risc-v > >>>>> > >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > >>>> > >>>> I don't know how small the RISC-V can be made. I know there is a > >>>> version designed in an ASIC that can compete with the ARM CPUs and > >>>> there are more than one version for FPGAs. I would hope they had a > >>>> version similar to the ARM CM-1 which is specifically targeted to > >>>> programmable logic and not overly large. I haven't seen any > >>>> indication this exists, but it is hard to find this type of info. Or > >>>> I'm just not looking in the right places. > >>> > >>> Googling RISC-V FPGA implementation got lots of hits. > >> > >> Too many, with all that I checked having little value. I've never > >> understood why people go to all the trouble of designing modules and > >> making them publicly available without significant documentation that > >> explains what was done and why. In some 10 or 12 links I was not able > >> to find a single overview of what the project is about, where it is > >> currently and where it is headed. > > > > That's typical of open-source projects: functionality is fun; good > > documentation is at least as time-consuming as good code (HDL or > > software), and documentation-writing isn't nearly as fun. > > > > For cutting-edge open-source stuff the key to success is to find the web > > forum or mailing list that covers the subject, and to start asking > > questions. I suppose that if I won the lottery and didn't get seduced by > > Tahiti I'd pick a project and just write documentation. > > > > Or you find a company (ideally run by at least some of the people behind > the open source project) that will provide you with support, > documentation, demos, point-and-click installations (especially for > Windows), etc. - all for a bit of money. When it works well, it can > give you all the benefits of a good open source project, /and/ all the > benefits of a good commercial project, for a price somewhere in between. > > I don't know if there is such commercial support available for RISC-V - > but if it gets popular enough, then I am sure there will be.Article: 159933
Tim, all, On 30-04-17 16:39, Tim Wescott wrote: (...) > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation. F.Y.I. One of the main mailing-lists is here: hw-dev@groups.riscv.org Traffic is relative low (about 15 messages a week), so quite easy to follow without getting flooded in messages. more info: https://riscv.org/mailing-lists/ KristoffArticle: 159934
Emilian Miron <emilian.miron@gmail.com> wrote: > An older version of the Risc V processor generator is here: > https://github.com/ucb-bar/riscv-sodor > This is the 1 stage version: > https://github.com/ucb-bar/riscv-sodor/tree/master/src/rv32_1stage > > A more recent version by the same group seems to be this BOOM Risc V which is synthesizable. > https://github.com/ucb-bar/riscv-boom > > This presentation seems to cover all versions: > https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf > > The CPU is implemented in Chisel which is a scala library that compiles to Verilog or C++. > https://chisel.eecs.berkeley.edu/2.2.0/getting-started.html For those who are confused, RISC-V is not a *processor*, it's an *architecture*. Anyone can come up with a microarchitectural implementation of the architecture - that's the point of an open source ISA. Being open-source you can also change the architecture - but it's then your problem to maintain the OS/compiler/etc for your fork of the architecture. Berkeley happen to have some of their own implementations that they have also open sourced. These might or might not suit your purposes. Being in Chisel is one thing that's not everyone's cup of tea. But the idea is that everyone has an architectural licence, so they are free to come up with their own implementations, and share them. I suspect that Microsemi have done their own, rather than importing the Berkeley cores, for instance. (That RISC-V bears a certain resemblance to MIPS is not entirely accidental; MIPS has long been used as a simple ISA for teaching, which is one role that RISC-V fills without treading on any toes [patents] of Imagination Technologies) TheoArticle: 159935
On 4/30/2017 10:04 AM, Theo Markettos wrote: > rickman <gnuarm@gmail.com> wrote: >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf > is the manifesto. Thanks for the link, this is useful to learn about the instruction set. Not much info on the available implementations. -- Rick CArticle: 159936
On 4/30/2017 10:39 AM, Tim Wescott wrote: > On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >>> >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>>> >>>>>> I don't recall where, but there was a conversation recently about >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>>> >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>>> embedded-processing/risc-v >>>>> >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>>> >>>> I don't know how small the RISC-V can be made. I know there is a >>>> version designed in an ASIC that can compete with the ARM CPUs and >>>> there are more than one version for FPGAs. I would hope they had a >>>> version similar to the ARM CM-1 which is specifically targeted to >>>> programmable logic and not overly large. I haven't seen any >>>> indication this exists, but it is hard to find this type of info. Or >>>> I'm just not looking in the right places. >>> >>> Googling RISC-V FPGA implementation got lots of hits. >> >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > That's typical of open-source projects: functionality is fun; good > documentation is at least as time-consuming as good code (HDL or > software), and documentation-writing isn't nearly as fun. > > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation. I see a total lack of documentation on amateur projects where someone designs something and tosses it up on one of the source sharing sites. But a major project like this is about being used. I don't think this is just a few guys who thought it would be cool to design a chip. This chip has been built as an ASIC and has multiple incarnations for FPGA. It would tremendously help encourage implementations to have a decent description of what is available. -- Rick CArticle: 159937
Pretty small (and fast): https://forums.xilinx.com/t5/Xcell-Daily-Blog/1680-open-source-ISA-RISC-V-processor-cores-run-on-one-Virtex/ba-p/742731 On 04/29/2017 08:04 PM, rickman wrote: > On 4/28/2017 9:56 PM, Tim Wescott wrote: >> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >> >>> I don't recall where, but there was a conversation recently about using >>> the RISC-V in FPGAs. Thought I'd pass on the link. >>> >>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >> embedded-processing/risc-v >> >> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > > I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places. >Article: 159938
> That's typical of open-source projects: functionality is fun; good=20 > documentation is at least as time-consuming as good code (HDL or=20 > software), and documentation-writing isn't nearly as fun. >=20 > For cutting-edge open-source stuff the key to success is to find the web= =20 > forum or mailing list that covers the subject, and to start asking=20 > questions. I suppose that if I won the lottery and didn't get seduced by= =20 > Tahiti I'd pick a project and just write documentation. >=20 I suppose this is one reason that Octave works so well for me: when I have= a question, I consult the Matlab documentation. That makes feel a little = guilty. I've found Octave is actually faster on a lot of my scripts though= . Sadly, when you mentioned Tahiti, I was trying to figure out if that was th= e name of some obscure HDL or open-source project. It took me a minute to = figure out you meant the place where Gaugin hung out. Yeah, that might be = better than writing documentation.Article: 159939
> A basic RV32I (the minimal 32 bit user-mode instruction set) is very simple. > Here's one that's about 400 lines of SystemVerilog, that was designed by a > student over a few weeks as a summer project: > > https://github.com/ucam-comparch/clarvi > > Theo The code looks pretty clear at first glance. I see a lot of SystemVerilog constructs that don't look synthesizer-friendly, though.Article: 159940
On Mon, 01 May 2017 15:42:03 -0700, Kevin Neilson wrote: >> That's typical of open-source projects: functionality is fun; good >> documentation is at least as time-consuming as good code (HDL or >> software), and documentation-writing isn't nearly as fun. >> >> For cutting-edge open-source stuff the key to success is to find the >> web forum or mailing list that covers the subject, and to start asking >> questions. I suppose that if I won the lottery and didn't get seduced >> by Tahiti I'd pick a project and just write documentation. >> > I suppose this is one reason that Octave works so well for me: when I > have a question, I consult the Matlab documentation. That makes feel a > little guilty. I've found Octave is actually faster on a lot of my > scripts though. > > Sadly, when you mentioned Tahiti, I was trying to figure out if that was > the name of some obscure HDL or open-source project. It took me a > minute to figure out you meant the place where Gaugin hung out. Yeah, > that might be better than writing documentation. Or maybe project TAHITI from Agent's of S.H.I.E.L.D. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159941
> I don't know how small the RISC-V can be made. I know there is a=20 > version designed in an ASIC that can compete with the ARM CPUs and there= =20 > are more than one version for FPGAs. I would hope they had a version=20 > similar to the ARM CM-1 which is specifically targeted to programmable=20 > logic and not overly large. =20 Speaking of ARM, I still can't figure out how ARM was acquired for $32B. I= f even a student can make a synthesizable 32-bit processor in a few weeks, = how much value can there be in a processor? It's almost a commodity. I kn= ow there is a lot of value in prediction pipelines, cache logic, compilers,= etc., but not $32b' worth.=20Article: 159942
On Mon, 01 May 2017 16:07:02 -0700, Kevin Neilson wrote: >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and >> there are more than one version for FPGAs. I would hope they had a >> version similar to the ARM CM-1 which is specifically targeted to >> programmable logic and not overly large. > > Speaking of ARM, I still can't figure out how ARM was acquired for $32B. > If even a student can make a synthesizable 32-bit processor in a few > weeks, how much value can there be in a processor? It's almost a > commodity. I know there is a lot of value in prediction pipelines, > cache logic, compilers, etc., but not $32b' worth. So, maybe the people who SOLD it are laughing their way to the bank. ARM processor variants have a huge installed base -- I suspect that went a long way to justifying the $32B. But, if ST started offering parts with the RISC-V core tomorrow, at a better price, I'd switch. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159943
On 05/01/2017 04:46 PM, Tim Wescott wrote: > On Mon, 01 May 2017 16:07:02 -0700, Kevin Neilson wrote: > >>> I don't know how small the RISC-V can be made. I know there is a >>> version designed in an ASIC that can compete with the ARM CPUs and >>> there are more than one version for FPGAs. I would hope they had a >>> version similar to the ARM CM-1 which is specifically targeted to >>> programmable logic and not overly large. >> >> Speaking of ARM, I still can't figure out how ARM was acquired for $32B. >> If even a student can make a synthesizable 32-bit processor in a few >> weeks, how much value can there be in a processor? It's almost a >> commodity. I know there is a lot of value in prediction pipelines, >> cache logic, compilers, etc., but not $32b' worth. > > So, maybe the people who SOLD it are laughing their way to the bank. > > ARM processor variants have a huge installed base -- I suspect that went > a long way to justifying the $32B. But, if ST started offering parts > with the RISC-V core tomorrow, at a better price, I'd switch. > You would. I probably wouldn't, having a larger team to drag around and all of the associated infrastructure. But the cell phone companies, with all that already written codebase and 10s of millions of units sold per year? Not a chance they do. That's billions of dollars of inertia. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 159944
On 05/01/2017 04:07 PM, Kevin Neilson wrote: >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. > > Speaking of ARM, I still can't figure out how ARM was acquired for $32B. If even a student can make a synthesizable 32-bit processor in a few weeks, how much value can there be in a processor? It's almost a commodity. I know there is a lot of value in prediction pipelines, cache logic, compilers, etc., but not $32b' worth. > The probably have a pretty good revenue stream. I don't remember what they get per processor instance, but pretty much all the major semiconductor houses, and several of the fabless ones are shipping products with ARM processors in them. They are showing up in all kinds of ASICs as well. Also, coding a synthesizable, 32 bit processor is only the beginning. Verifying it, implementing a silicon validation suite, getting compiler and debugger support and getting all of that stable and accepted are pretty big tasks. ARM has been at this project for a LONG time (early to mid 90's that I know of, maybe longer). That's a lot of customer experience. Having a uniform (fairly, anyway) ecosystem on multiple vendors is worth some to me. I like that the I/O, Interrupt, power control and clock generation stuff is at least recognizable from vendor to vendor. I can't say whether it is all worth $32B, but I guess it was to somebody... BobHArticle: 159945
On Mon, 01 May 2017 17:15:01 -0700, Rob Gaddi wrote: > On 05/01/2017 04:46 PM, Tim Wescott wrote: >> On Mon, 01 May 2017 16:07:02 -0700, Kevin Neilson wrote: >> >>>> I don't know how small the RISC-V can be made. I know there is a >>>> version designed in an ASIC that can compete with the ARM CPUs and >>>> there are more than one version for FPGAs. I would hope they had a >>>> version similar to the ARM CM-1 which is specifically targeted to >>>> programmable logic and not overly large. >>> >>> Speaking of ARM, I still can't figure out how ARM was acquired for >>> $32B. >>> If even a student can make a synthesizable 32-bit processor in a few >>> weeks, how much value can there be in a processor? It's almost a >>> commodity. I know there is a lot of value in prediction pipelines, >>> cache logic, compilers, etc., but not $32b' worth. >> >> So, maybe the people who SOLD it are laughing their way to the bank. >> >> ARM processor variants have a huge installed base -- I suspect that >> went a long way to justifying the $32B. But, if ST started offering >> parts with the RISC-V core tomorrow, at a better price, I'd switch. >> >> > You would. I probably wouldn't, having a larger team to drag around and > all of the associated infrastructure. > > But the cell phone companies, with all that already written codebase and > 10s of millions of units sold per year? Not a chance they do. That's > billions of dollars of inertia. I probably have 20 lines of ARM assembly written, and in retrospect that could just as well be carefully-crafted C. Assuming that FreeRTOS makes a port, everything else is C or C++, and could just be compiled for the new target. I don't know about the cell phone companies -- are they really that heavily invested in processor-specific stuff? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!Article: 159946
On 5/1/2017 11:45 AM, Robert F. Jarnot wrote: > Pretty small (and fast): > https://forums.xilinx.com/t5/Xcell-Daily-Blog/1680-open-source-ISA-RISC-V-processor-cores-run-on-one-Virtex/ba-p/742731 This design has processors plus other interconnecting logic. Hard to say how much is processor. Taking it all as processor gives around 1.54 kLCs per processor. There are lots of processors that are much smaller than this. I don't see *any* info on the speed of these processors, so I don't know what the "fast" claim is based on. -- Rick CArticle: 159947
On 5/1/2017 7:07 PM, Kevin Neilson wrote: >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. > > Speaking of ARM, I still can't figure out how ARM was acquired for $32B. If even a student can make a synthesizable 32-bit processor in a few weeks, how much value can there be in a processor? It's almost a commodity. I know there is a lot of value in prediction pipelines, cache logic, compilers, etc., but not $32b' worth. The value of a company is not directly related to technology. There are many ways to make a buck and making a buck is what the value of a company is about. Anyone can make hamburgers, but McDonalds seems to have done well over the decades. -- Rick CArticle: 159948
On 5/1/2017 8:42 PM, Tim Wescott wrote: > On Mon, 01 May 2017 17:15:01 -0700, Rob Gaddi wrote: > >> On 05/01/2017 04:46 PM, Tim Wescott wrote: >>> On Mon, 01 May 2017 16:07:02 -0700, Kevin Neilson wrote: >>> >>>>> I don't know how small the RISC-V can be made. I know there is a >>>>> version designed in an ASIC that can compete with the ARM CPUs and >>>>> there are more than one version for FPGAs. I would hope they had a >>>>> version similar to the ARM CM-1 which is specifically targeted to >>>>> programmable logic and not overly large. >>>> >>>> Speaking of ARM, I still can't figure out how ARM was acquired for >>>> $32B. >>>> If even a student can make a synthesizable 32-bit processor in a few >>>> weeks, how much value can there be in a processor? It's almost a >>>> commodity. I know there is a lot of value in prediction pipelines, >>>> cache logic, compilers, etc., but not $32b' worth. >>> >>> So, maybe the people who SOLD it are laughing their way to the bank. >>> >>> ARM processor variants have a huge installed base -- I suspect that >>> went a long way to justifying the $32B. But, if ST started offering >>> parts with the RISC-V core tomorrow, at a better price, I'd switch. >>> >>> >> You would. I probably wouldn't, having a larger team to drag around and >> all of the associated infrastructure. >> >> But the cell phone companies, with all that already written codebase and >> 10s of millions of units sold per year? Not a chance they do. That's >> billions of dollars of inertia. > > I probably have 20 lines of ARM assembly written, and in retrospect that > could just as well be carefully-crafted C. Assuming that FreeRTOS makes > a port, everything else is C or C++, and could just be compiled for the > new target. Assembly language code is not the only way to be wedded to an architecture. There are lots of C code written to manage the CPU and tightly coupled functionality not to mention optimizing code for maximum performance in an architecture. Then there is the effort required to optimize the tools. Yes, it is easy to port tools, but to get them honed for optimal usage requires a lot more effort. I doubt that has been done for the RISC-V as yet. -- Rick CArticle: 159949
On 02/05/17 03:46, rickman wrote: > On 5/1/2017 8:42 PM, Tim Wescott wrote: >> On Mon, 01 May 2017 17:15:01 -0700, Rob Gaddi wrote: >> >>> On 05/01/2017 04:46 PM, Tim Wescott wrote: >>>> On Mon, 01 May 2017 16:07:02 -0700, Kevin Neilson wrote: >>>> >>>>>> I don't know how small the RISC-V can be made. I know there is a >>>>>> version designed in an ASIC that can compete with the ARM CPUs and >>>>>> there are more than one version for FPGAs. I would hope they had a >>>>>> version similar to the ARM CM-1 which is specifically targeted to >>>>>> programmable logic and not overly large. >>>>> >>>>> Speaking of ARM, I still can't figure out how ARM was acquired for >>>>> $32B. >>>>> If even a student can make a synthesizable 32-bit processor in a few >>>>> weeks, how much value can there be in a processor? It's almost a >>>>> commodity. I know there is a lot of value in prediction pipelines, >>>>> cache logic, compilers, etc., but not $32b' worth. >>>> >>>> So, maybe the people who SOLD it are laughing their way to the bank. >>>> >>>> ARM processor variants have a huge installed base -- I suspect that >>>> went a long way to justifying the $32B. But, if ST started offering >>>> parts with the RISC-V core tomorrow, at a better price, I'd switch. >>>> >>>> >>> You would. I probably wouldn't, having a larger team to drag around and >>> all of the associated infrastructure. >>> >>> But the cell phone companies, with all that already written codebase and >>> 10s of millions of units sold per year? Not a chance they do. That's >>> billions of dollars of inertia. >> >> I probably have 20 lines of ARM assembly written, and in retrospect that >> could just as well be carefully-crafted C. Assuming that FreeRTOS makes >> a port, everything else is C or C++, and could just be compiled for the >> new target. > > Assembly language code is not the only way to be wedded to an > architecture. There are lots of C code written to manage the CPU and > tightly coupled functionality not to mention optimizing code for maximum > performance in an architecture. Then there is the effort required to > optimize the tools. Yes, it is easy to port tools, but to get them > honed for optimal usage requires a lot more effort. I doubt that has > been done for the RISC-V as yet. > A sizeable part of that is hidden in the three key components - the OS kernel, the basic libraries, and the compiler. The huge majority of the code on a telephone is cpu agnostic. Most of it got bumped from 32-bit ARM to 64-bit ARM without much bother, and the 32 to 64 bit jump is often a bigger port issue than moving between different 32-bit architectures. I don't know if the current state of these RISC-V tools are good enough, however - I believe the Linux port of RISC-V is quite new, and the gcc port has just been redone. For the big customers, they will want to see a bit of maturity before considering RISC-V. For us mere mortals, however, RISC-V is a great idea. If nothing else, it gives ARM some much-needed competition (which should have come from MIPS).
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