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On Wednesday, January 10, 2018 at 5:56:45 PM UTC-8, Weng Tianxiang wrote: > Hi, >=20 > A wive-pipelined circuit has the same logic as its pipeline counterpart e= xcept that the wive-pipelined circuit has only one stage, a critical path f= rom the input register passing through a piece of computational logic to th= e output register, and no intermediate registers. >=20 > My invention kernel idea is: A designer provides the least information an= d logic code about the critical path, and leave all complex logic designs t= o a synthesizer and a system library that is what an HDL should do. >=20 > All coding has 3 steps: > 1. Write a Critical Path Component (CPC) with defined interface; >=20 > 2. Call a Wave-Pipelining Component (WPC) provided by a system library; >=20 > 3. Call one of 3 link statement to link a CPC instantiation with a paired= WPC instantiation to specify what your target is. >=20 > Here is the all code on a 64*64 bits signed integer multiplier C <=3D A*B= . >=20 > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > use work.wave_pipeline_package.all; >=20 > -- CPC code for wave-pipelined 64-bit signed integer multiplier C <=3D A*= B > -- CPC_1_2 is linked with SMB by link1() / link2() if "wave" is accepted = in VHDL > -- link1(): generation would fail if the circuit cannot accept 1 data per= cycle > -- link2(): generation never fails and the circuit is capable of acceptin= g 1 data per=20 > -- INPUT_CLOCK_NUMBER cycles >=20 > entity CPC_1_2 is=20 > generic ( =20 > input_data_width : positive :=3D 64; -- optional > output_data_width : positive :=3D 128 -- optional > ); > port ( > CLK : in std_logic; > WE_i : in std_logic; -- '1': write enable to input registers = A & B=20 > Da_i : in signed(input_data_width-1 downto 0); -- input data= A > Db_i : in signed(input_data_width-1 downto 0); -- input data= B > WE_o_i: in std_logic; -- '1': write enable to output register C > Dc_o : out unsigned(output_data_width -1 downto 0) -- output dat= a C > ); > end CPC_1_2; >=20 > architecture A_CPC_1_2 of CPC_1_2 is > signal Ra : signed(input_data_width-1 downto 0); -- input register= A > signal Rb : signed(input_data_width-1 downto 0); -- input register= B > signal Rc : signed(output_data_width-1 downto 0); -- output registe= r C > signal Cl : signed(output_data_width-1 downto 0); -- combinational = logic > =20 > begin > Cl <=3D Ra * Rb; -- combinational logic output, key par= t of CPC > Dc_o <=3D unsigned(Rc); -- output through output register >=20 > p_1 : process(CLK) > begin > if Rising_edge(CLK) then > if WE_i =3D '1' then -- WE_i =3D '1' : latch input data > Ra <=3D Da_i; > Rb <=3D Db_i; > end if; > =20 > if WE_O_I =3D '1' then -- WE_O_I =3D '1': latch output data > Rc <=3D Cl; > end if; > end if; > end process; >=20 > -------------------------------------------------------------------------= ------- >=20 > end A_CPC_1_2; >=20 > In summary, after HDL adopting my system, writing a wave-pipelined circui= t is simple as writing a one-cycle logic circuit. >=20 > Thank you. >=20 > Weng Hi, The following information is from Wikipedia: 1. The Intel 8087, announced in 1980, was the first x87 floating-point copr= ocessor for the 8086 line of microprocessors. 2. MMX is a single instruction, multiple data (SIMD) instruction set design= ed by Intel, introduced in 1997 with its P5-based Pentium line of microproc= essors, designated as "Pentium with MMX Technology".[1] It developed out of= a similar unit introduced on the Intel i860,[2] and earlier the Intel i750= video pixel processor. MMX is a processor supplementary capability that is= supported on recent IA-32 processors by Intel and other vendors. MMX has subsequently been extended by several programs by Intel and others:= 3DNow!, Streaming SIMD Extensions (SSE), and ongoing revisions of Advanced= Vector Extensions (AVX). 8087's floating 64-bit multiplier needs 5 cycles to finish a data processin= g with one input data per cycle. MMX floating 64-bit floating multiplier needs 4 cycles to finish a data pro= cessing with one set of input data per 2 cycles. Because each multiplier needs one multiplicand A and one multiplier B to ge= t the result C, so naturally many testing benches claim MMX 64-bit floating= multiplier is 20% faster than 8087 (4 cycles vs 5 cycles). With my invention, any college students with knowledge of HDL can write a M= MX wave-pipelined 64-bit floating multiplier within half an hour under foll= owing conditions: 1. My invented system is fully accepted to HDL; 2. Synthesizer manufacturers have updated their products to handle the gene= ration of related wave-pipelined circuits. All related technology and algorithms are available off selves. 3. It needs time. One of wonderful wave-pipelined circuits I think may be 16 channels FFT pro= cessor with wave-pipelined technology: the benefits are faster running freq= uency and a lot of saving in respect of logic area and power consumption. Thank you. WengArticle: 160401
On Wednesday, January 10, 2018 at 6:17:32 AM UTC-8, john wrote: > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > > -- > > john > > ========================= > http://johntech.co.uk > ========================= Verilog, Verilog, Verilog. I've been consulting for over 24 years now and I now focus exclusively on Verilog for a variety of reasons. I've seen the Verilog vs VHDL discussion many times, it boils down to either a religious or toothpaste debate - what were you raised with or what flavor do you prefer. I've found I am *much* more productive in Verilog. At this point, I don't take on jobs in VHDL. My $0.02. John PArticle: 160402
john p wrote on 1/12/2018 10:09 PM: > On Wednesday, January 10, 2018 at 6:17:32 AM UTC-8, john wrote: >> I'm trying to decide on which to use for a project as the main default that may >> include a number of freelance people. >> >> can you say which of these you actually use (the most) >> and have the best skills in >> >> Verilog >> systemVerilog >> SystemC >> VHDL >> Other >> >> And if possible what type of work you use it for in general >> I dont need to know why you use a particular one - and to avoid >> flame wars request you dont explain that. >> >> I'm just trying to get a general feel for what people here use regularly. >> >> TIA >> >> -- >> >> john >> >> ========================= >> http://johntech.co.uk >> ========================= > > Verilog, Verilog, Verilog. > > I've been consulting for over 24 years now and I now focus exclusively on Verilog for a variety of reasons. > > I've seen the Verilog vs VHDL discussion many times, it boils down to either a religious or toothpaste debate - what were you raised with or what flavor do you prefer. > > I've found I am *much* more productive in Verilog. > > At this point, I don't take on jobs in VHDL. > > My $0.02. I met a guy in another forum who said not only he, but a number of people he has shown to use Verilog at work are much more productive. I've heard that there are various defaults in Verilog that are real gotchas unless you know about them. But no one has been able to point me to a book that describes these issues. Can you suggest a good Verilog book that covers these details? It doesn't have to be a beginner's book as I am pretty experienced in HDL and have even done some work in Verilog. I just want to get to the point that I won't be making student mistakes in my designs. Well, at least no more than I do in VHDL. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160403
Am 10.01.2018 um 15:17 schrieb john: > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > Is use MyHDL which gets translated into VHDL for synthesis. ThomasArticle: 160404
Am 10.01.2018 um 19:32 schrieb rickman: > I have used the Lattice XP3 FPGAs in a design I've made a lot of money > from. The parts have gone EOL but Arrow bought some 70,000+ and is > still trying to get rid of them. Seems they over estimated the market. > I had to pay a higher price to them in 2016 than I paid when they were > in production (~$10) but now they are going for around $5-$6 depending > on quantity and they still have 65,000. lol > > I wonder how cheap they would sell the lot? > > With that many left in inventory, this might be a good chip to design a > low priced hobby board from, like the TinyFPGA, but cheaper, although > there are boards on eBay using the Altera EP2C5 with half again as many > LUTs plus 13 multipliers. The board is only $15 or $18 with a > programming cable. > The firmware-only USB implementation on the TInyFPGA got me interested in them. I now have 2 on my desk. Thanks for the heads-up. ThomasArticle: 160405
On 01/13/2018 12:57 AM, rickman wrote: > I met a guy in another forum who said not only he, but a number of > people he has shown to use Verilog at work are much more productive. > I've heard that there are various defaults in Verilog that are real > gotchas unless you know about them. But no one has been able to point > me to a book that describes these issues. Can you suggest a good > Verilog book that covers these details? It doesn't have to be a > beginner's book as I am pretty experienced in HDL and have even done > some work in Verilog. I just want to get to the point that I won't be > making student mistakes in my designs. Well, at least no more than I do > in VHDL. > The best Verilog reference book that I have found is "Verilog HDL A Guide to Digital Design and Synthesis" by Samir Palnitkar. It is good enough that it lives in my book bag to get hauled to work every day (and shows it now). This is not really a beginners book, and it is not perfect, but it is the best that I have found. There are at least two editions of this out and there may be more. The second edition is the one that is most useful to me. For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference Guide" is excellent. This document can be downloaded from Mr Sutherland's web site. I work in Verilog and C depending on the phase of the project that I am in (FPGA or firmware). Swapping between Verilog and C means that looking up the exact syntax is necessary, especially around the transitions. BobHArticle: 160406
BobH wrote on 1/13/2018 11:08 AM: > On 01/13/2018 12:57 AM, rickman wrote: >> I met a guy in another forum who said not only he, but a number of people >> he has shown to use Verilog at work are much more productive. I've heard >> that there are various defaults in Verilog that are real gotchas unless >> you know about them. But no one has been able to point me to a book that >> describes these issues. Can you suggest a good Verilog book that covers >> these details? It doesn't have to be a beginner's book as I am pretty >> experienced in HDL and have even done some work in Verilog. I just want >> to get to the point that I won't be making student mistakes in my >> designs. Well, at least no more than I do in VHDL. >> > > The best Verilog reference book that I have found is "Verilog HDL A Guide to > Digital Design and Synthesis" by Samir Palnitkar. It is good enough that it > lives in my book bag to get hauled to work every day (and shows it now). > This is not really a beginners book, and it is not perfect, but it is the > best that I have found. There are at least two editions of this out and > there may be more. The second edition is the one that is most useful to me. > > For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference > Guide" is excellent. This document can be downloaded from Mr Sutherland's > web site. I work in Verilog and C depending on the phase of the project that > I am in (FPGA or firmware). Swapping between Verilog and C means that > looking up the exact syntax is necessary, especially around the transitions. Do either of these books cover the defaults issue I mention above? I have coded in Verilog by copying from existing work and that has worked pretty well for me. But that was in a day job where I had people I could ask for help if I didn't understand something and it only lasted a few months. To use Verilog on my own I would want to be sure I wasn't embedding any time bombs that would rear its ugly head after the design had been handed off to a customer. Of course, that's always possible from logic errors, but I'm talking about misuse of the language. I'd like a reference book that clearly identifies these potential problems. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160407
Do you have a YouTube example? And an example that wil synthesize in Icarus? So we can see your method compares to a standard example. -- Rick C. HodginArticle: 160408
On Saturday, January 13, 2018 at 1:31:17 PM UTC-8, Rick C. Hodgin wrote: > Do you have a YouTube example? And an example that wil=20 > synthesize in Icarus? So we can see your method compares to a > standard example. >=20 > --=20 > Rick C. Hodgin Hi Rick, Actually I have got 3 patents issued for the subject:=20 1. 9,747,252: Systematic method of coding wave-pipelined circuits in HDL. 2. 9,734,127: Systematic method of synthesizing wave-pipelined circuits in = HDL. 3. 9,575,929: Apparatus of wave-pipelined circuits. All 3 patents have the same specification, drawings, abstract with differen= t claims Here is my new non-provisional patent application 15,861,093 (application, = hereafter), "Coding wave-pipelined circuits with buffering function in HDL"= , filed to USPTO on 2018/01/03.=20 The non-provisional patent application 15,861,093 has a *txt (*.vhd) file a= ttached so that they are not secrets and any persons who are interested in = the subject can email me to get what he wants, I would email the file set t= o him, even full application set will be published 18 months later. The following is part of my sell-promotional file to some big companies: "The new application can be viewed in some extents as the continuation of t= he 3 patents logically, but legally it is a brand new invention devoting th= e main attention to coding buffering function for wave-pipelined circuits i= n HDL, a topic never mentioned in the 3 patents, while it is still paying g= reat attention to improve the 3 patents to make them more robust, friendlie= r and more complete in point of view from coding designers."=20 In the 3 previous patents a first version of source code was attached, the = new application provides the second version. With the 2nd version of VHDL s= ource code available you can use a VHDL-2002 or above simulator to simulate= all workings and generate waves. The source file is also well noted with i= nserted debugging function code. Please email me what you want me to send: for 3 patents: 1.1 Specification=20 1.2. 3 sets of claims. 1.3. Drawings. 1.4. Source code. 1.5. ZIP file of all above. For new application: 2.1 Specification. 2.2. claims. 2.3. Drawings. 2.4. Abstract. 2.5. Source code. 2.6. ZIP file of all above. For the new application, specification has 81 pages, 48 claims have 15 page= s and drawings have 24 pages. If you lack time, the best way to learn all working structures needs only 2= .1 Specification; 2.3. Drawings; and 2.4. Abstract. Because the target of my patents and new application is a) to make my inven= ted system as part of HDL (not only VHDL, but all languages in HDL), and b)= to make the source code as part of system library in HDL, I am willing to = distribute my code and all related files to any persons who are really inte= rested in how I did it. Through CPC_1_2 you may know that my scheme needs the least logic informati= on and coding from a designer to resolve a very difficult problem, an almos= t 50-years open problem.=20 My Email address is wtx wtx @ gmail . com (please remove spaces between cha= racters) Thank you. WengArticle: 160409
rickman <gnuarm.deletethisbit@gmail.com> wrote: > I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. > The parts have gone EOL but Arrow bought some 70,000+ and is still trying > to get rid of them. Seems they over estimated the market. I had to pay a > higher price to them in 2016 than I paid when they were in production (~$10) > but now they are going for around $5-$6 depending on quantity and they still > have 65,000. lol > > I wonder how cheap they would sell the lot? A while back Farnell had some ECP2 on clearance for about GBP1 each in 1-off. I bought a few dozen, not for their FPGA capability but because I wanted to try BGA soldering and they were the cheapest large (256 pin) BGA I could find. I don't remember how many they had in stock at the time, but probably about 1K. I didn't have a use for 1K at the time. > With that many left in inventory, this might be a good chip to design a low > priced hobby board from, like the TinyFPGA, but cheaper, although there are > boards on eBay using the Altera EP2C5 with half again as many LUTs plus 13 > multipliers. The board is only $15 or $18 with a programming cable. I'm confused by their branding - is it the same as the MachXO3 or ECP3? If they have SERDES that could get very interesting. I'm sceptical whether cutting $5 from the price of a comparable low-end board is going to stimulate much further demand. Are there lots of people who have the skills to get into FPGA design but are held up by lacking $5? To me the barriers seem to be tools and languages, not the price of the hardware. If there was some killer app - like Kodi is for RPi - that could be packaged up and would sell lots of boards to people who don't have to use FPGA tools, things would be different. TheoArticle: 160410
On 01/13/2018 02:28 PM, rickman wrote: > BobH wrote on 1/13/2018 11:08 AM: >> On 01/13/2018 12:57 AM, rickman wrote: >>> I met a guy in another forum who said not only he, but a number of >>> people >>> he has shown to use Verilog at work are much more productive. I've >>> heard >>> that there are various defaults in Verilog that are real gotchas unless >>> you know about them. But no one has been able to point me to a book >>> that >>> describes these issues. Can you suggest a good Verilog book that covers >>> these details? It doesn't have to be a beginner's book as I am pretty >>> experienced in HDL and have even done some work in Verilog. I just want >>> to get to the point that I won't be making student mistakes in my >>> designs. Well, at least no more than I do in VHDL. >>> >> >> The best Verilog reference book that I have found is "Verilog HDL A >> Guide to >> Digital Design and Synthesis" by Samir Palnitkar. It is good enough >> that it >> lives in my book bag to get hauled to work every day (and shows it now). >> This is not really a beginners book, and it is not perfect, but it is the >> best that I have found. There are at least two editions of this out and >> there may be more. The second edition is the one that is most useful >> to me. >> >> For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference >> Guide" is excellent. This document can be downloaded from Mr Sutherland's >> web site. I work in Verilog and C depending on the phase of the >> project that >> I am in (FPGA or firmware). Swapping between Verilog and C means that >> looking up the exact syntax is necessary, especially around the >> transitions. > > Do either of these books cover the defaults issue I mention above? I > have coded in Verilog by copying from existing work and that has worked > pretty well for me. But that was in a day job where I had people I > could ask for help if I didn't understand something and it only lasted a > few months. To use Verilog on my own I would want to be sure I wasn't > embedding any time bombs that would rear its ugly head after the design > had been handed off to a customer. Of course, that's always possible > from logic errors, but I'm talking about misuse of the language. I'd > like a reference book that clearly identifies these potential problems. > I am not sure that there is a quick answer to what you are looking for. Sutherland's Guide book is extremely short and tightly written (about 48 pages), it is written to provide quick answers on utilizing each language element. While extremely useful, I don't think it will have the answers you are looking for. You can download the whole thing for free from his site: http://sutherland-hdl.com/books_and_guides.html#V2K%20HDL%20Ref and look for yourself. He has several other books including one specifically on "gotchas" in Verilog and System Verilog that I have not read. My start in Verilog was taking Sutherland's class in the late '90s and his class text was clear and well written. Palnitkar's book has details on usage of Verilog from basic to advanced stuff. One of the main things that I use if for is understanding syntax and behavior of "advanced" language elements from outside sources.Article: 160411
> use Verilog on my own I would want to be sure I wasn't embedding any time= =20 > bombs that would rear its ugly head after the design had been handed off = to=20 > a customer. Of course, that's always possible from logic errors, but I'm= =20 > talking about misuse of the language. I'd like a reference book that=20 > clearly identifies these potential problems. Do you mean a misuse that would cause a mismatch between simulation and syn= thesis? The main type of issue I can think of that would "rear its head" l= ater would be a clock-domain-crossing problem, but that wouldn't a result o= f misusing the language. If you forget to declare a multibit wire, it will= be assumed that it's a single bit, and then you can have weird behavior be= cause you thought it was a bus, but that's probably something you're going = to quickly find in sim.=20 I do not think the Palnitkar book is good and I have never found any Verilo= g book that is very good. I have a decent one somewhere that is for engine= ers doing synthesis, though I can't remember the name, and it's more of a s= upplemental reference. You can find some papers on Cliff Cumming's Sunburs= t Design page which go over some Verilog solecisms.Article: 160412
On Wednesday, January 10, 2018 at 5:56:45 PM UTC-8, Weng Tianxiang wrote: > Hi, >=20 > A wive-pipelined circuit has the same logic as its pipeline counterpart e= xcept that the wive-pipelined circuit has only one stage, a critical path f= rom the input register passing through a piece of computational logic to th= e output register, and no intermediate registers. >=20 > My invention kernel idea is: A designer provides the least information an= d logic code about the critical path, and leave all complex logic designs t= o a synthesizer and a system library that is what an HDL should do. >=20 > All coding has 3 steps: > 1. Write a Critical Path Component (CPC) with defined interface; >=20 > 2. Call a Wave-Pipelining Component (WPC) provided by a system library; >=20 > 3. Call one of 3 link statement to link a CPC instantiation with a paired= WPC instantiation to specify what your target is. >=20 > Here is the all code on a 64*64 bits signed integer multiplier C <=3D A*B= . >=20 > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > use work.wave_pipeline_package.all; >=20 > -- CPC code for wave-pipelined 64-bit signed integer multiplier C <=3D A*= B > -- CPC_1_2 is linked with SMB by link1() / link2() if "wave" is accepted = in VHDL > -- link1(): generation would fail if the circuit cannot accept 1 data per= cycle > -- link2(): generation never fails and the circuit is capable of acceptin= g 1 data per=20 > -- INPUT_CLOCK_NUMBER cycles >=20 > entity CPC_1_2 is=20 > generic ( =20 > input_data_width : positive :=3D 64; -- optional > output_data_width : positive :=3D 128 -- optional > ); > port ( > CLK : in std_logic; > WE_i : in std_logic; -- '1': write enable to input registers = A & B=20 > Da_i : in signed(input_data_width-1 downto 0); -- input data= A > Db_i : in signed(input_data_width-1 downto 0); -- input data= B > WE_o_i: in std_logic; -- '1': write enable to output register C > Dc_o : out unsigned(output_data_width -1 downto 0) -- output dat= a C > ); > end CPC_1_2; >=20 > architecture A_CPC_1_2 of CPC_1_2 is > signal Ra : signed(input_data_width-1 downto 0); -- input register= A > signal Rb : signed(input_data_width-1 downto 0); -- input register= B > signal Rc : signed(output_data_width-1 downto 0); -- output registe= r C > signal Cl : signed(output_data_width-1 downto 0); -- combinational = logic > =20 > begin > Cl <=3D Ra * Rb; -- combinational logic output, key par= t of CPC > Dc_o <=3D unsigned(Rc); -- output through output register >=20 > p_1 : process(CLK) > begin > if Rising_edge(CLK) then > if WE_i =3D '1' then -- WE_i =3D '1' : latch input data > Ra <=3D Da_i; > Rb <=3D Db_i; > end if; > =20 > if WE_O_I =3D '1' then -- WE_O_I =3D '1': latch output data > Rc <=3D Cl; > end if; > end if; > end process; >=20 > -------------------------------------------------------------------------= ------- >=20 > end A_CPC_1_2; >=20 > In summary, after HDL adopting my system, writing a wave-pipelined circui= t is simple as writing a one-cycle logic circuit. >=20 > Thank you. >=20 > Weng Hi, Here is more information on WPC (Wave-Pipelining Component) provided by a s= ystem library (I wroted).=20 1. There are only 2 WPCs to cover all wave-piplined circuits: a) It is used for the situation under which only one critical path is use= d. b) It is used for the situation under which more than one same critical p= ath is used. 2. There are 5 types of structures of all wave-pipelined circuits based on = my classification: a) A one cycle non-pipelining circuit when it is coded as a wave-pipeline= d circuit, but finally it turns out to be a 1-cycle regular circuit. b) A wave-pipelined circuit that can accept one input data per cycle with= one critical path. c) A wave-pipelined circuit that can accept one input data per multiple c= ycles with one critical path. d) A wave-pipelined circuit that can accept one input data per cycle with= more than one critical path, each critical path having an input register a= nd an output register. e) A wave-pipelined circuit that can accept one input data per cycle with= more than one critical path, each critical path having an input register a= nd sharing a sole output register. 3. The method guarantees 100% success rate for generating a specific wave-p= ipelined circuit. Thank you. WengArticle: 160413
Theo Markettos wrote on 1/16/2018 4:55 AM: > rickman <gnuarm.deletethisbit@gmail.com> wrote: >> I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. >> The parts have gone EOL but Arrow bought some 70,000+ and is still trying >> to get rid of them. Seems they over estimated the market. I had to pay a >> higher price to them in 2016 than I paid when they were in production (~$10) >> but now they are going for around $5-$6 depending on quantity and they still >> have 65,000. lol >> >> I wonder how cheap they would sell the lot? > > A while back Farnell had some ECP2 on clearance for about GBP1 each in 1-off. > I bought a few dozen, not for their FPGA capability but because I wanted to > try BGA soldering and they were the cheapest large (256 pin) BGA I could > find. > > I don't remember how many they had in stock at the time, but probably about > 1K. I didn't have a use for 1K at the time. > >> With that many left in inventory, this might be a good chip to design a low >> priced hobby board from, like the TinyFPGA, but cheaper, although there are >> boards on eBay using the Altera EP2C5 with half again as many LUTs plus 13 >> multipliers. The board is only $15 or $18 with a programming cable. > > I'm confused by their branding - is it the same as the MachXO3 or ECP3? > If they have SERDES that could get very interesting. I'm not sure what "it" means. If you are talking about the XP Lattice device, then no, the XP family is very old and basic with just block RAM and no multipliers. The XP2 has multiplier I believe, but no SERDES. The XO2 is marketed as more of a high end CPLD functionality, again not SERDES, but I don't recall if they have multiplier. I think the XO3 might have SERDES and I'm pretty sure they have multipliers. It's hard to keep them all straight when there is so much overlap and the names don't really tell so much about the parts, except the XPx and XOx lines are all flash while the ECPx lines are all RAM based like the Xilinx parts. > I'm sceptical whether cutting $5 from the price of a comparable low-end > board is going to stimulate much further demand. Are there lots of people > who have the skills to get into FPGA design but are held up by lacking $5? > To me the barriers seem to be tools and languages, not the price of the > hardware. The point is people reach for a $5 MCU board and learn the skills to program it vs. reaching for a $20+ FPGA board to learn the skills. There is a particular MCU on eBay that is sold on a board for $3 I think. FPGA can't touch that! > If there was some killer app - like Kodi is for RPi - that could be > packaged up and would sell lots of boards to people who don't have to use > FPGA tools, things would be different. Kodi? Never heard of it. I guess I was killed. I don't understand what you mean about not having to use FPGA tools. What exactly are you proposing? -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160414
Kevin Neilson wrote on 1/16/2018 8:33 PM: > >> use Verilog on my own I would want to be sure I wasn't embedding any time >> bombs that would rear its ugly head after the design had been handed off to >> a customer. Of course, that's always possible from logic errors, but I'm >> talking about misuse of the language. I'd like a reference book that >> clearly identifies these potential problems. > > Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim. In VHDL everything is explicitly stated, no assumptions. In Verilog my understanding is there are things that are assumed that you need to know about or the tools will do something other than what you expect. It is not possible to test everything, so some of these may be missed unless you are wary of them. I don't recall anything about them, but I think some have to do with arithmetic. In VHDL you specify the bus widths of operands, results and even intermediates. I believe Verilog is consistent, but what it does may not be obvious. > I do not think the Palnitkar book is good and I have never found any Verilog book that is very good. I get this a lot. > I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms. > -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160415
On 13/01/18 12:29, Thomas Heller wrote: > Am 10.01.2018 um 15:17 schrieb john: >> >> I'm trying to decide on which to use for a project as the main default that may >> include a number of freelance people. >> >> can you say which of these you actually use (the most) >> and have the best skills in >> >> Verilog >> systemVerilog >> SystemC >> VHDL >> Other >> > > Is use MyHDL which gets translated into VHDL for synthesis. > > Thomas > I had a look at MyHDL a while ago and it looked promising. Can you share some experiences, pointers, etc? I'd like to know from someone who actually is using it! PereArticle: 160416
On Sat, 13 Jan 2018 13:31:14 -0800 (PST) "Rick C. Hodgin" <rick.c.hodgin@gmail.com> wrote: > Do you have a YouTube example? And an example that wil > synthesize in Icarus? So we can see your method compares to a > standard example. There is perhaps some explanation in "Wave-Pipelining: A Tutorial and Research Survey"[1], and "DESIGN AND TIMING ANALYSIS OF WAVE PIPELINED CIRCUITS"[2]. Jan Coombs -- [1] IEEE Transactions on VLSI Systems http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.1783&rep=rep1&type=pdf [2] Recep Ozgun's MSc thesis https://soar.wichita.edu/bitstream/handle/10057/383/t06064.pdf?sequence=3Article: 160417
On Tuesday, January 16, 2018 at 11:40:55 PM UTC-8, Jan Coombs wrote: > On Sat, 13 Jan 2018 13:31:14 -0800 (PST) > "Rick C. Hodgin" <rick.c.hodgin@gmail.com> wrote: >=20 > > Do you have a YouTube example? And an example that wil=20 > > synthesize in Icarus? So we can see your method compares to a > > standard example. >=20 > There is perhaps some explanation in "Wave-Pipelining: A > Tutorial and Research Survey"[1], and "DESIGN AND TIMING > ANALYSIS OF WAVE PIPELINED CIRCUITS"[2]. >=20 > Jan Coombs > --=20 >=20 > [1] IEEE Transactions on VLSI Systems=20 > http://citeseerx.ist.psu.edu/viewdoc/download?doi=3D10.1.1.90.1783&rep=3D= rep1&type=3Dpdf >=20 > [2] Recep Ozgun's MSc thesis > https://soar.wichita.edu/bitstream/handle/10057/383/t06064.pdf?sequence= =3D3 Hi Jan, I appreciate your efforts to dig deep into my inventions.I would like to pa= tiently answer all reasonable technical questions.=20 Your reference [1] is none but what activates my inspiration to resolve the= open problem: design both a coding and a synthesizing methods so that any = logic design engineers, including college students with basic knowledge in = HDL, can code and generate a wave-piplined circuit. All published materials I have read are centered on how to eliminate data c= ontamination, a special feature which is never heard in any non-wave-pipeli= ned circuit design. A data contamination is defined as a later entered data catches up an earli= er entered data, damaging the earlier entered data. What my inventions do is to build a bridge between code designers and synth= esizers in order to code and generate a wave-pipelined circuit in the easie= st way: If a code designer provides all necessary and sufficient information to a s= ynthesizer, the synthesizer should and can generate a wave-pipelined circui= t as it is specified.=20 Your reference [1] (1998) at page 142 below table 1 indicates that "Last, d= ue to a lack of commercial tools that are directly applicable to designs us= ing wave-pipelining, each group has more or less developed in-house design = analysis and optimization tools which enable VLSI design using wave-pipelin= ing." So I have assumed at the beginning of my project that if a new part on wave= -pipelined circuit in HDL standard is well designed and laid out,any synthe= sizer manufacturers have the ability to generate a wave-pipelined circuit. = The assumption was also based on your reference [1] (1998) at table 1 at pa= ge 142 where it indicates there are 30 wave-pipelined circuits (20 years ag= o), none of their authors have any relationships with a professional synthe= sizer manufacturer. Furthermore during the development period I found that no matter how many t= ypes of wave-pipelined circuits are in the past or in the future, each of a= ll wave-pipelined circuits comprises two part, one is the critical path, pr= esented by CPC (Critical Path Component), all remaining logic is always the= same for a group of wave-pipelined circuits WPC (Wave-Pipelining Component= ), depending on what target a designer wants for his circuit. In my design no timings related to a wave-pipelined circuit appear, never, = because they are within the scope of a synthesizer operation and have nothi= ng to do with their coding. There is no a commercial synthesizer in the world which can directly genera= te a wave-pipelined circuit. To prove my WPCs are correct, I coded a CPC wh= ich does nothing but passes the data in the critical path obeying a critica= l path behavior: if the critical path needs 5 cycle for signals to travel, = its output would be available in 6 cycles and if the critical path is block= ed, a later entered data would have a chance to damage an earlier entered d= ata if design is not right. So essentially I have no very sophisticated too= ls used, nor timing analysis. Thank you. WengArticle: 160418
On Tuesday, January 16, 2018 at 6:21:06 PM UTC-8, rickman wrote:
> Kevin Neilson wrote on 1/16/2018 8:33 PM:
> >
> >> use Verilog on my own I would want to be sure I wasn't embedding any t=
ime
> >> bombs that would rear its ugly head after the design had been handed o=
ff to
> >> a customer. Of course, that's always possible from logic errors, but =
I'm
> >> talking about misuse of the language. I'd like a reference book that
> >> clearly identifies these potential problems.
> >
> > Do you mean a misuse that would cause a mismatch between simulation and=
synthesis? The main type of issue I can think of that would "rear its hea=
d" later would be a clock-domain-crossing problem, but that wouldn't a resu=
lt of misusing the language. If you forget to declare a multibit wire, it =
will be assumed that it's a single bit, and then you can have weird behavio=
r because you thought it was a bus, but that's probably something you're go=
ing to quickly find in sim.
>=20
> In VHDL everything is explicitly stated, no assumptions. In Verilog my=
=20
> understanding is there are things that are assumed that you need to know=
=20
> about or the tools will do something other than what you expect. It is n=
ot=20
> possible to test everything, so some of these may be missed unless you ar=
e=20
> wary of them. I don't recall anything about them, but I think some have =
to=20
> do with arithmetic. In VHDL you specify the bus widths of operands, resu=
lts=20
> and even intermediates. I believe Verilog is consistent, but what it doe=
s=20
> may not be obvious.
>=20
>=20
> > I do not think the Palnitkar book is good and I have never found any Ve=
rilog book that is very good.
>=20
> I get this a lot.
>=20
>=20
> > I have a decent one somewhere that is for engineers doing synthesis, th=
ough I can't remember the name, and it's more of a supplemental reference. =
You can find some papers on Cliff Cumming's Sunburst Design page which go =
over some Verilog solecisms.
> >
>=20
>=20
> --=20
>=20
> Rick C
>=20
> Viewed the eclipse at Wintercrest Farms,
> on the centerline of totality since 1998
I have not yet found a Verilog book that I thought was worth buying :(
I'd look for papers by Sutherland and Cliff Cummings, especially, I think, =
Cliff's book on Verilog gotchas.
The key rule I use for Verilog is when coding combinatorial blocks, use
blocking assignments:
always @(*)
foo =3D bar;
When coding synchronous logic, use non-blocking assignments:
always @(posedge clk)
foo <=3D bar;
Rules are made to be broken, but I *rarely* break these two rules.
John P
Article: 160419Am 17.01.2018 um 08:37 schrieb o pere o: > On 13/01/18 12:29, Thomas Heller wrote: >> Am 10.01.2018 um 15:17 schrieb john: >>> >>> can you say which of these you actually use (the most) >>> and have the best skills in >>> >>> Verilog >>> systemVerilog >>> SystemC >>> VHDL >>> Other >>> >> >> Is use MyHDL which gets translated into VHDL for synthesis. >> > > I had a look at MyHDL a while ago and it looked promising. Can you share > some experiences, pointers, etc? I'd like to know from someone who > actually is using it! I'm not good at writing reviews, but I'm very happy with MyHDL. It removes the pain that I mostly feel when writing VHDL. And using MyHDL is the first time that I write real testbenches and simulate. Something that I can recommend to read about MyHDL are articles by Jan Decaluwe, the main author, at http://jandecaluwe.com/hdldesign/ . Especially this one: http://jandecaluwe.com/hdldesign/counting.html . Then Christopher Felton also has a couple of nice articles at fpgarelated: https://www.fpgarelated.com/blogs-1/nf/Christopher_Felton.php ThomasArticle: 160420
On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote: > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > > -- > > john > > ========================= > http://johntech.co.uk > ========================= I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around. For a reference I recommend: RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.Article: 160421
Mark Humphries wrote on 1/18/2018 10:34 AM: > On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote: >> I'm trying to decide on which to use for a project as the main default that may >> include a number of freelance people. >> >> can you say which of these you actually use (the most) >> and have the best skills in >> >> Verilog >> systemVerilog >> SystemC >> VHDL >> Other >> >> And if possible what type of work you use it for in general >> I dont need to know why you use a particular one - and to avoid >> flame wars request you dont explain that. >> >> I'm just trying to get a general feel for what people here use regularly. >> >> TIA >> >> -- >> >> john >> >> ========================= >> http://johntech.co.uk >> ========================= > > I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around. > > For a reference I recommend: > RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland. Seems to be a $120 book. That's a bit steep even for HDL books. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160422
john <anon@example.com> wrote: > > I'm trying to decide on which to use for a project as the main default > that may include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in Bluespec SystemVerilog (BSV), which is actually nothing to do with SystemVerilog but is a high-level HDL derived from Haskell (including types, polymorphism, functional language features). Since BSV is a bit niche, I teach SystemVerilog to undergrads and will use it for glue when necessary. Talking to major IP vendors who provide both Verilog and VHDL versions of IP, the Verilog versions are a lot more popular. TheoArticle: 160423
Hi,
I have told that my invention kernel idea is: A designer provides the least=
information and logic code about the critical path, and leaves all complex=
logic designs to a synthesizer and a system library that is what an HDL sh=
ould do.=20
Here are the technique key points that I have used used to fully develop my=
technique, assuming that you are an experienced code designer in HDL.
Even though the technique is tricky, but it is easy to understand if you fu=
lly understand the concepts in this and next posts, each in 20 or more minu=
tes for 80% engineers here
Here I am using 64*64 bits signed multiplexer as the target circuit example=
.
1. If my CPC_1_2 code is presented to a synthesizer, the first question you=
may ask is how do you code your WPC (Wive-Pipelining Component). For clari=
ty, I copied the CPC_1_2 code here again.
By the way, I claim that nobody can further simplify the CPC_1_2 code to de=
liver full information about a critical path to a synthesizer for generatin=
g a wave-pipelined circuit! If you can, please challenge my claim.=20
entity CPC_1_2 is=20
generic ( =20
input_data_width : positive :=3D 64; -- optional=
=20
output_data_width : positive :=3D 128 -- optional=
=20
);=20
port (=20
CLK : in std_logic;=20
WE_i : in std_logic; -- '1': write enable to input registers A =
& B=20
Da_i : in signed(input_data_width-1 downto 0); -- input data A=
=20
Db_i : in signed(input_data_width-1 downto 0); -- input data B=
=20
WE_o_i: in std_logic; -- '1': write enable to output register C=20
Dc_o : out unsigned(output_data_width -1 downto 0) -- output data =
C=20
);=20
end CPC_1_2;=20
architecture A_CPC_1_2 of CPC_1_2 is=20
signal Ra : signed(input_data_width-1 downto 0); -- input register A=
=20
signal Rb : signed(input_data_width-1 downto 0); -- input register B=
=20
signal Rc : signed(output_data_width-1 downto 0); -- output register =
C=20
signal Cl : signed(output_data_width-1 downto 0); -- combinational lo=
gic=20
=20
begin=20
Cl <=3D Ra * Rb; -- combinational logic output, key part =
of CPC=20
Dc_o <=3D unsigned(Rc); -- output through output register=20
p_1 : process(CLK)=20
begin=20
if Rising_edge(CLK) then=20
if WE_i =3D '1' then -- WE_i =3D '1' : latch input data=20
Ra <=3D Da_i;=20
Rb <=3D Db_i;=20
end if;=20
=20
if WE_O_I =3D '1' then -- WE_O_I =3D '1': latch output data=20
Rc <=3D Cl;=20
end if;=20
end if;=20
end process;=20
end A_CPC_1_2;=20
2. Assume 3 situations:
a) If you know that each data needs 5 cycles to pass the 64*64 bits signed =
multiplexer and the circuit can accept one data per cycle, you should know =
how to code the WPC for the circuit. Because we have already assumed that t=
he synthesizer is capable of generating the wave-pipelined circuit for it, =
leaving most difficult task to the synthesizer. By definition a WPC contain=
s all remaining logic for the circuit except the CPC_1_2.=20
b) If you know that each data needs 5 cycles to pass the 64*64 bits signed =
multiplexer and the circuit can accept one data per 2 cycles, you should kn=
ow how to code the WPC for the circuit.
c) If you know that each data needs 5 cycles to pass the 64*64 bits signed =
multiplexer and the circuit can accept one data per 2 cycles, but the desig=
ner wants the circuit to be able of accepting one data per cycle, not one d=
ata per 2 cycles, you should know how to code the WPC for the circuit with =
2 copies of critical paths and each alternatively accepting an input data p=
er 2 cycles. Actually all CPCs have 2 types of code patterns, CPC_1_2 is on=
e of them and another CPC_3 is slightly complex, but is an off shelf coding=
pattern either.In this situation CPC_3 code would replace CPC_1_2 with sam=
e input and output interfaces.
Now the problem comes: how do you know all 3 unknown parameters before you =
code the WPC for the 64*64 bits signed multiplexer? I think that this is th=
e key reason why so many wave-pipelined circuits have been generated, but n=
one of the circuits designers can resolve the 50 years old open problem.
And the circuit may, should and can be any type of pipelined circuits!
To be continued.
I would like to listen to your questions and comments!
Weng
=20
Article: 160424Weng Tianxiang wrote on 1/10/2018 8:56 PM: > Hi, > > A wive-pipelined circuit has the same logic as its pipeline counterpart except that the wive-pipelined circuit has only one stage, a critical path from the input register passing through a piece of computational logic to the output register, and no intermediate registers. > > My invention kernel idea is: A designer provides the least information and logic code about the critical path, and leave all complex logic designs to a synthesizer and a system library that is what an HDL should do. > > All coding has 3 steps: > 1. Write a Critical Path Component (CPC) with defined interface; > > 2. Call a Wave-Pipelining Component (WPC) provided by a system library; > > 3. Call one of 3 link statement to link a CPC instantiation with a paired WPC instantiation to specify what your target is. > > Here is the all code on a 64*64 bits signed integer multiplier C <= A*B. > > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > use work.wave_pipeline_package.all; > > -- CPC code for wave-pipelined 64-bit signed integer multiplier C <= A*B > -- CPC_1_2 is linked with SMB by link1() / link2() if "wave" is accepted in VHDL > -- link1(): generation would fail if the circuit cannot accept 1 data per cycle > -- link2(): generation never fails and the circuit is capable of accepting 1 data per > -- INPUT_CLOCK_NUMBER cycles > > entity CPC_1_2 is > generic ( > input_data_width : positive := 64; -- optional > output_data_width : positive := 128 -- optional > ); > port ( > CLK : in std_logic; > WE_i : in std_logic; -- '1': write enable to input registers A & B > Da_i : in signed(input_data_width-1 downto 0); -- input data A > Db_i : in signed(input_data_width-1 downto 0); -- input data B > WE_o_i: in std_logic; -- '1': write enable to output register C > Dc_o : out unsigned(output_data_width -1 downto 0) -- output data C > ); > end CPC_1_2; > > architecture A_CPC_1_2 of CPC_1_2 is > signal Ra : signed(input_data_width-1 downto 0); -- input register A > signal Rb : signed(input_data_width-1 downto 0); -- input register B > signal Rc : signed(output_data_width-1 downto 0); -- output register C > signal Cl : signed(output_data_width-1 downto 0); -- combinational logic > > begin > Cl <= Ra * Rb; -- combinational logic output, key part of CPC > Dc_o <= unsigned(Rc); -- output through output register > > p_1 : process(CLK) > begin > if Rising_edge(CLK) then > if WE_i = '1' then -- WE_i = '1' : latch input data > Ra <= Da_i; > Rb <= Db_i; > end if; > > if WE_O_I = '1' then -- WE_O_I = '1': latch output data > Rc <= Cl; > end if; > end if; > end process; > > -------------------------------------------------------------------------------- > > end A_CPC_1_2; > > In summary, after HDL adopting my system, writing a wave-pipelined circuit is simple as writing a one-cycle logic circuit. > > Thank you. > > Weng What is SMB? I think I understand the concept of wave pipelining. It is just eliminating the intermediate registers of a pipeline circuit and designing the combinational logic so that the delays are even enough across the many paths so the output can be clocked at a given time and will receive a stable result from the input N clocks earlier. In other words, the logic is designed so that the changes rippling through the logic never catch up to the changes created by the data entered 1 clock cycle earlier. Nice if you can do it. I can see where this would be useful in an ASIC. In ASICs FFs and logic compete for space within the chip. In FPGAs the ratio between FFs and logic are fixed and predetermined. So using logic without using the FFs that are already there is not of much value. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998
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