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Hello, I am looking for a substitut component for the XC17*** PROM by Xilinx. * Flash Memory or EEMemory * ISP Programing thrugh JTag. Thank you KerenArticle: 18051
I think that Stephan meant http://www.distributed.net correct me if I'm wrong. Stephan Diemer <s.diemer@gmx.de> wrote in message news:7sj1nj$g4i$1@news.online.de... > Hello friends i am an absolut newbie so i dont know anything about > programmable logic but i am very interested in this issue. What i want to do > is building or programming a PCI card with some algorithms (for RC5 > decoding). I know that it would be a wonder if i get this working so i am > searching someone with the same interests who could help me or do it. > If someone want to help me please visit www.ditributed.net so you will > see why i want to build this and e-mail me! > > thanx > >Article: 18052
Check the Xilinx web site. I believe they have a new part that meets your requirements. It may not be 'out' yet, but will be soon... Keren <keren2@inter.net.il> wrote in article <7skstj$84d$1@news2.inter.net.il>... > Hello, > > I am looking for a substitut component for the XC17*** PROM by Xilinx. > * Flash Memory or EEMemory > * ISP Programing thrugh JTag. > > Thank you > > Keren > > > > >Article: 18053
Yes you´re right. Stephan Diemer wrote: > Hello friends i am an absolut newbie so i dont know anything about > programmable logic but i am very interested in this issue. What i want to do > is building or programming a PCI card with some algorithms (for RC5 > decoding). I know that it would be a wonder if i get this working so i am > searching someone with the same interests who could help me or do it. > If someone want to help me please visit www.ditributed.net so you will > see why i want to build this and e-mail me! > > thanxArticle: 18054
Yes, you do need an include file. You can do this by opening the lowwer level design with the text editor, and then selecting Generate Include file under the File menu. This could cause the project name to get changed to the lowwer level, and then you will need to change it back. Once you actually have a working hierarchy, then you can use the project view, double click on the file, and then select create new include. This will not cause the project name to change. John Becich wrote: > It seems, when one works exclusively with text entry, that in order to build > hierarchical designs using Max+Plus 9.3, one must INCLUDE > "'smaller-design'.inc"; > where 'smaller-design' is the name of some lower level module that we wish > to use within the file we are building. > > Simply put, that means I have to have an ".inc" file for the smaller module, > or building a hierarchical design won't work! > Does anyone agree or disagree with this observation? > > Megafunctions and megafunctions that I modify seem to render .inc files OK. > I have not, however, been able to produce .inc files from the graphic or > textual files that I create from scratch, without using the "Megawizard." > > Am I missing something? > > Thanks, > JohnArticle: 18055
The simplest thing to do is use the init state of all 0, since the FPGA will bring all registers to 0 unless you do something special. (Special means different languages and compilers may require different things.) If you try to reset the device once configured, then you have the problem of multiple reset signals. Some compilers/languages allow other approaches to the inital state problem. For example, AHDL uses a MACHINE construct in which the first state listed in the construct will be the init state. I have seen different aproaches with different Verilog compilers. Currently Altera does not support 1 hot statemachine in Verilog, thus the 0 state is the init state. Others that support 1 hot actually use the first state again. micheal_thompson@my-deja.com wrote: > Hi > I have implemented a few state machines (binary encoded!)in this device > and am wondering how I get them to go to the 'init' state on power-up. > Design entry was VHDL so I'm making no assumptions on whether the FSM > init state is clear or preset. ( For example, the init state is not > always the first state in the declaration list). > As far as I understand all the Flex 10k registers will be cleared just > after configuration? > I considered an external reset-pin driven by a reset-ic. A possible > shortcoming of this though maybe that the Flex's configuration time (c. > 200ms)could exceed my minimum reset pulse-width (most parts specify a > minimum 100ms pulse) so my pulse would never be seen. > Any thoughts would be appreciated! > > regds > Mike > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18056
This is a multi-part message in MIME format. --------------40C5F7C45B7E8BFA9CB4D3E1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, U can find a lot of info on evolvable hardware in the forms of reconfigurable computing, or custom computing. But if U get a chance to read the Magazine called "Communications of the ACM, April 1999- Volume 42, Number 4", it talks a lot about Evolvable Hardware.. All the best Regards Anup Kumar, University of Queensland, Australia. Stephen Kempenaers wrote: > Hi, > I have to write a thesis about evolvable hardware, but everywhere i look, i > find other defenitions, can somebody refer me to a site where i can find > detailed information about this subject > > thxs in advance --------------40C5F7C45B7E8BFA9CB4D3E1 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup kumar raghavan Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:0061-7-38761962 tel;work:0061-7-33658849 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:anup@elec.uq.edu.au fn:Anup end:vcard --------------40C5F7C45B7E8BFA9CB4D3E1--Article: 18057
This is a multi-part message in MIME format. --------------8752160F8239A9EB51129FBD Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi again, U can try the web site www.vcc.com It talks abour EWH Cheers Anup Stephen Kempenaers wrote: > Hi, > I have to write a thesis about evolvable hardware, but everywhere i look, i > find other defenitions, can somebody refer me to a site where i can find > detailed information about this subject > > thxs in advance --------------8752160F8239A9EB51129FBD Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup kumar raghavan Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:0061-7-38761962 tel;work:0061-7-33658849 x-mozilla-html:FALSE adr:;;;;;; version:2.1 email;internet:anup@elec.uq.edu.au fn:Anup end:vcard --------------8752160F8239A9EB51129FBD--Article: 18058
Does anyone who uses Foundation under windoze know how to to get a site id for the Synopsys site? They assume that the whole world uses unix. Novel. I assume that the site id is in a license file that come with FPGA Express, but I'll be dammed if I can find it. Cheers -- --------------------------------------------------------------------------------------------- David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm Centre for Intelligent Systems Swinburne University of Technology --------------------------------------------------------------------------------------------Article: 18059
Keren wrote:
>
> I am looking for a substitut component for the XC17*** PROM by Xilinx.
> * Flash Memory or EEMemory
> * ISP Programing thrugh JTag.
Atmel supplies direct replacements for the XC17* series. You should be
able to find data sheets etc. at http://www.atmel.com
Look under 'Memory', then 'FGPGA Configuration Memory'. They are
available from stock (the last time I inquired).
--
Hukt on fonix werkt fer me!
http://cr347197-a.surrey1.bc.wave.home.com/larry/
Article: 18060Hi there, if you can figure out whether fpga xpress users are elidgible to get direct support from and access to the solve-it site at synopsys, pls. let us know about your findings. I've tried to solve an issue some time ago, and the synopsys attitude was, that since xilinx oem-bundles their product with their tools, they don't want to know anything about these user requests. bye for now, kostas david braendler wrote: > > Does anyone who uses Foundation under windoze know how to to get a site > id for the Synopsys site? They assume that the whole world uses unix. > Novel. > > I assume that the site id is in a license file that come with FPGA > Express, but I'll be dammed if I can find it. > > Cheers > > -- > --------------------------------------------------------------------------------------------- > > David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm > Centre for Intelligent Systems > Swinburne University of Technology > --------------------------------------------------------------------------------------------Article: 18061
Does anyone have a definition of the REV on the Virtex flip-flops? A search at Xilinx reveals nothing. This connection pairs with INIT on each FF -- INIT seems to be set/reset. Many thanks. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18062
hi there, REV seems to be the synchronous reset input. INIT on the other hand links to the synchronous set. kostas simon_bacon@my-deja.com wrote: > > Does anyone have a definition of the REV on the Virtex flip-flops? > A search at Xilinx reveals nothing. This connection pairs with > INIT on each FF -- INIT seems to be set/reset. > > Many thanks. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 18063
This is a multi-part message in MIME format. --------------E26B008FAABA2F743CA611F0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Try one of the Atmel 17C*** eeproms if they are big enough to hold your bitstream. Keren wrote: > Hello, > > I am looking for a substitut component for the XC17*** PROM by Xilinx. > * Flash Memory or EEMemory > * ISP Programing thrugh JTag. > > Thank you > > Keren --------------E26B008FAABA2F743CA611F0 Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;David tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;28560 fn:Dave Vanden Bout end:vcard --------------E26B008FAABA2F743CA611F0--Article: 18064
I am interested to know if any one has used the LVDS IO on the 20KE? If so what are your experiences with it and where can I get hold of detailed timing and electrical specifications? (They have yet to be included in the 20K data sheet.) My interest is in the possibility of using the LVDS IO for direct input from a 500 MSPS ADC with LVDS output.Article: 18065
Hello. I am currently writing a thesis on EHW, and I wondered if anyone have tried to manipulate a Virtex's configuartion bits by genetic operations ? Best Regards Espen Tislevoll e-mail: tislevol@idi.ntnu.noArticle: 18066
On Sun, 26 Sep 1999 11:21:03 -0400, in <37EE39DF.CF49E5C1@programmable-products.com> Brad Ree <brad.ree@programmable-products.com> wrote: >Yes, you do need an include file. You can do this by opening the lowwer level >design with the text editor, and then selecting Generate Include file under the >File menu. This could cause the project name to get changed to the lowwer >level, and then you will need to change it back. Once you actually have a >working hierarchy, then you can use the project view, double click on the file, >and then select create new include. This will not cause the project name to >change. Do watch out for the fact that if you change the I/Os on the schematic, the .inc file is not automatically updated. > > >John Becich wrote: > >> It seems, when one works exclusively with text entry, that in order to build >> hierarchical designs using Max+Plus 9.3, one must INCLUDE >> "'smaller-design'.inc"; >> where 'smaller-design' is the name of some lower level module that we wish >> to use within the file we are building. >> >> Simply put, that means I have to have an ".inc" file for the smaller module, >> or building a hierarchical design won't work! >> Does anyone agree or disagree with this observation? >> >> Megafunctions and megafunctions that I modify seem to render .inc files OK. >> I have not, however, been able to produce .inc files from the graphic or >> textual files that I create from scratch, without using the "Megawizard." >> >> Am I missing something? >> >> Thanks, >> John -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.uk/ -- remember to despam return addressArticle: 18067
In article <37ecf381.2226175@news.freeserve.net>, martin@nospam.the-thompsons.freeserve.co.uk wrote: > Mike, > I've used the INIT_DONE or CONF_DONE (can't remember which, > I'm not at work at the mo') pins out of the 10K. If you have a signal > called reset internally, feed the x_DONE pin into whichever pin this > signal comes out on. The compiler usually puts it on a global input. > > I seem to remember needing an inverter somewhere, as some of the LPM's > I was using expected an active high reset, but the DFF's didn't. Or > something. > > If that helps, great. If not, let me know and I'll dig out > some details from work (try me on martin.thompson2@lucasvarity.com for > best success!) > > HTH, > Martin Martin Thanks for your suggestion. This brings up two points for me: 1. I'm just wondering would I get an extra degree of 'security' if I made a small extension to your idea: between the init_done o/p (Open-drain) and the 'reset' input hook up an open-drain reset-ic's push-button_in/ reset_out pin. In this way I will get a 'post-init' extension of the reset pulse thereby ensuring that the pulse is definitely 'seen'. 2. The other point is that depending on the compiler ( I use FPGA-xpress) implementation maybe this is all overkill? The compiler has (I think) 2 choices in how it implements a state-machine reset: A) Connects ALL FSM_ff.CLR pins to the reset signal and places inverters on those FSM_ff.Q's that need to be preset on init. B) Connects the reset signal to a mix of FSM_ff.CLR and FSM_ff.SET. Therefore if method 'A' is used all FFlops cleared will also mean all FSMs are in their init-states and so I won't need an external reset-ic. Maybe! regds Mike Sent via Deja.com http://www.deja.com/ Before you buy.Article: 18068
"Stephen Kempenaers" <stephenk6@excite.com> writes:
> I have to write a thesis about evolvable hardware, but everywhere i look, i
> find other defenitions, can somebody refer me to a site where i can find
> detailed information about this subject
I would start out reading an introductory article by Yao and Higuchi:
X. Yao and T. Higuchi, ``Promises and Challenges of Evolvable
Hardware,'' IEEE Transactions on Systems, Man, and
Cybernetics, Part C, 28(4), November 1998.
Available as
<url:ftp://www.cs.adfa.oz.au/pub/xin/smc097-04-0453.ps.gz>
Also this link should contain a lot of interesting articles
<url:http://www.etl.go.jp/etl/divisions/~ehw/> (the articles are in
the download-section)
-sig
--
sigurd urdahl
Article: 18069I'm looking for a Philips SAA7146A (multimedia bridge, high performance scaler and PCI circuit) SDK/drivers/utilities. Where is it possible to download it ? Thanks With best regards, Gennadij Volkov gennadij@telemed.lt ---------------------------------------------Article: 18070
- Based on the 0.18 µm, 6LM process vs. a 0.25 µm 5LM process for Virtex - Over 3x density increase (from 1 million to 3.2 million system gates) - 1.3x speed grade performance - Over 1.5x number of user I/Os (from 512 to 804) - Over 1.5x I/O performance (from 200 MHz to over 311 MHz) - 6.5x the internal block memory (from 128 Kbits to 832 Kbits) - 2x the number of DLLs (from 4DLLs to 8 DLLs) - Available with more advanced fine pitch packaging (FG860, FG900, and FG1156) support bringing the max I/O count up to 804 - Support three differential I/O standards: LVDS, Bus LVDS, and LVPECL (from supporting 17 I/O standards to 20 I/O standards) - Capable of delivering 622 Megabits per second (Mbps) differential I/O performance There are press releases, datasheets and new application notes available at: http://www.xilinx.com Enjoy! Best Regards, Rune BaeverrudArticle: 18071
There are a couple of decent tutorials listed on The Programmable Logic Jump Station at http://www.optimagic.com/tutorials.html. -- ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Keith Tobin <keith@suparule.com> wrote in message news:7sn7e5$t5s$1@scotty.tinet.ie... > I want to learn VHDL to be used on fpga's , what i wand to > know is any good sites with info , > > Thanking Ye ..... > >Article: 18072
--------------A6D62391A22C14AA39B6EAAB Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit We just started a new design using a PowerPC microcontroller (MPC823) on the motherboard. This board will be plugged in VME system. We also would like to put a PC/104 interface on this motherboard. How can we easily interface the MPC823 and the VME bus (chipset, fpga, application note...) for 16-bit bus (3U) and 32-bit bus (6U) ? How can we easily interface the MPC823 and the PC/104 (ISA) bus (chipset, fpga, application notes....)? How could we design an interface to plug PC/104 modules (ISA bus) on a VME board? Existing boards or design? Many thanks for your ideas and tips! +----- ----------------------------------------------------+ | Daniel Schneider | | Secheron Ltd. Phone: +4131 / 990 71 84 | | Untermattweg 8 Fax: +4131 / 990 72 22 | | CH-3027 Bern E-mail: daniel.schneider@secheron.com | +----------------------------------------------------------+ --------------A6D62391A22C14AA39B6EAAB Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> We just started a new design using a PowerPC microcontroller (MPC823) on the motherboard. <br>This board will be plugged in VME system. <br>We also would like to put a PC/104 interface on this motherboard. <p>How can we easily interface the MPC823 and the VME bus (chipset, fpga, application note...) for 16-bit bus (3U) and 32-bit bus (6U) ? <p>How can we easily interface the MPC823 and the PC/104 (ISA) bus (chipset, fpga, application notes....)? <p>How could we design an interface to plug PC/104 modules (ISA bus) on a VME board? <br>Existing boards or design? <p>Many thanks for your ideas and tips! <p><font face="Courier New,Courier"><font size=-1>+----- ----------------------------------------------------+</font></font> <br><font face="Courier New,Courier"><font size=-1>| Daniel Schneider |</font></font> <br><font face="Courier New,Courier"><font size=-1>| Secheron Ltd. Phone: +4131 / 990 71 84 |</font></font> <br><font face="Courier New,Courier"><font size=-1>| Untermattweg 8 Fax: +4131 / 990 72 22 |</font></font> <br><font face="Courier New,Courier"><font size=-1>| CH-3027 Bern E-mail: daniel.schneider@secheron.com |</font></font> <br><font face="Courier New,Courier"><font size=-1>+----------------------------------------------------------+</font></font> <br> <br> </html> --------------A6D62391A22C14AA39B6EAAB--Article: 18073
What is the availability? I've got a current customer that could use higher density than the XCV1000, but he needs it today. Rune Baeverrud wrote: > - Based on the 0.18 µm, 6LM process vs. a 0.25 µm 5LM process for Virtex > - Over 3x density increase (from 1 million to 3.2 million system gates) > - 1.3x speed grade performance > - Over 1.5x number of user I/Os (from 512 to 804) > - Over 1.5x I/O performance (from 200 MHz to over 311 MHz) > - 6.5x the internal block memory (from 128 Kbits to 832 Kbits) > - 2x the number of DLLs (from 4DLLs to 8 DLLs) > - Available with more advanced fine pitch packaging (FG860, FG900, and > FG1156) support bringing the max I/O count up to 804 > - Support three differential I/O standards: LVDS, Bus LVDS, and LVPECL (from > supporting 17 I/O standards to 20 I/O standards) > - Capable of delivering 622 Megabits per second (Mbps) differential I/O > performance > > There are press releases, datasheets and new application notes available at: > > http://www.xilinx.com > > Enjoy! > > Best Regards, > Rune Baeverrud -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18074
On Mon, 27 Sep 1999 10:29:16 GMT, micheal_thompson@my-deja.com wrote: > >Martin >Thanks for your suggestion. This brings up two points for me: >1. >I'm just wondering would I get an extra degree of 'security' if I made >a small extension to your idea: between the init_done o/p (Open-drain) >and the 'reset' input hook up an open-drain reset-ic's push-button_in/ >reset_out pin. In this way I will get a 'post-init' extension of the >reset pulse thereby ensuring that the pulse is definitely 'seen'. Hi Mike, Sounds like that might be a good belt-and-braces plan, but the Altera FAE I spoke to about it seemed to think it would be OK the way it was. Admittedly, he didn't sound *hugely* confident, and this is the first time I've used a FLEX series device (a 6016, but the guts look much like the 10K so it should be the same)! >2. >The other point is that depending on the compiler ( I use FPGA-xpress) >implementation maybe this is all overkill? The compiler has (I think) 2 >choices in how it implements a state-machine reset: A) Connects ALL >FSM_ff.CLR pins to the reset signal and places inverters on those >FSM_ff.Q's that need to be preset on init. B) Connects the reset signal >to a mix of FSM_ff.CLR and FSM_ff.SET. >Therefore if method 'A' is used all FFlops cleared will also mean all >FSMs are in their init-states and so I won't need an external reset-ic. >Maybe! > This may be why I couldn't find much information about how to do this anywhere. The tools may make it a non-issue! >regds >Mike > > >Sent via Deja.com http://www.deja.com/ >Before you buy. Cheers, Martin
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Compare FPGA features and resources
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