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Hi, guys. I hope you help me with this. I am trying to install Xilinx Foundation 2.1i on my PC, but a message wich stands it can not "inflate PCFJars" appears on the screen, and cancells the installation. I have a Pentium Celeron 333MHz w/ 64Mb RAM. So I tried to install it from the hard disk, but it didn´t help. Please, any help to jaac@pregrado.upb.edu.co Thanks in advance -- Please confirm recieving. Favor confirmar recibimento. Jaime Andrés Aranguren Cardona jaac@pregrado.upb.edu.coArticle: 20776
Has anyone used the Xilinx JTAG Programmer SW and the Parallel Cable III with Windows 2000? I have installed and used the Fndtn 2.1i tools under 2000, but I cannot get the JTAG Programmer to work properly.Article: 20777
As you correctly point out, using derived clocks on non-DLL parts (pre-Virtex) can be a headache. The traditional Xilinx approach which I was discussing involves running everything at the highest clock rate and distributing a global lower speed clock enable which just has to meet CE setup timing on the flops. The downside is the extra power dissipation from the high master clock rate and from the additional lower-speed clock net. regards, tom Rickman wrote: > <snipped> > > Maybe I am missing something. If you are generating a slower clock (40 > MHz) from a faster clock using a divide by 2 FF, then you will have skew > between your clock domains. Signals moving from the 40 MHz domain to the > 80 MHz domain will have a reduced setup time (by the amount of the > skew). This will not be easy to deal with since you are starting with > only 12.5 nS. > > But signals going from 80 MHz domain to the 40 MHz domain will have a > setup time based on the skew time, not the clock cycle time. The 40 MHz > clock edge is delayed from the 80 MHz clock edge. If you can't guaranty > that the minimum delay time for the signal is greater than the skew > time, which you can't, then you must use the skew time as your clock > cycle time for this signal! > > Am I missing something in the design? > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. Tom Burgess -- Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 20778
nestor@ece.concordia.ca wrote: > > Thanks Peter, Ray and Hal for your input. > > Since creating a completelly digital DPLL in an FPGA looks to be > quite difficult, what about creating a hybrid PLL where only the > voltage-controlled oscillator would be external (analog) and the rest > (phase detector, loop filter and divide-by-N) would be designed in the > FPGA? Yes, look at the data on 74HC4046/74VHC4046 ( Philips,TI,Mot,Fairchild etc ). This shows alternatives for Phase/freq detectors, the simplest is a XOR gate. You could even trail their VCO circuit on a FPGA :-). If you the multiplied freq is fixed, and known, then a LC/Varicap Diode VCO can work well. > In most previous cases I have seen, only the phase detector designed > digitally and the rest was still analog. I wouldn't mind building a > hybrid PLL solution as long as I could be guaranteed that clock > multiplication would be possible. Otherwise, I would have to resort > to a completely analog design... How much jitter / phase wobble can you tolerate on the multiplied clock ? Another multiplier alternative is a Rate Multiplier (CD4089, HEF4527 ) where you can select a % of clock pickets, from a stream. The gaps produce phase wobble, but in many apps, this is divided down and averaged to tolerablle levels. We also use the Rate Multiplier as a DAC. - jg -- ======= Manufacturers of Design Tools for uC and PLD ===== * IceP2051 - Full Speed ICE, for 1K,2K,4K 20 Pin FLASH controllers * OptoISP - Safe, fast In System Program of 89S, 90S, 17C devices => http://www.DesignTools.co.nz/winner51.htm for highlightsArticle: 20779
> More to the point: > For new designs, 5-V technology does not make any sense. 3.3-V devices are > faster, cheaper, bigger, consume less power, and have a much longer future. And > big devices use 2.5 and 1.8 V, with 1.5 and 1.3 V lurking around the corner. Yeah, but Peter, there are still 300 MILLION PCs out there that only supply 5V to the plug in boards... I know I can add a voltage regulator and other 'stuff' to make the majority of the board work at 3.3V, but sometimes, just a plain old 5V device makes life a LOT easier... --------------Article: 20780
> If I were interested in a 4KE for a new design, I'd go for the spartan. You > get the same function, better performance, and less power for a lower price. > You give up a few minor things that you probably wouldn't be using anyway: > async mode of the CLB RAM, wide edge decodes, some of the (the parallel ones) > configuration modes. Some of the device/package combinations are bitstream compatible between the 4ke and the Spartan ;-) -------------Article: 20781
In article <87v2b1$2ecj$1@noao.edu>, "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> wrote: (snip) > > The signals that go between the 80 and 40 MHz domains are simply flags that > get set or reset. These flags are used as clock enables (like, "turn > counter 3 on or off"). > Better late than never... Careful with the simple flags assumption. CE gets routed to ALL flops in the counter. If you have a timing violation on your flag when it changes state, then some flops might enable, and some might not. If this happens, then your counter output will be indeterminate, and potentially metastable. I have seen real and reproducible effects from this kind of failure mode, as well as failures caused by clocks not routed on global clock assets. (rant on) I make big bucks finding these kinds of problems for companies that can't figure out why their products went nuts when they plugged in a faster FPGA, or an FPGA from a different lot, or decided to test the product at something other than TA=25C. This stuff gets into production way too often, because engineers that don't understand FPGAs are reviewing designs of other engineers that don't understand FPGAs... Fortunately, you realized that there was a potential problem. I hate to say it, but I have been in companies with departments full of FPGA engineers, where no-one thought about clock distribution issues as much as you have. I have seen companies (yes, plural) that are shipping mission and safety critical products with incorrect FPGA clock implementation. They simply ignore the warnings from the Xilinx software, without giving it a second thought. Meanwhile, they are busy verifying, validating, and documenting their product software to the n'th degree. They aren't intentionally doing it wrong; I guess this is what happens when everyone focuses on procedures and stops paying attention to what is really happening around them. (rant off) Normally, we use one clock for the FPGA, and route slower frequency chip enables around to the flops. This can cause problems with routing resources, especially in older FPGAs. We have also implemented designs just the way you have now, but we treated all signals passing between clock domains as asynchronous, and used multi-stage registers to synchronous signals between domains. This works when you have more leftover flops available than routing resources. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20782
Ray Andraka wrote: > For all of you who have been asking, and those who wanted to know but > were afraid to ask, I have finally gotten a page explaining distributed > arithmetic up on my website. And for those who don't have a clue what > I'm talking about, distributed arithmetic is a hardware technique that > lets us hide lots of multipliers in an FPGA. Take a look and let me > know what y'all think. > http://users.ids.net/~randraka This is very nice Ray. It all makes good sense. In the "extreme" case that you mention however, I think a CSD multiplier would be better. It is very natural to want to play with #bits/cycle. But somewhere between the single bit serial approach and the full parallel approach, it seems like multipliers would start to win. CSD multipliers that is. GilArticle: 20783
Also take a look at: http://www.xilinx.com/xapp/xapp028.pdf jim granville <jim.granville@DesignTools.co.nz> wrote in message news:38B1D8C9.4891@DesignTools.co.nz... > nestor@ece.concordia.ca wrote: > > > > Thanks Peter, Ray and Hal for your input. > > > > Since creating a completelly digital DPLL in an FPGA looks to be > > quite difficult, what about creating a hybrid PLL where only the > > voltage-controlled oscillator would be external (analog) and the rest > > (phase detector, loop filter and divide-by-N) would be designed in the > > FPGA? > > Yes, look at the data on 74HC4046/74VHC4046 ( Philips,TI,Mot,Fairchild > etc ). > > This shows alternatives for Phase/freq detectors, the simplest is a XOR > gate. > You could even trail their VCO circuit on a FPGA :-). > > If you the multiplied freq is fixed, and known, then a LC/Varicap Diode > VCO > can work well. > > > > In most previous cases I have seen, only the phase detector designed > > digitally and the rest was still analog. I wouldn't mind building a > > hybrid PLL solution as long as I could be guaranteed that clock > > multiplication would be possible. Otherwise, I would have to resort > > to a completely analog design... > > How much jitter / phase wobble can you tolerate on the multiplied clock > ? > Another multiplier alternative is a Rate Multiplier (CD4089, HEF4527 ) > where you can select a % of clock pickets, from a stream. > The gaps produce phase wobble, but in many apps, this is divided down > and averaged to tolerablle levels. > > We also use the Rate Multiplier as a DAC. > > - jg > > > -- > ======= Manufacturers of Design Tools for uC and PLD ===== > * IceP2051 - Full Speed ICE, for 1K,2K,4K 20 Pin FLASH controllers > * OptoISP - Safe, fast In System Program of 89S, 90S, 17C devices > => http://www.DesignTools.co.nz/winner51.htm for highlights > >Article: 20784
In article <38A33051.7E751035@xilinx.com>, peter.alfke@xilinx.com wrote: > > > Tom Burgess wrote: > > > <snip>. This also applies to Peter's suggestion of distributing a 40 MHz CE, > > in which case you have to worry about meeting CE setup times back in the 80 MHz domain. > > It looks like derived clocks will be much easier to deal with in the Virtex/Spartan 2 family. > > > > I made the assumption that meeting the 80 MHz set-up time with a global net ( plus divider delay) > would be no problem. > One gets spoiled with the newer parts, like Virtex-E: > clock-to-Q = 1ns, Tilo = 0.5 ns, Tsu = 1 ns, > plus of course routing which is also very fast. > 100 MHz designs are not difficult anymore. > > And the DLL lets you divide the clock without intoducing any delay between the two clock domains. > Neat stuff ! > > Peter Alfke, Xilinx Applications I'm just about to migrate from flex10K to VIRTEX. Am I missing something here but if I set a global clock frequency of XMHz doesn't the tool make quite sure that the clock enables get where they need to in time. I'm not new to this game but you seem to giving this more thought than it needs, the whole design is now in one clock domain! Rob Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20785
jim granville wrote: > nestor@ece.concordia.ca wrote: > > > > Thanks Peter, Ray and Hal for your input. > > > > Since creating a completelly digital DPLL in an FPGA looks to be > > quite difficult, what about creating a hybrid PLL where only the > > voltage-controlled oscillator would be external (analog) and the rest > > (phase detector, loop filter and divide-by-N) would be designed in the > > FPGA? > > Yes, look at the data on 74HC4046/74VHC4046 ( Philips,TI,Mot,Fairchild > etc ). > > This shows alternatives for Phase/freq detectors, the simplest is a XOR > gate. > You could even trail their VCO circuit on a FPGA :-). DON'T DO THAT! Power supply noise will kill your attempts to get a good jitter. Instead use a LC vco (74HC04 gates will do) with a separate voltage regulator and even an additionnal RC decoupling (say 220uF, 100R) or a crystal vco (VCXO) if your reference frequency tolerances are tight. Forget the XOR gate, if the loop bandwidth is smaller than the vco control range it will NEVER lock alone. Instead use a phase / frequency comparator but not with a tristate output like on HC4046 you got a good AN there: <http://www.latticesemi.com/lit/docs/designexamples/cpld/an8017.pdf> Beware of fpga's 'high' logic levels on outputs. For phase comparators outputs you must pullup them or better, buffer them externally. With the preceding phase comp, you must use an differential op amp loop filter, it will give you common mode mode supply noise rejection, and good control on loop bandwidth / damping. > If you the multiplied freq is fixed, and known, then a LC/Varicap Diode > VCO > can work well. It works also with variable mult. frequ.!!! At last you should at last give your reference frequency stability and your precise requirements as to your multiplied frequency jitter. If you don't tell what you need nobody will give you useful answers. Pll design is not straigtfoward if you want performance. D.Article: 20786
Hello, I'm working on a vhdl design, synthesis is done hierarchical by Leo. spectrum, and I fit it in a virtex. I want to do advanced debug, and to vizualise signals deep in the hierarchy on external connectors. Now, I'm bringing each signal to the top level through all "layers". This is not an easy way, and modify all my design... I also tryed to directly insert some OUTBUF in the vhdl module (deep in hierarchy), but it does not seems to work. The last method is to use EPIC in M1.5 design manager. But all the modifications are lost for each new fit. Does someone have experience for resolving this problem simply? Regards, Frederic Cezilly, France.Article: 20787
Hi I have a question about how to send an integer from a counter in a CPLD (XC95144) to LabVIEW. Is it possible to convert an integer variable to a serial or parallell outport. Tankful for help. Björn Lindegren Sent via Deja.com http://www.deja.com/ Before you buy.Article: 20788
Hello,
I have to implement an ASP-like block on an ASIC in order to put many
chips on the same JTAG channel. I have asked Texas Instruments if they
sell the VHDL or Verilog code of this block but I have not received an
answer yet.
Can you point me to anyone who can provide me this IP core ?
Thank you very much for your help.
Regards,
Davide
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Davide Falchieri
Physics Department, Bologna University
40127,Viale Berti Pichat 6/2, Bologna(ITALY)
TEL:+39-051-2095077, FAX:+39-051-2095297
URL:http://sunvlsi4.bo.infn.it/~davide
mailto:davide.falchieri@bo.infn.it
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/
Article: 20789
Hello All !
It's what the subject says...
I am learning VHDL....
I need expample VHDL files for Xilinx Foundation 2.1i , some which are
working ....
The Synopsys VHDL synthesis tool often produces very strange error
messages...
All 'generic' samples I used were not able to be systhesized.
I was not able to create a simple 8 bit counter....
I take every good link to a website who you can give me !!!!
Here I have postet the source code with a remark on the line which seems not
to be ok.
I do not understand why.... It is taken out of some sample code and articles
in a electronic magazine...
Thank you for any help ot information.
*************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
ENTITY count1 is
PORT
(
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
qa : OUT STD_LOGIC_VECTOR (0 to 7)
);
END count1;
ARCHITECTURE Count1Arch of count1 is
BEGIN
VAR: PROCESS (clock)
VARIABLE count : INTEGER RANGE 0 TO 255;
BEGIN
IF (clock'EVENT AND clock = '1') THEN
IF enable = '1' THEN
count := count + 1;
END IF;
END IF;
qa <= CONV_STD_LOGIC_VECTOR(count,8); -- This line produces an error
message on synthesis
END PROCESS;
END Count1Arch;
*************
--
Holger Kleinert
Development / Support
IBP Instruments GmbH
Sutelstrasse 7a
D-30659 Hannover, Germany
http://www.ibpmt.com
Fon : +49-511-652286
Fax : +49-511-652283
Article: 20790
I have not run your code myself. But I think the problem is in variable,
which usually don't synthesize well.
I have rewritten your code. Give it a try.
(Note that the increment is on std_logic_vector + integer. I think one of
the library takes care of the
conversion so you don't need to worry about it.)
*************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
ENTITY count1 is
PORT
(
clock : IN STD_LOGIC;
enable : IN STD_LOGIC;
qa : OUT STD_LOGIC_VECTOR (7 downto 0)
);
END count1;
ARCHITECTURE Count1Arch of count1 is
SIGNAL CNT: std_logic_vector (7 downto 0);
BEGIN
process (clock, enable, CNT)
BEGIN
IF (clock'EVENT AND clock = '1') THEN
IF enable = '1' THEN
CNT <= CNT + 1;
END IF;
END IF;
qa <= CNT;
END PROCESS;
END Count1Arch;
Article: 20791Could someone post (or email me) the binaries that come with Xilinx In-System Programming Using an Embedded Microcontroller? For the past several days I've been trying to download them from ftp.xilinx.com without success. PC version is preferable but I will take Solaris or HP as well. Thank you, MichalArticle: 20792
Hi everybody, i want to load an ALTERA EPC2 configuration Eeperom from an embedded controller which has an RS232. I plan to use the free ALTERA Jam Player running on a PC. So i have to emulate the BitBlaster functionality in my controller firmware. Does anybody have information about the bitblaster (schematics !!! ...). Thanks for any help and excuse my english FabriceArticle: 20793
I have started a company to make several DSP boards and I am looking for a program to manage the parts procurement and tracking for manufacturing these boards. As it turns out, I am spending more time dealing with the management of the process than I am the engineering. A good MRP program would help me enormously. It would also be good if it included or interfaced to an accounting package. I have considered using Quick Books for accounting simply because that is recommended by my accountant. Anyone involved in the support of manufacturing that can offer some advice? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 20794
Try the IEC website: http://www.iec.ch/catlg-e.htm but the information is not free. * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 20795
Yes, you do reach break even point when you approach the full parallel case. Although, the routing may be a little easier for the distributed arithmetic version. You can also trim the widths of the adder trees if you group the coefficients by minimum number of bits required to represent them. CSD multipliers give you less flexibility if the coefficients are to be changed after the design is complete. The LUTs in the distributed arithmetic design can be easily reloaded to change the filter characteristic. Most of the applications discussed here (comp.dsp) can use a serial design. Current FPGAs support serial designs with bit rates between 150 and 200 MHz for 12 bit coefficients, so with 12 bit data you're good for a least 12 MHz sample rates. "Gilbert H. Herbeck" wrote: > Ray Andraka wrote: > > > For all of you who have been asking, and those who wanted to know but > > were afraid to ask, I have finally gotten a page explaining distributed > > arithmetic up on my website. And for those who don't have a clue what > > I'm talking about, distributed arithmetic is a hardware technique that > > lets us hide lots of multipliers in an FPGA. Take a look and let me > > know what y'all think. > > http://users.ids.net/~randraka > > This is very nice Ray. It all makes good sense. > In the "extreme" case that you mention however, > I think a CSD multiplier would be better. > > It is very natural to want to play with #bits/cycle. > But somewhere between the single bit serial > approach and the full parallel approach, it seems > like multipliers would start to win. CSD multipliers > that is. > > Gil -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 20796
Holger Kleinert wrote: > > ************* > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > use IEEE.STD_LOGIC_ARITH.all; > > ENTITY count1 is > PORT > ( > clock : IN STD_LOGIC; > enable : IN STD_LOGIC; > qa : OUT STD_LOGIC_VECTOR (0 to 7) > ); > END count1; > > ARCHITECTURE Count1Arch of count1 is > BEGIN > VAR: PROCESS (clock) > VARIABLE count : INTEGER RANGE 0 TO 255; > > BEGIN > IF (clock'EVENT AND clock = '1') THEN > IF enable = '1' THEN > count := count + 1; > END IF; > END IF; > qa <= CONV_STD_LOGIC_VECTOR(count,8); -- This line produces an error > message on synthesis > END PROCESS; > END Count1Arch; Question: What was the exact error? I'll bet that it couldn't find the proper function for CONV_STD_LOGIC_VECTOR. You have to convert your integer to a signed or an unsigned before converting to SLV. Comment #1: Using a variable for your counter is fine. Comment #2: FPGA Express v3.3 supports numeric_std so use that library, rather than the synopsys std_logic_arith/unsigned kludge. Comment #3: You'll want a reset for your flip flop. Simulating without a reset will always give you "unknown" for both count and qa. -andyArticle: 20797
S Lam wrote: > > I have not run your code myself. But I think the problem is in variable, > which usually don't synthesize well. In this case, they synthesize just fine.Article: 20798
All, I'm having a little luck creating a script file to apply test vectors to my design... I have something like: <snip> | Stimulators Assignment | | Select and/or define your own stimulators | and assign them to the selected signals clock SCLKNET 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 clock RX0CLKNET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 pattern RX0 < rx0.txt </snip> my pattern RX0 is assigned off of the SCLKNET clock however when I want it to be assigned off of the RX0CLKNET. In addition, for a timing simulation, I'd like RX0 to take it's value say 4 ns after rising edge on RX0CLKNET... Does anyone know how to do this? thx m Matt Billenstein REMOVE_THIS________mbillens@one.netArticle: 20799
Some documentation about printer port <-> PLD connect
Arnold
aaf <mindornf@online.no> wrote in message
NJDr4.2668$kz6.50251@news1.online.no...
>Hi everyone!
>
>Having the need to reprogram an old Lattice Ispl1016, and without the
>download cable at hand, I hope someone of you will help me to get around
the
>problem. My question is:
> a) Can I program a single device from the PC- printer port without using
>any kind of buffering?
>
>b) If so, Which pin of the LPT port is connected to what programming line?
>
>Thanks in advance
>Aage
>
>
begin 666 Lattice_download_cable.zip
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end
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