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where FlexGen is? thanks!Article: 29101
hello, Say a parrallel arithmetic. Is it possible to compute -A-B in one bank of slice. yes, i know, i can compute A+B, the transmit the sign (-) later for the subsequent operator. As i can compute A+B (one bank of Slice), and feed the result to 2's Complement Negator ( another bank of Slice). but i want to know, is it possible that the operation -(A+B) consumes the same number of slices as A+B ... any input for serial arithmetic will more than appreciated Regards --Erika Sent via Deja.com http://www.deja.com/Article: 29102
Hi, I'm after a second hand programmer for PAL/GAL 22V10 (CE) type devices. Anyone know where I might get one in the UK? Thanks Chris Anderson chris@anderson.u-net.comArticle: 29103
If the data is bit serial, this seems straightforward. Here's a design sketch. Ultimately your crossbar is just a vector of 30 30-1 multiplexers. In Virtex devices, for instance, a 32-1 mux is four 8-1 muxes feeding an 4-1 mux, requires about 4x4 + 1x2 LUTs plus some MUXFx's = about 4 1/2 CLBs per mux or ~140 CLBs total. Fits in an XC2S30. The mux control signals can easily be done by an addressable 5-bit register per mux (e.g. the control bus is 10 bits: a 5-bit address and a 5-bit input select per mux). Since your data rate is so low, you may be able to save logic by time multiplexing one or more muxes. For instance, for a 3 MHz data rate, if you can overclock the mux fabric 15-1, you can use just 2 30-1 muxes each feeding 15 output flip-flops. In which case, the mux selects are read out of 16x5-bit RAMs or SRLs adjacent to the muxes. That brings the area down to under 15 CLBs, a fraction of the '2S15. It's way overkill, but you may get some design ideas from the Xilinx App Note#240, "High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices", Vinta Singhai and Robert Le, http://www.xilinx.com/xapp/xapp240.pdf. Jan Gray, Gray Research LLCArticle: 29104
The 4000E is equivalent to the Spartan parts, which are really inexpensive. Trash the 4010 and use the XCS20 Spartan equivalent. ----- Original Message ----- From: "V R" <nospam@nonononononospam.com> Newsgroups: comp.arch.fpga Sent: Tuesday, February 06, 2001 12:44 PM Subject: Xilinx XC4010 > Hello. > > I have an FPGA board with an XC4010. The current tools (Foundation > 3.1/3.3) & VHDL/Verilog synthesizers (FPGA Xrp, Spectrum, etc) don't show > support for the XC4000 "plain vanilla" family of parts. > > I was however told that the 4000E uses the same bitstream as the 4000 so > one could "set up" the tools for an 4010E and use that bitstream to > configure the 4010, is this true? (I was told internally 4000E and 4000 > are the same). > > If not, is there anyone who wants to "trade" multiple 4010 and 4003A parts > for 4000E series? > > Thanks! > V.Article: 29105
Marc wrote: > I need to build a 'switching matrix'. (Please look at the > picture to understand the message ). I must be able to 'route' the > signal from port A to port X,Y or Z, and idem for B and C. If port X > is used, it quite understandable that i wont be able to 'route' an > other signal comming from port A.B or C there. The signal that i'll > use is PCM clocked at the speed of "from 64Khz to 3Mhz". Each > port has a TX and RX pin. > > Once a 'virtual' route is created, ( example, from port B to > port Z ) i must be able to create a other 'route' ( example, from > port A to port Y ) without creating a glitch or noise to the first one > already 'live'.For testing a 3x3 ports matrix is ok. but the next one > will be around 30x30 ports matrix. > > My question is, which device can be the best for this > kind of application, and , an idea how to build the concept of > a matrix like that. Please don't post binaries of your homework assignments in this newsgroup. Have a happy day. -aArticle: 29106
Brian, Oh, wait, now I remember. They were the 740 and the 780 series parts? Named after Volvos. Interesting. I still have a CD-ROM of the Motorola stuff around here somewhere. Unopened, of course. --a Brian Philofsky wrote: > > Intel did do Programmable Logic at one time as did AMD, Motorola and TI. Intel > did have the FLASHlogic line in the early 90's but sold the line to Altera > sometime in the mid-90's. Altera has since discontinued the line, > http://www.altera.com/html/products/flash.html > > -- Brian > > Andy Peters wrote: > > > Ed Ngai wrote: > > > > > > "Kevin J. McCann" wrote: > > > > I am an amateur circuit designer. It seems that the FPGA world may now be > > > > inexpensive enough for me to give it a try. Could you please recommend a > > > > book and board combo that would get me going. Although I have a good > > > > understanding of TTL style logic design, I have no experience with this > > > > more advanced stuff. > > > > Thanks, > > > > Kevin > > > > > > I've come across an older book "FPGA Workout, Beginning Exercises > > > w/ the Intel > > > FlexLogic FPGA", X Systems Engr. Software, 2608 Sweetgum dri., > > > Apex, N.C. 27502 > > > 1-800-549-XESS. I've heard they have a 2nd ed of this book ? > > > > Intel does FPGAs?Article: 29107
Yes. You need just one extra LUT.
-A = (not A)+1
therefore
-A-B = (-A) + (-B) = (not A) + (not B) + 2;
So, you need to handle the first two bits seperately. With three luts
you can determine sum(0), sum(1) and carry(1). Carry(1) is then fed
into a (n-2)-bit adder with inverted inputs.
CU,
Kolja
In article <95p5al$74q$1@nnrp1.deja.com>,
erika_uk@my-deja.com wrote:
> hello,
>
> Say a parrallel arithmetic.
> Is it possible to compute -A-B in one bank of slice.
> yes, i know, i can compute A+B, the transmit the sign (-) later for
the
> subsequent operator. As i can compute A+B (one bank of Slice), and
feed
> the result to 2's Complement Negator ( another bank of Slice).
>
> but i want to know, is it possible that the operation -(A+B) consumes
> the same number of slices as A+B ...
>
> any input for serial arithmetic will more than appreciated
>
> Regards
>
> --Erika
>
> Sent via Deja.com
> http://www.deja.com/
>
Sent via Deja.com
http://www.deja.com/
Article: 29108I believe the 4000E's are a superset of the functions of the 4000 series, with a method to either expand a 4000 configuration to fit their device (and thus not use the features specific to the 4000E), or perhaps there are configuration settings that are illegal/unused in the 4000 that represent these additional resources in the 4000E series. Thus, you can use a 4000 bitstream in a 4000E, but I believe it is very unlikely you can use a 4000E bitstream in a 4000. Scott In article <95ork3$6qo$1@news.utdallas.edu>, V R <nospam@nonononononospam.com> wrote: >Hello. > >I have an FPGA board with an XC4010. The current tools (Foundation >3.1/3.3) & VHDL/Verilog synthesizers (FPGA Xrp, Spectrum, etc) don't show >support for the XC4000 "plain vanilla" family of parts. > >I was however told that the 4000E uses the same bitstream as the 4000 so >one could "set up" the tools for an 4010E and use that bitstream to >configure the 4010, is this true? (I was told internally 4000E and 4000 >are the same). > >If not, is there anyone who wants to "trade" multiple 4010 and 4003A parts >for 4000E series? > >Thanks! >V.Article: 29109
I noticed some other job postings in this group with needs for FPGA engineers, so I thought I might post some applicable needs...but if this is not wanted or wrong, I apologize, and please let me know. I am an internal recruiter with Ericsson in Raleigh (RTP), North Carolina, and have been tasked in finding digital/hardware design engineers. This position is responsible for the analysis, design and integration of digital baseband hardware for cellular base station products and systems. Senior positions will be responsible for specification, design, construction, test and documentation of TDMA cellular base station equipment. Create subassembly requirement specifications from higher-level system requirements. Design and implement new base station configurations, including functionality, cabling, arrangement, and physical prototype construction. Test the configurations for compliance with RF, electrical, and functional specifications. Document designs and assist factory introduction. These individuals would be working with our research and development facility in Raleigh, NC, specifically in our DWOS (wireless office) and Base Station development groups. These are intermediate to senior positions, and 2-7 years experience is required. Experience with product and subsystem development. Experience with the analysis, design, and development of digital and mixed signal circuitry. Experience with FPGA, ASIC, logic design and telecom/datacom knowledge. Work with Mentor Graphics tools is preferred. Proficient with the use of logic analyzers, oscilloscopes is a must. Any help that you can give me, in either locating qualified individuals for the roles, or potential places to look, would be most appreciated. Additionally, I would welcome an opportunity to speak with you directly if you are interested yourself. Thank you very much and Best Regards, -- Mike DeCellis Ericsson Recruiter RTP, NC (Raleigh-Durham) Phone: 919-472-6541 Fax: 919-472-6510 Mobile: 919-522-2815 mike.decellis@ericsson.com Sent via Deja.com http://www.deja.com/Article: 29110
This is a multi-part message in MIME format. --------------1063928F65A48100F8EADDE2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You can use an equivelent size 4000 bitstream safely in a 4000E however the opposite is not necessarily true. See http://support.xilinx.com/techdocs/1661.htm The reason for this is the 4000E is a superset of the features of the 4000 device. Dual-Port, synchrounous RAM and CE in the IOBs are a couple of changes that come to mind with the 4000E series however there may be a few others. If the bitstream enables any of these "new" features, there is no telling what might happen in the older 4000 device that does not have these features and certaintly the design will not behave as expected since those features don't exist in the silicon. If I remember right, the 4000A is a completely different animal in terms of routing so the bitstreams are not remotely compatible. My first suggest would be to purchase some Spartan (plain Spartan, not-XL, not-II) and plug those in. As long as you get the same package (PC84 most likely) they should be footprint and pinout compatible although you could only configure it serially which is most likely not a problem for you. Spartan parts are generally cheaper than 4000Es and you can target them with the current software, thus the suggestion. 4000Es will work as well though. If you do attempt to use these older devices, I either suggest getting your hands on the older software (safest) or use the newer sofftware but be sure not to use any of the features supported in 4000E that are not availible in the 4000 devices. There is no guraentees that using a bitstream targeted to a 4000 will work but if this is for a hobby application and not a critical and/or production system, I see no harm in trying. You will not be able to do any timing analysis though so use good synchronous design practices and use a slow clock to be safe. In other words, I would not push the silicon too hard. Good luck, -- Brian V R wrote: > Hello. > > I have an FPGA board with an XC4010. The current tools (Foundation > 3.1/3.3) & VHDL/Verilog synthesizers (FPGA Xrp, Spectrum, etc) don't show > support for the XC4000 "plain vanilla" family of parts. > > I was however told that the 4000E uses the same bitstream as the 4000 so > one could "set up" the tools for an 4010E and use that bitstream to > configure the 4010, is this true? (I was told internally 4000E and 4000 > are the same). > > If not, is there anyone who wants to "trade" multiple 4010 and 4003A parts > for 4000E series? > > Thanks! > V. --------------1063928F65A48100F8EADDE2 Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian tel;work:1-800-255-7778 x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx, Inc.;Software Marketing adr:;;2300 55th Street;Boulder;CO;80301;USA version:2.1 email;internet:brianp@xilinx.com title:Sr. Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------1063928F65A48100F8EADDE2--Article: 29111
Correct. If you prefer it from the horse's mouth, here is the 1999 data book, page 6-7 ( hard to believe that this is just 2 years, seems like looong ago!) "Any XC4000E device is pin-out and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program the XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device." Peter Alfke, Xilinx Applications ================================== Scott Hauck wrote: > I believe the 4000E's are a superset of the functions of the 4000 series, with > a method to either expand a 4000 configuration to fit their device (and thus > not use the features specific to the 4000E), or perhaps there are > configuration settings that are illegal/unused in the 4000 that represent > these additional resources in the 4000E series. > > Thus, you can use a 4000 bitstream in a 4000E, but I believe it is very > unlikely you can use a 4000E bitstream in a 4000. > > Scott > > In article <95ork3$6qo$1@news.utdallas.edu>, V R <nospam@nonononononospam.com> > wrote: > >Hello. > > > >I have an FPGA board with an XC4010. The current tools (Foundation > >3.1/3.3) & VHDL/Verilog synthesizers (FPGA Xrp, Spectrum, etc) don't show > >support for the XC4000 "plain vanilla" family of parts. > > > >I was however told that the 4000E uses the same bitstream as the 4000 so > >one could "set up" the tools for an 4010E and use that bitstream to > >configure the 4010, is this true? (I was told internally 4000E and 4000 > >are the same). > > > >If not, is there anyone who wants to "trade" multiple 4010 and 4003A parts > >for 4000E series? > > > >Thanks! > >V.Article: 29112
JianYong Niu schrieb: > > I am trying to implement a simple design. An error report is as below: > > ERROR:Pack:198 - NCD was not produced. All logic was removed from design. > This is usually due to having no input or output PAD connections in the > design and > no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' > attributes to the design, or run 'map -u' to disable logic trimming in > the > mapper. > Problem encountered generating the NCD. > > I have assigned all the pins in the design entry. what is wrong? ;-))) The GATE-EATER got you. This happens when you have some internal signals that are not used in your design. The logic/Flip-Flops generating this signal will be removed. Now, there are some new unused signals, that will be removed too and so on. So check you design for missing/wrong signal assignments. -- MFG FalkArticle: 29113
I am working with Handelc,too. do you have the manual from celoxica? if not, I can mail it to you. "Eric Jeandeau" <ejeandeau@mpc-data.co.uk> wrote in message news:004701c08f90$2512b720$3e5c96c0@mpcdata.co.uk... > Hi all, > > I am working on a project to port an C-ANSI program to Handel C > target XILINX 4000E series. > If you have any information about Handel-C such as tutorial, > guideline,etc..., let me know ! > > Cheers > > ejeandeau@mpc-data.co.uk > > > > > -- > Posted from anchor-post-34.mail.demon.net [194.217.242.92] > via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29114
Dont hate, man, love. There are good bits and bad bits to every country. Whatever you decide, make sure that the salary will give you the lifestyle you expect, with some on top for incidentals that _will_crop up. Don't believe those bullshit cost of living comparison web sites. Do what I did and actually figure out what your take-home will be in a different country. Then check how much housing etc. will cost. Me? I'm leaving the UK for Portland (in Oregon USA). My Visa came through this week. Woohoo! Just one thing on the US though, I would not move to California for anything (well almost). Whatever you get offered in "The Valley", it will probably not be enough unless you already live there and bought your house 5+ years ago. Cheers Stuart On Mon, 05 Feb 2001 16:24:32 GMT, frouatbi@my-deja.com wrote: > > >I will tell you a philosofical dilemna, I'm an FPGA designer in Canada >which is a descent peacefull, country. > >Why would I go to France I'm Tunisian, I do have and in your face >a deep hate for this country. Athough I like the francophone >culture, I have a deep hate/liking of this country culture. > > >The United States, with the bloody george bush, and the people of >the gulf war. > > >I better stick in here in Montreal, and complain about the weather, >It's better than France Racism, or USA war on the arabs. > >Sorry but you have to consider the human side along with the technical >stuff, > >Yours Truly > >Fredj Le magnifique > > >Sent via Deja.com >http://www.deja.com/ For Email remove "NOSPAM" from the addressArticle: 29115
Trying to find a real-time embedded MPEG1 video encoder for a fairly low-volume application (500-1000 units per year). The only MPEG1-only IC vendor I found was Zapex, but our volumes are too low for them. There are several broadcast-type MPEG2 codec vendors (C-Cube, VisionTech, IBM, NEL) that support MPEG1, but again our volume is too low. Have also looked at Philips TriMedia chip. They have an MPEG1 encoder library module but it only supports I and P frames (we need to support B frames). Any pointers to other options, either dedicated IC, FPGA-based IP core, or DSP-based software encoder, would be very much appreciated. The requirements are: - real time - MPEG1 elementary stream output - IPB encoding - SIF and QSIF resolution - 200kbps - 2Mbps output bitrate Thanks, RobertArticle: 29116
Hi Kevin, There are good lists of FPGA boards at both http://www.optimagic.com/boards.html http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protobo ards_page At Burch Electronic Designs, we sell the BED-SPARTAN2+ kit. This will probably be of interest to you. See http://www.burched.com.au/ Features include: - 200,000 gates! - free Xilinx Webpack software CD included - introductory price US$120! We also have a very basic "jumpstart guide" for this kit, downloadable from our website at http://www.burched.com.au/downloads.html It is a quick guide to creating and compiling a new project with the Xilinx WebPACK ISE design software. You may also wish to check out the Plug-On modules. (SRAM, FPGA-CPU-IO, 7SEG-DISPLAYS, DIPSWITCH). http://www.burched.com.au/products.html International orders are very welcome. Best regards Tony Burch www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits! "Kevin J. McCann" <KevinMcCann@Home.com> wrote in message news:sORe6.63183$B6.16603004@news1.rdc1.md.home.com... > I am an amateur circuit designer. It seems that the FPGA world may now be > inexpensive enough for me to give it a try. Could you please recommend a > book and board combo that would get me going. Although I have a good > understanding of TTL style logic design, I have no experience with this > more advanced stuff. > > Thanks, > > Kevin > >Article: 29117
Robert Sefton wrote: > Any pointers to other options, either dedicated IC, FPGA-based IP core, or > DSP-based software encoder, would be very much appreciated. > > The requirements are: > > - real time > - MPEG1 elementary stream output > - IPB encoding > - SIF and QSIF resolution > - 200kbps - 2Mbps output bitrate http://www.mpeg.org has a fairly extensive list of companies that have MPEG products. -- Matthew Donadio (donadio@worldmulti.com) World MultiCom www.worldmulti.comArticle: 29118
Hi. > I am looking to start coding fpga's but have a little trouble getting the > first very basic info. Maybe have a look at http://www.optimagic.com/index.shtml and possibly start under the "Device Summary" button. There's alot of good basic info there. There are alot of great sites on the web. To list only a small subset, perhaps you could look at: Ray Andraka's http://www.fpga-guru.com Dave Van den Bout's http://www.xess.com/ And, maybe not so much for a beginner, but I'd like to add Jan Gray's http://www.fpgacpu.org/ dealing with implementing CPUs on an FPGA. I also have an "FPGA? What's That?" document on my website, but this is really only intended to explain that question to non-tech people. http://www.burched.com.au/what.html Perhaps the faqs for comp.lang.vhdl and comp.lang.verilog may be of interest to you also (search on the web for those). > Such as how many gates on a chip is many, which starterkits would be > recomendable, what the potential of fpga is... such as how fast they will > actually function ect ect. In terms of starter kits, there are good lists of FPGA boards at both http://www.optimagic.com/boards.html http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=protoboards_protobo ards_page *My company tiny ad here :)... At Burch Electronic Designs, we sell the BED-SPARTAN2+ kit. See http://www.burched.com.au/ And we also have a very basic "jumpstart guide" for this kit http://www.burched.com.au/downloads.html > Is there a faq for this group coving some of this? > I believe you haven't had a quick response on this group with a link to the "official faq", because it is either now out-of-date and not maintained, or now doesn't exist. Anyone else know that link? Hope this helps. Best regards Tony Burch www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits!Article: 29119
IF you don't know how to awnser, don't wasted our bandwidth with your stupidity. Im technician for 10 years in fiber optical networks, not a student. >Please don't post binaries of your homework assignments in this >newsgroup. > >Have a happy day. > >-aArticle: 29120
Check the Xilinx Xperts web page for resources.Article: 29121
Hello Jan, Thanks for your help, it will give me a very good idea how to design it. Regards, Marc. On Tue, 06 Feb 2001 16:16:34 GMT, "Jan Gray" <jsgray@acm.org> wrote: >If the data is bit serial, this seems straightforward. Here's a design >sketch. > >Ultimately your crossbar is just a vector of 30 30-1 multiplexers. In >Virtex devices, for instance, a 32-1 mux is four 8-1 muxes feeding an 4-1 >mux, requires about 4x4 + 1x2 LUTs plus some MUXFx's = about 4 1/2 CLBs per >mux or ~140 CLBs total. Fits in an XC2S30. The mux control signals can >easily be done by an addressable 5-bit register per mux (e.g. the control >bus is 10 bits: a 5-bit address and a 5-bit input select per mux). > >Since your data rate is so low, you may be able to save logic by time >multiplexing one or more muxes. For instance, for a 3 MHz data rate, if you >can overclock the mux fabric 15-1, you can use just 2 30-1 muxes each >feeding 15 output flip-flops. In which case, the mux selects are read out >of 16x5-bit RAMs or SRLs adjacent to the muxes. That brings the area down >to under 15 CLBs, a fraction of the '2S15. > >It's way overkill, but you may get some design ideas from the Xilinx App >Note#240, "High-Speed Buffered Crossbar Switch Design Using Virtex-EM >Devices", Vinta Singhai and Robert Le, >http://www.xilinx.com/xapp/xapp240.pdf. > >Jan Gray, Gray Research LLC > >Article: 29122
Marc, you should be ashamed of yourself for this response. Your question was not well formulated ( were you talking about many ports or wide ports ?), and the idea of doing this in a CPLD is so incredibly naive that one automatically suspects an ineperienced student. Especially when you are hiding behind an anonymous e-mail address. So, behave yourself next time. Peter Alfke ======================== Marc wrote: > IF you don't know how to awnser, don't wasted our bandwidth > with your stupidity. Im technician for 10 years in fiber optical > networks, not a student. > > >Please don't post binaries of your homework assignments in this > >newsgroup. > > > >Have a happy day. > > > >-aArticle: 29123
Thanks but.. Perhaps I wasn't clear. I have already looked at the manuals. What I want to know is how to specify the 'net_name' that is used everywhere when the net is not at the root of the hierarchy. eg for the example is the net name "av_testmod_clk2" ? or "testmod_clk2" neither of these work. I've tried many different permutations. I can get the net name to work when the net is at the root of the hierarchy, but I haven't found any examples where the net is within another net. Do I have to somehow specify the net name in the source code ? How do I do this? I'm using Verilog. "Utku Ozcan" <ozcan@netas.com.tr> wrote in message news:3A7E4C12.2BD9B1CE@netas.com.tr... > Rob Finch wrote: > > > duh, how do I specify a timing constraint on a module port for a module > > instantiated inside another one. > > > > eg > > module av(clk, ....) > > ... other stuff > > my_mod testmod(clk2, ....) > > > > endmodule > > > > I want to set a period constraint on clk2. > > I am using Xilinx F1.5 student edition software > > > > Thanks > > Rob > > Look at the TNM, TNM_NET, TIMEGRP and TIMESPEC > commands used in UCF described thoroughly in > http://support.xilinx.com. In this page, go to library, and > go to M2.1i manuals. In the front page of the M2.1i manuals, > you will find M1.5i manuals. These manuals are the best > for you. Xilinx has placed the link in such a deep place. > > Utku > >Article: 29124
Sorry if my question wasn't well formulated, english is not my first language, but if you look at the pic, you can easily understand that it is a 'many ports' matrix. I don't have experience with 'programmable logic', but it's not a reason to throw in the air " don't post your homework.. bla bla " Im a technician in fiber optic, not it 'PLD'. About the anonymous e-mail ; i always use this email when i post in newsgroup, sorry but i receive too much junk. But for all who have awnser me , i give my real address so we can keep in touch with a "real email". Regards, Marc. On Tue, 06 Feb 2001 16:01:21 -0800, Peter Alfke <peter.alfke@xilinx.com> wrote: >Marc, >you should be ashamed of yourself for this response. >Your question was not well formulated ( were you talking about many ports or >wide ports ?), and the idea of doing this in a CPLD is so incredibly naive that >one automatically suspects an ineperienced student. >Especially when you are hiding behind an anonymous e-mail address. >So, behave yourself next time. > >Peter Alfke >======================== >Marc wrote: > >> IF you don't know how to awnser, don't wasted our bandwidth >> with your stupidity. Im technician for 10 years in fiber optical >> networks, not a student. >> >> >Please don't post binaries of your homework assignments in this >> >newsgroup. >> > >> >Have a happy day. >> > >> >-a
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