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Brant Soudan wrote in message <3B02C14A.EE905873@xilinx.com>... >andrew, > >the first thing to check is your memory usage. i see you only mentioned >available memory on the HP Vectra. and that was only 0.5 GB. increasing this >could be an easy way to reduce compile times on all machines. > >in my experience, the 2 things that affect compile times the most are memory and >CPU speed. Nope. Compile time can be improved by moving to Synplicity. Or maybe Exemplar. You can also use incremental compiles; the Xilinx tools will tie the EDIFs together. P&R time can be improved by floorplanning. Even minimal floorplanning will pay off big time. This gives a much bigger effect than a few tens of percentage processor boost.Article: 31276
--------------171C410C898C6E24A2509B46 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I was promised that sesigns with 0 inputs and 2 outputs fit into Xilinx CPLDs after installing this service pack. But this bugifx is not in the list. ;-( Kolja Sulimma Roy White wrote: > Hello Xilinx Software users, > > Service Pack 8 is now available for all Platforms. To keep you > software up to date with the latest features I encourage you to visit > our service pack download center > at support.xilinx.com. > > Thank you for designing with Xilinx! > > Roy White > --------------171C410C898C6E24A2509B46 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> I was promised that sesigns with 0 inputs and 2 outputs fit into Xilinx CPLDs after installing this service pack. <br>But this bugifx is not in the list. <p>;-( <p>Kolja Sulimma <p>Roy White wrote: <blockquote TYPE=CITE>Hello Xilinx Software users, <p>Service Pack 8 is now available for all Platforms. To keep you software up to date with the latest features I encourage you to visit our service pack download center <br>at <a href="http://support.xilinx.com/support/techsup/sw_updates/">support.xilinx.com</a>. <p>Thank you for designing with Xilinx! <p>Roy White <br> </blockquote> </html> --------------171C410C898C6E24A2509B46--Article: 31277
> >Now, I know Insight-Electronics (www.insight-electronics.com) offers a > >PCI base-connector board for their Spartan2-150 PCI evalualtion kit. > >The base-connector board converts the PCI 32-bit edge-connector into a > >bunch of standard pin headers, which are very easy to work with. > >(Naturally, the base-board doesn't generate any PCI signals of its own, > > and I'm sure it adds a lot of unwanted delay to the I/O paths.) > >This could be a good way to get generic test-points through the > >PCI-interface, for only $100. > > actually we ended up using the same trick. We plugged in a pci > backplane and hooked up logic analyzer probes on it. Nice! So I wasn't the only one who struggled with the proprietary I/O connectors. I keep thinking I was a lesser engineer, because I didn't know how to solder/procure my own cable. Where do you get PCI backplanes? The Xess XSV boards have two 50-pin headers. They're the same form-factor as an old SCSI internal cable. I bought a pair of SCSI cables ($5 each), then used standard 22-gauge copper wire (single strand) to connect individual I/Os between the SCSI-cable and a Radio-Shack experimenter breadboard. This was fine for my low-speed ( <8MHz ) application.Article: 31278
> You seem to be arguing against code reuse? If there's a perfectly good > free core already available, why should someone write a new one? This > doesn't sound like "very bad news" to me. Writing your own code is the best way to learn the design intimately. Of course, it never hurts to have independent verification of your work! I learn a lot by designing something on my own, then comparing my work with someone else's work. I have to admit sometimes I end up getting depressed at 'how much I don't know.' sigh... For example, I spent an afternoon writing a 'clever' Verilog RTL barrel shifter. Little did I realize, that every Designware Foundation library shipped with Synopsys already generates a better structure than what I came up with. But it was a good educational experience in working around limitations of Verilog syntax. (What idiot decided NOT to allow wire bus arrays? And why can't I directly bit-select on a register-array? grrrr...) > If you're suggesting that having free cores for CRC generators is bad > for that reason, I think you're facing an uphill battle. Sure, students > like to get out of doing work. But so do engineers. > > Instructors need to give homework assignments whose results can be > distinguished from publicly available code. For instance, the famous > traffic light and vending machine problems. These work well as homework > assignments precisely because in the real world no one designs either in > HDL; they are both microprocessor based. > > Have you seen the responses in this newsgroup or in comp.lang.vhdl when > students ask for traffic light or vending machine code? It can be quite > entertaining. You mean like what is the terminal velocity of a swift in diving? 'African or European?'Article: 31279
For arithmetic intensive applications, the Actel architecture pales in comparison to Xilinx and Altera. Fast arithmetic in the latter two can make use of optimized carry chains with the result that simple ripple carry arithmetic is usually the fastest way to do arithmetic. Actel has no dedicated carry chains, so fast arithmetic has to be constructed using more expensive fast arithmetic structures. It can be done, but it is more of a pain, and uses much more real estate per function. Xilinx also has the advantage of being able to use the CLBs as small RAMs or shift registers. This usually permits a very significant compaction of the frequent small delay queues encountered in DSP functions such as filters. You also lose the advantage offered by reconfiguration for system test and debug. Reconfigurable logic essentially lets you separate board level debug from FPGA debug, and also lets you get more flexibility in function. Chris Eilbeck wrote: > > Has anyone used both? I'm used to the Xilinx toolchain and devices > but a client wants a project done using Actel antifuse. Are there any > objective comparisons anywhere on the web or does anyone have any > opinions as to how hard it would be to make the change? > > Ta > > Chris > -- > Chris Eilbeck mailto:chris@yordas.demon.co.uk > MARS Flight Crew http://www.mars.org.uk/ > UKRA #1108 Level 1 BSMR -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 31280
I am very much interested in Digital PLL (DPLL) design. By DPLLs I meant the ones used in UARTS for clock/data recovery by oversampling. This is done using a local clock whose frequency is 4/8/16/32 times higher then the frequency of the received data. At the transmitter side, data is appropriately encoded (NRZI etc.) to introduce sufficient transitions in the received data stream. I intend to implement the DPLL as a State Machine /Look up table using Verilog. Thus the DPLL would be a purely digital method of clock and data recovery. Could you suggest any reference books/links, give me any tips to get me started? Waiting in anticipation, Regards, Amey HegdeArticle: 31281
Hi,
Actualy i need the specifications of PowerPC 860 CHASSIS
specifications., I searched the internet for this but i got specifications of 750, but i didnt get any specifications related to 860 CHASSIS SPECIFICATIONS.,it shows only the archetectural overview of it, no focussed clearly on chassis 860., so please
anyone knows helpme out..
with thanks and regards.,
jawahar ali.
Article: 31282xapp#059 says an n input LUT has n/4 times the functionality of a 4 input LUT . Going by the definition of functionality , we can't arrive at this figure certainly. So how did we arrive at this figure?? ThanksArticle: 31283
Guys,
Thanks for the ideas. I ran some performance monitoring on the box, and the
par process uses 99% of CPU, there is no disk swapping at all with 512MB
main memory (RAMBUS), so the bottleneck doesn't seem to be lack of memory. I
guess a P4 aware version of the software might help or multi processor
support, but that's not there yet. Here is some details from the test
compile that was run. I'm not a XILINX user but I did an electronics degree
so I know roughly what it means :)
Cheers
Andrew
Design 1
Xilinx Mapping Report File for Design 'ra1next'
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Design Information
------------------
Command Line : map -p xcv1000-4-bg560 -o map.ncd ra1next.ngd ra1next.pcf
Target Device : xv1000
Target Package : bg560
Target Speed : -4
Mapper Version : virtex -- D.24
Mapped Date : Mon May 14 16:53:14 2001
Design Summary
--------------
Number of errors: 0
Number of warnings: 172
Number of Slices: 8,323 out of 12,288 67%
Number of Slices containing
unrelated logic: 0 out of 8,323 0%
Number of Slice Flip Flops: 7,075 out of 24,576 28%
Total Number 4 input LUTs: 8,161 out of 24,576 33%
Number used as LUTs: 8,143
Number used as 16x1 RAMs: 18
Number of bonded IOBs: 347 out of 404 85%
Number of Tbufs: 446 out of 12,544 3%
Number of Block RAMs: 21 out of 32 65%
Number of GCLKs: 3 out of 4 75%
Number of GCLKIOBs: 3 out of 4 75%
Number of RPM macros: 448
Total equivalent gate count for design: 462,269
Additional JTAG gate count for IOBs: 16,800
Design 2
Xilinx Mapping Report File for Design 'ra2sim'
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.
Design Information
------------------
Command Line : map -p xcv1600e-6-bg560 -o map.ncd ra2sim.ngd ra2sim.pcf
Target Device : xv1600e
Target Package : bg560
Target Speed : -6
Mapper Version : virtexe -- D.26
Mapped Date : Tue May 01 16:05:48 2001
Design Summary
--------------
Number of errors: 0
Number of warnings: 849
Number of Slices: 14,085 out of 15,552 90%
Number of Slices containing
unrelated logic: 0 out of 14,085 0%
Number of Slice Flip Flops: 10,668 out of 31,104 34%
Number of 4 input LUTs: 14,930 out of 31,104 48%
Number of bonded IOBs: 286 out of 404 70%
Number of Block RAMs: 26 out of 144 18%
Number of GCLKs: 1 out of 4 25%
Number of GCLKIOBs: 1 out of 4 25%
Number of RPM macros: 1,403
Total equivalent gate count for design: 623,415
Additional JTAG gate count for IOBs: 13,776
"Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
news:3B02DF24.16D7E014@algor.co.uk...
>
>
> Andrew Webb wrote:
> >
> > Dear All,
> >
> > I have been asked by the FPGA developers at my company to recommend a
> > suitable platform and configuration to minimise the time they have to
spend
> > waiting for XILINX compilations. They currently have to wait around 8
hours.
> > We tried a P4 with RAMBUS memory, but the performance increase over a P3
> > wasn't that great. Any ideas ... my boss gave me this brief.
> >
> > Thanks,
> >
> > Andrew Webb
> > Thales Defence
> >
> > ......
> > Our Software
> > Xilinx Foundation 3.1I with SP7
> >
> > Devices
> > Devices are xcv1000, xcv1600e-6
> >
> >
>
> <snip>
>
> > Part 2
> > We have since been steered towards the AMD processors, which we are
testing
> > today.
> >
>
> I can give you one data point here. Changing from a PIII-600-PC100 to an
> Athlon-1G3-DDR266 has speeded up PAR by 52% and post-synth/post-PAR
> simulations by ~45% [ModelSim-PE].
>
> The designs aren't as big as yours but that's more a question of memory
> size. If you are using WinNT/Win2K then the main rule is: Never, ever,
> ever, let it start swapping. If you do the performance plummets to i286
> levels - if you're lucky.
>
>
>
> > Our Aim
Article: 31284Dave, What kind of Virtual Machines are you going to implement? Java? we have an FPGA board available for prototyping, and next come out with an add-on board with SRAM and flash. We use a JEMcore java processor which runs on the FPGA. Check out our site, we will have a new product anouncement in 1/2 weeks, with the sram/flash boards, and will setup a kit which can be bought that includes both the FPGA board as well as the sram board. The sram board also has an ethernet interface on board which can be used from the fpga. Richard Dave Feustel wrote: > I am a longtime system sw programmer with some hardware experience and > an armchair background in computer architecture suddenly very interested > in FPGAs. I would like to program a couple of virtual machines (implemented > in C) into FPGAs on a commercially produced FPGA development board and > then play with those VMs under Windows 2000. I've pretty much settled on > Xilinx parts and Verilog as the implementation language but I have no FPGA hw/sw > tools yet. What is the best way to get started along this path? > > Thanks, > > Dave Feustel -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 31285
Synplify v6.2 gives warnings for ports of instantiated black-box in a VHDL code: @W:<filename>:10:8:10:16:Input clock is unused The point is that the code to be instantiated in VHDL is actually Verilog but I have created VHDL code with an empty ARCHITECTURE, like Verilog-style black-box module. I also used ATTRIBUTE syn_black_box OF <module> : COMPONENT IS TRUE; ...inside VHDL top-level. What do you recommend when I want to instantiate a Verilog module in VHDL module? Is it not the only way to synthesize Verilog module and create a VHDL black-box "wrapper" to "cheat" the Synplify? Synplify still gives warnings that black-box pins are unused. Environment is Sun Solaris 2.6, Synplify v6.2, target is Xilinx XCV2000E. Synplify support is in USA, I'm in Europe, so I don't think I'll get support until next day, therefore I am asking the question to you. UtkuArticle: 31286
I'm using the XCR3256XL from the Coolrunner XPLA3 family. One of the
features of this family is that it should be 100% routable. I'm using
WebPack Project Navigator with the WebPack XPLA fitter to implement my
design. In order to test parts of my design I have defined an array of
8, 8 bit wide standard logic vectors to act as memory locations. When I
try to implement this design I get the messages below.
Parsing...
Parsing file test_epp_int.blx ...
Synthesizing and Optimizing...
Fitting...
> WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> Cannot preassign signals.
> ERROR 4060 Cannot fit the design into the chip. You may want to try
a larger device or split the design into sub-designs.
%% ERROR count: 1 WARNING count: 3
By setting the Use Design Location Constraints option to "try" the
implementation process will complete successfully but is unable to
assign the above signals to the required pins, it generates the resource
summery below.
$DEVICES XCR3256XL-10TQ144 fit (9 sec)
---------------------------------------------------
| Total Device Resource Summary |
---------------------------------------------------
| RESOURCE AVAIL. USED UTILIZATION |
---------------------------------------------------
| Clock Inputs 4 1 25.00% |
| Global C-Terms 4 3 75.00% |
| Func Blocks 16 10 62.50% |
| I/O Pins 116 29 25.00% |
| Macro Cells 256 139 54.30% |
| PLA P-Terms 768 322 41.93% |
| PLA S-Terms 256 137 53.52% |
| Block C-Terms 128 14 10.94% |
| Fbk Nands 0 0 0.00% |
---------------------------------------------------
If I halve the size of my 'memory' array it passes through the
implementation process successfully, I assume this means that the fitter
tool is unable to utilise the 100% routable feature of the taget.
My question is, can I get around this? I have tried fiddling with the
process options for systhesis and implementation but have had no luck.
Alan
Article: 31287Hi Stan, Nallatech do a DIME module called the Bally1553 that has the 1553 interface chip from DDC as well as a VirtexE FPGA. http://www.nallatech.com/products/dime_professional/bally1553/index.htm Lisa Warren Nallatech -----Original Message----- From: Stan Ramsden [mailto:stan.ramsden@avnet.com] Posted At: 09 May 2001 22:58 Posted To: fpga Conversation: Xilinx : 1553 interface Subject: Xilinx : 1553 interface Has anyone done a 1553 serial bus interface that they would like to share?? Thanks, Stan RamsdenArticle: 31288
www.thevoter.co.uk ttnfcqmxljkclfrispuzspxmyzrqlbjokkzqefiupmgcevbgbhuzujxcrouwcdeehofefegryfouyArticle: 31289
I'm doing currently something similar as my final project for university. It's 270Mbps asynchronous 8B/10B encoded serial stream receiver, in Virtex 2 FPGA. xapp224.pdf from Xilinx site could be useful for you, the only thing is that I'm afraid in case of some jitter in incoming signal it actually doesn't work. But I still used the main idea from it. I myself couldn't think of any way to actually restore the clock of incoming signal in purely digital design, the idea in xapp224 is to extract the data from incoming signal but subsequent processing of it is done using internal clock of receiver, meaning not the exact clock of incoming signal but slightly higher clock frequency. I bit different idea I had was to make several copies of input signal each with a bit different delay (different delays could be created with routing on PCB) and then by monitoring signal fronts on each input to determine the input with most suitable delay for reading data bits in. I was planning to implement a receiver like this in Virtex E, using 135MHz clock for receiving 270Mbps serial stream. However this design came out so complicated that it was quite difficult to get it run at 135MHz in Virtex E. So, I moved on to Virtex2 and used the idea in xapp224. In my design(and in xapp224) the problem is that I can't use much higher frequency than of the incoming signal, FPGA just can't stand frequencies much higher than 270MHz, if you can use frequencies multiple times higher than input signal it's probably a lot easier. My english isn't very good and I don't know if you understood my explanations above but I hope it helps, Meelis "amey hegde" <amey@controlnet.co.in> wrote in message news:9dvknd$a8n0$1@ID-89792.news.dfncis.de... > I am very much interested in Digital PLL (DPLL) design. ...Article: 31290
Hi,
for an asynchronous data stream, oversampling at a factor of 4 or even 8
is probably not enough. If you look at any data-sheets, such as the
Infineon C166 Architecture, you will usually find that the over-sample
rate for an asynchronous interface is usually 16. The best value to
chose is dependent on your frame size. The idea is that you start
sampling in the middle of a bit-window and the oversampling should be
high enough so that the sample time is still within the bit-window at
the end of the frame, allowing for clock drift between the nominal
interface speed and your internal clock speed. You can of course
re-adjust at each edge in the data stream. Many telco applications
actually use an oversample rate of 40 or more.
An example (in VHDL) of serial channels (rcv/xmit) suitable for a UART
can be found at our page =
http://www.eda-services.de/SiSoCKit/index.html
The steps involved are:
1) Synchronise the incoming signal
2) Take three consecutive synchronised samples and do a two-out-of-three
election to determine stable value (glitch suppression)
3) When the start condition is recognised (e.g. falling edge for UART
interface) start your deframer-FSM. =
Hope this helps.
=
Best regards,
Mit freundlichen Gr=FC=DFen,
Charles Gardiner
-------------------------------------------------------------
Charles Gardiner, B.E.
Program Manager, Silicon IP
Siemens AG
Dept: I&S IT PS 8 Mch
Otto-Hahn-Ring 6
D-81730 Muenchen
Email: mailto:charles.gardiner@mchr2.siemens.de
Phone: Office +49 89/636 42969, Mobile (0)171/867 2732
Fax : Office +49 89/636 44595
Homepage : http://eda-services.atd.siemens.de/gardiner
(Siemens Intranet only)
I&S Homepage: http://www.atd.siemens.de/it-dl/eda
Siemens I&S - Munich's ARM approved Design Centre
Article: 31291Dave, For a low cost (< US$120) FPGA board with a 200K gate ( ! ) Xilinx Spartan II device, you may wish to consider the B3-SPARTAN2+ board from Burch Electronic Designs. http://www.burched.com.au/bedspartan2.html We also have various plug-on modules that you can use to expand the board with resources such as SRAM, PC-connectors, 7 segment displays, dip-switches, etc. Importantly, it works with the free Xilinx WebPACK software (Verilog and VHDL entry supported), which you can download from the Xilinx website. Best regards Tony Burch http://www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits! "Dave Feustel" <dfeustel@mindspring.com> wrote in message news:9dm31v$vek$1@nntp9.atl.mindspring.net... > I am a longtime system sw programmer with some hardware experience and > an armchair background in computer architecture suddenly very interested > in FPGAs. I would like to program a couple of virtual machines (implemented > in C) into FPGAs on a commercially produced FPGA development board and > then play with those VMs under Windows 2000. I've pretty much settled on > Xilinx parts and Verilog as the implementation language but I have no FPGA hw/sw > tools yet. What is the best way to get started along this path? > > Thanks, > > Dave Feustel > > > >Article: 31292
"Keith R. Williams" wrote: > > On Wed, 16 May 2001 18:33:03 +0200, Falk Brunner <Falk.Brunner@gmx.de> > wrote: > > >Iwo Mergler schrieb: > >> > > > >> IIRC, the tracks on your card should be routed above a continuos > >> power plane and must be shorter than 1 inch. The PCI clock signal > >> must be 1.5 inches long. All signals drive exactly one CMOS input. > >> I might be completely wrong. > > > >I think so. I dont have the PCI spec (and never read them :-( but Iam > >sure that this wont work. It is called PCI-BUS, so one signal cant drive > >only 1 input. Also, the distance between the PCI slots in my PC is > >greater than 1 inch. > > I think he meant the on-card stub. Anyway, I happen to be debugging a > PCI board right now (hangs the system on boot - hate that!) and have > open my copy of _PCI_System_Architecture_ (MindShare). According to > Shanley and Anderson: > > Maximum Card Trace Lengths: > > - All signals on the 32bit portion of the bus must be no longer than > 1.5". > > - All 64-bit extension signals must be no more than 2". > > - PCI CLK signal trace length must be 2.5" +/- .1" (hmm) and connected > to only one load. > > ---- > Keith OK, got the specs back, sorry about the misinformation. Motherboard: The general gist is do what you want, as long as you meet the timing specs with all sockets putting 10pf load on the lines: at 33MHz: max allowed clock skew 2 ns, pin-to-pin between any two components, not sockets max. allowed round trip delay (one reflection) for any signal 10ns You are allowed to lower the clock frequency if you want. Expansion board: See Keith's post for trace lengths, disregard my previous one. :^) You are not allowed to have more than one input (max 10pf) on any signal, the impedance of your traces should be 60-100 Ohm and the trace velocity is supposed to be 150-190 ps/inch. Regards, IwoArticle: 31293
This isn't a FPGA specific issue, but there seems to be lots of PCI and Compact PCI experience in this group, so I thought I'd post the question: Are clamp diodes to 3.3V needed for reliable Compact PCI operation? If the PCI chip does not have internal clamp diodes, should I add external clamp diodes? Can anyone recommend clamp diodes (or a diode array) that wouldn't add much capacitance? A little background: I'm looking at using the Cypress CY7C09449PV PCI controller in a Compact PCI, 33MHZ, 3.3V, 32-bit, 3.3V design. It looks like a nice part, but it does not have the 3.3V clamp required by PCI Spec 2.2. The Cypress part can handle a 7V input level so the peak level of the incident wave shouldn't damage the part, but I'm concerned about the negative reflected wave possible dipping below the upper end of the input threshold causing spurious transitions. I can see how a clamp diode would dampen the overshoot, which would reduce the ringing. I've noticed that other PCI controllers (such as V3 Semi's V320USC) don't have the upper clamp diode either. What's the deal? Thank you, GeraldArticle: 31294
This is a multi-part message in MIME format. --------------F7DE1A28B3B061289CC033F9 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <br>One thing I would also point out is that the devices don't appear to be that full. 3.1i will try a lot harder that 2.1i used to by default with timing constraints. When it is running PAR, take a look at the *.itr file and it will tell you by how much the timing constraints are missing by. If they are missing by a large margin then this means that the design needs modifying, with either the synthesis tools' attributes (for fanout) or re-architecting the design. <p>Also never run Delay or Cost based cleanup with Virtex designs - it takes too long, and gives little or no improvement. <p>I have a number of designs running in full V1000's/2000's in under 5 hours (with timing constraints set to ~90MHz plus in the -6) - machine is Twin 850 P3 with 1GB RDRAM. <p>Dave <p>Rick Filipkiewicz wrote: <blockquote TYPE=CITE>Andrew Webb wrote: <br>> <br>> Dear All, <br>> <br>> I have been asked by the FPGA developers at my company to recommend a <br>> suitable platform and configuration to minimise the time they have to spend <br>> waiting for XILINX compilations. They currently have to wait around 8 hours. <br>> We tried a P4 with RAMBUS memory, but the performance increase over a P3 <br>> wasn't that great. Any ideas ... my boss gave me this brief. <br>> <br>> Thanks, <br>> <br>> Andrew Webb <br>> Thales Defence <br>> <br>> ...... <br>> Our Software <br>> Xilinx Foundation 3.1I with SP7 <br>> <br>> Devices <br>> Devices are xcv1000, xcv1600e-6 <br>> <br>> <p><snip> <p>> Part 2 <br>> We have since been steered towards the AMD processors, which we are testing <br>> today. <br>> <p>I can give you one data point here. Changing from a PIII-600-PC100 to an <br>Athlon-1G3-DDR266 has speeded up PAR by 52% and post-synth/post-PAR <br>simulations by ~45% [ModelSim-PE]. <p>The designs aren't as big as yours but that's more a question of memory <br>size. If you are using WinNT/Win2K then the main rule is: Never, ever, <br>ever, let it start swapping. If you do the performance plummets to i286 <br>levels - if you're lucky. <p>> Our Aim</blockquote> </html> --------------F7DE1A28B3B061289CC033F9 Content-Type: text/x-vcard; charset=us-ascii; name="dhawke.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for David Hawke Content-Disposition: attachment; filename="dhawke.vcf" begin:vcard n:Hawke;David Hawke tel;cell:(+44) 778 875 5002 tel;work:(+44) 870 7350 517 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx"> version:2.1 email;internet:dhawke@xilinx.com title:XILINX Field Applications Engineer adr;quoted-printable:;;Xilinx Northern Europe=0D=0ABenchmark House;203 Brooklands road;Weybridge;; x-mozilla-cpt:;2672 fn:David Hawke end:vcard --------------F7DE1A28B3B061289CC033F9--Article: 31295
Hello Alan,
Since I do not have your design file, I cannot tell you exactly why your design
is not fitting.
But, by looking at the fitter report you attached, it seems as though you are
using a decent amount of P-terms and registers. I would guess that your design
is not fitting because of fan-in limitations. A certain node/equation probably
requires a bunch of P-terms. However, we can tweak this --
By default , the WebPack software does not allow the user to utilize all
available resources. This gives the designer some fan-in to spare, should he
need it later. i.e. It allows the designer to add more logic late in the game
without going having to go to a higher density part.
With that said, I would suggest that you try changing your design implementation
options to:
Collapsing Pterm Limit = 16 (default 28)
Collapsing Input Limit = 16 (default 32)
Block Input Limit = 38 (default 36)
(Just in case, you can acces these options by right clicking on Implmentation,
then left clicking on Properties. Then go to the Optimization tab.)
Try those options, and let me know how they work. If it still doesn't work, I
would be happy to look into it further.
Regards,
Mark
Alan Glynne Jones wrote:
> I'm using the XCR3256XL from the Coolrunner XPLA3 family. One of the
> features of this family is that it should be 100% routable. I'm using
> WebPack Project Navigator with the WebPack XPLA fitter to implement my
> design. In order to test parts of my design I have defined an array of
> 8, 8 bit wide standard logic vectors to act as memory locations. When I
> try to implement this design I get the messages below.
>
> Parsing...
>
> Parsing file test_epp_int.blx ...
>
> Synthesizing and Optimizing...
>
> Fitting...
> > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > WARNING 6342 Cannot assign signal 'led4' to pin/node '140=FB9_15'.
> > Cannot preassign signals.
> > ERROR 4060 Cannot fit the design into the chip. You may want to try
> a larger device or split the design into sub-designs.
>
> %% ERROR count: 1 WARNING count: 3
>
> By setting the Use Design Location Constraints option to "try" the
> implementation process will complete successfully but is unable to
> assign the above signals to the required pins, it generates the resource
> summery below.
>
> $DEVICES XCR3256XL-10TQ144 fit (9 sec)
>
> ---------------------------------------------------
> | Total Device Resource Summary |
> ---------------------------------------------------
> | RESOURCE AVAIL. USED UTILIZATION |
> ---------------------------------------------------
> | Clock Inputs 4 1 25.00% |
> | Global C-Terms 4 3 75.00% |
> | Func Blocks 16 10 62.50% |
> | I/O Pins 116 29 25.00% |
> | Macro Cells 256 139 54.30% |
> | PLA P-Terms 768 322 41.93% |
> | PLA S-Terms 256 137 53.52% |
> | Block C-Terms 128 14 10.94% |
> | Fbk Nands 0 0 0.00% |
> ---------------------------------------------------
>
> If I halve the size of my 'memory' array it passes through the
> implementation process successfully, I assume this means that the fitter
> tool is unable to utilise the 100% routable feature of the taget.
>
> My question is, can I get around this? I have tried fiddling with the
> process options for systhesis and implementation but have had no luck.
>
> Alan
Article: 31296--------------35B9F1207DFF326C832996EC Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit If you are looking for answers to technical questions, here are three existing resources that might help you: http://www.xilinx.com/support/sitemap.htm shows you, on one page, all the technical support files available from Xilinx. http://xup.msu.edu/ brings you the Xilinx University Support at Michigan State University Try them, they are helpful and friendly. http://www.fpga-faq.com/archives/index.html puts the complete (!) archives of this newsgroup at your fingertips. You can even scroll up and down three different ways: chronologically, inside the thread, or for a specific author. Philip Freidin collected the >30,000 entries and sponsors the website, while (I think) Jan Gray provided the smart archive engine. Big thanks to both of them, and enjoy plowing through those musty and juicy archives... Peter Alfke --------------35B9F1207DFF326C832996EC Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> If you are looking for answers to technical questions, here are three existing resources that might help you: <p><u><A HREF="http://www.xilinx.com/support/sitemap.htm">http://www.xilinx.com/support/sitemap.htm</A></u> <br>shows you, on one page, all the technical support files available from Xilinx. <p><u><A HREF="http://xup.msu.edu/">http://xup.msu.edu/</A></u> <br>brings you the Xilinx University Support at Michigan State University <br>Try them, they are helpful and friendly.<u></u> <p><u><A HREF="http://www.fpga-faq.com/archives/index.html">http://www.fpga-faq.com/archives/index.html</A></u> <br>puts the complete (!) archives of this newsgroup at your fingertips. <br>You can even scroll up and down three different ways: <br>chronologically, inside the thread, or for a specific author. <br>Philip Freidin collected the >30,000 entries and sponsors the website, while (I think) Jan Gray provided the smart archive engine. Big thanks to both of them, and enjoy plowing through those musty and juicy archives... <p>Peter Alfke <p> </html> --------------35B9F1207DFF326C832996EC--Article: 31297
Alan- Has anyone from Xilinx apps contacted you about this? Or have you tried to contact our apps (support.xilinx.com)? If not, forward the design to me and I'll get someone to take a look at it. Thanks, -Dennis McCrohan, Xilinx CPLD S/W Alan Glynne Jones wrote: > The problem that is making my life a misery at the moment is an application > error message generated by Windows NT. > ----------------------------------------------------------------------------------------------------------------------------- > xplaopt.exe - Application error > > The instruction at "0x004fbe7c" referenced memory at "0x00000010". The memory > could not be "read" > > Click on OK to terminate the application > Click on CANCEL to debug the application > ----------------------------------------------------------------------------------------------------------------------------- > After closing this window, another comes, > ----------------------------------------------------------------------------------------------------------------------------- > Dr Watson for Windows NT > > An application error has occurred > and an application error log is being generated. > > xplaopt.exe > Exception: access violation (0xc0000005), Address: 0x004fbe7c > ----------------------------------------------------------------------------------------------------------------------------- > > I was basically trying to synthesise and implement a smallish design using the > WebPack VHDL project Navigator, this error came up intermittently to begin with > but now occurs every time. I can still successfully synthesise and implement > other code. I have tried fiddling with the process options, I have tried > deleting and re-installing the WebPack software, this had no effect. I have now > had a new HDD image installed to start from scratch and installed the WebPack > design entry and WebPack XPLA fitter once more and I get the same problem when > attempting to implement my VHDL code. > > This problem does not occur when the same files are implemented on a colleagues > machine, it successfully completes the process generating a file for the device > programmer. My collegue uses a custom installation of NT. > I have 128MB RAM, 10GB HDD, Intel 730MHz running NT version 4 (build 1381: > service pack 6) > > It looks like there is some basic incompatibility problem between NT and the > WebPack application. Have you come across this problem before? Can anybody > help? > > regards, > > Alan > > PS I have attached the VHDL code I have been trying to synthesise. Don't see any attachement...Article: 31298
I'm also having problems with FPGA express & One hot state machines. This
is what I've found:
The finite state machine itself is synthesized correctly using dual process
method or single process method (ie. both sythesize with one register per
state). However, if you use the state signal outside of the FSM process,
FPGA express uses all the registers in the FSM to determine if it is in
that state. The proper way is to only compare one state register.
In the example below, a 5 state FSM is created. Synthesize it with FPGA
Express 3.5 and you will see (in the schematic viewer) all 5 registers used
to determine if fsm_state = fsm_2_state (whereas only one register should
have been used). This causes extra delay to occur. A workaround is to
assign the signals within the FSM case statement. However, I don't like
this coding style so I'm not gonna use it. (BTW, Altera MaxPlusII
synthesizes the code using a single state register compare).
So what's the scoop? Is there a bug in FPGA Express???
Tom Kaminski
Norsat International Inc.
Winnipeg, Manitoba. Canada.
--**********************************************
Here is my sample VHDL code:
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fsm1 is
port(
clk : in std_logic;
reset : in std_logic;
some_output : out std_logic;
some_input : in std_logic;
another_input : in std_logic
);
end fsm1;
architecture rtl of fsm1 is
type fsm_state_type is
(
fsm_idle_state,
fsm_1_state,
fsm_2_state,
fsm_3_state,
fsm_4_state
);
signal fsm_state : fsm_state_type;
begin
-- All 5 registers are used to determine fsm_state = fsm_2_state
-- This Adds lots of delay!!! Bug in FPGA EXPRESS????
some_output <= '1' when fsm_state = fsm_2_state and
( some_input = '1' or another_input = '1')
else '0';
fsm_fsm: process( reset, clk )
begin
if reset = '1' then
fsm_state <= fsm_idle_state;
elsif rising_edge( clk ) then
case fsm_state is
when fsm_idle_state =>
fsm_state <= fsm_1_state;
when fsm_1_state =>
fsm_state <= fsm_2_state;
when fsm_2_state =>
fsm_state <= fsm_3_state;
when fsm_3_state =>
fsm_state <= fsm_4_state;
when fsm_4_state =>
fsm_state <= fsm_1_state;
when others =>
fsm_state <= fsm_idle_state;
end case;
end if;
end process;
end rtl;
kahhean@bigfoot.com wrote in <9b1e11$reo$1@news.netmar.com>:
>
>Hi all,
>
>Recently, I had problems with DLL locking. After upgrading to Service
>Pack 7, and FPGA Express (3.5.0.6013), the DLLs are locking fine.
>
>However, the very same vhdl code that used to be synthesized to be under
>8 ns, is now 18ns component delay alone.
>
>After checking in Timing Analysis, I observed that FE seems to be giving
>me rubbish. I have a 38-state state machine. I specified one-hot
>encoding. The result is that I get 38 flip flops for the state machine
>(which looks like one-hot), but I also get each state talking to every
>other state. Since each of my state transits to only a few other
>states, FE must be giving me rubbish. Anyway, the very same vhdl code
>synthesized well using FGPA Express 3.4.
>
>Does anybody have the same experience too?
>
>Thanks in advance.
>
>TA TA
>kahhean
>
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Article: 31299bhupesh wrote: > > Hi I am trying to build a functionality around xc9500xv family of CPLDs. It requires interfacing the CPLD to keyboard and seven segment displays. If anyone has a prior experience interfacing a keyboard and/or seven segment display to this family of CPLDs, I am looking forward to your advice Thanking you in anticipation bhupesh bhupeshr@softhome.net We've done plenty of Keypad/Display work in CPLD, but on the ATFXXX'L' series, not the XC devices. The Atmel 'L' devices have much lower power, so you have more power budget for LED drive, or for smaller/cheaper system power chain. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nz
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