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I've a little bit of confusion on my mind, hope you could help to clear something to me, this is the problem : I've 3 block each large 512x12 bits (... in each of it are stored some polyphase sum for a different interpolation rate) , depending on the rate selected I need to connect only one of this to the rest of the circuit but for this operation is not required an high speed. I've some idea : 1) Arrange each block in a different BlockRAM initialized using CORE GENERATOR and then switch between them with a case 2) Only one RAM not initialized and three constant depending on the rate I load the ram with the values stored in three different ROM or defined with a constant (I don't know if it is the same). 3) Arrange each block in a ROM using the case construct which is recognized by XST and mapped on a ROM, by the way which is the speedest, blockRAM or this kind of ROM ?? For the selection of the ROM depending on the rate I could use the CASE again. 4) Use a constant which I think produde a big multiplexer 5) your suggestion I'm interested in speed, hope to reach at least 165MHz on VirtexE 600 -6 , so this is the key of lecture of this post Thanks Antonio

> > I'm starting a new design in which I'm using a multi-channel A/D with a low > > sampling-rate and Flash memory for the storage and the system is going to be > > powered by battery. In this stage, I'm not yet sure if using a FPGA would be > > wise, as I'm very concerned with the power consumption. The gate count of You need to tighter specify what your requirements How much data? How often do you want to store it. Resolution/speed of A/D. An FPGA does not have an ADC internally, so you need to add power for that. The Atmel AVR will draw less power than the Atmel 8051. I'd try out with an ATmega8, which has internal R/C oscillator and power down mode. -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.

I've got a cut down PCI design which works nicely in a MAX7256SQC208-7. I have changed device to a FLEX10KA30-1 to port it to CardBus. What I do not understand is why the simulation shows that the design on the FLEX10K part has delays of about twice that of the 7256, even though the flex part is a -1, and the max is a -7? Thus the timing becomes marginal to say the least, yet the datasheet claims PCI 33MHz compliance. Any ideas? -- Chris Cowdery e-mail c.cowdery@nxtsound.TAKE-THIS-BIT-OUT.com

First of all, thanks for the ideas. As to the connection of the buses to the same row/column, I'm afraid that will be difficult. We're using the 208-pin PQFP package (EP1K100QC208-3) and there are maximally only 4 (2) pins that share the same row (column). (e.g. pins 147, 144, 143, 142 on row B, unless I am misreading the information), so I would follow the advice of Martin, suggesting I should go for routability. I'll keep you posted on the outcome of that. Second point, concerning the idea of Kevin Brace: I must say our experience with Xilinx FPGA's (XC4000 family) is not that good. We've been using it in a students' lab and they had lots of problems with the software (crashes, wrong output that required awkward workarounds), and we did not have any problems using the free Max+2. We program mostly in VHDL and the Leonardo compiler is functionally good although it's Windows interface _badly_ needs a good Windows programmer. Furthermore: we do not need the ultimate speed ! We use the FPGA in motor control applications to generate tens of 20-100 kHz high resolution (12-16 bit) PWM signals, decode quadrature encoder signals and acquire current waveforms from serial ADC's. These measurements must be checked for interferences and overloads and the innermost high bandwidth control loop, implemented on the FPGA, is based on them. The actual system control is very complex and performed with a powerful DSP. Modern DSP's however, depend heaviy on their pipeline architecture and we noticed that the best way to kill their computing power is to have them interrupted a few 10k times per second to write PWM update values and read currents. (This I/O actually burdened our researchers/programmers too...) It seemed to us that we would need a lot of 'random' logic. The quick compile/fit times with Leonardo/Max+2 and the immediate availability of the device made us decide for the ACEX 1K. And while we were at it, we went for the largest device we could get our hands on. BTW, we paid about $30 for the EP1K100-3 (next day delivery) and for us (university reasearch) time to market and the lowest price are not (ahem...) very important. Jeroen. "heyho" <nospam@heyho.com> wrote in message news:ee746ec.2@WebX.sUN8CHnE... > Hi, > > both, Max+plus 2 as well as Quartus 2 provide you with a lot of information which is not shown in any datasheet. If you´re using Max+2 just go to the "Online Help" and the search for the string "pins". Then you will find all the relevant information on which pins are conneceted to which row or which column. If your´re going for spped it is importnat that you will do the pin assignments based on that information. For example, the 32bit bus or the 16bit bus should be assigned to the pins which are connected to the SAME row or SAME column. > > BTW, Kevin, why should he use Spartan II´s? ACEX devices are great! This should be a newsgroup which discusses technical questions and not stupid stuff what device is a few cents cheaper than another one. This kind of information hich cannot be proven anyway!!

My discrete math is rusty, but I would think that the possible number of _distinct_ r-bit functions in an n-bit lookup table would be f(n, r) = C(n, r) - C(n - 1, r). The total number of functions would then be sum[r = 1..15] f(16,r), which is 26333. Plus I guess 2 for all-0's and all-1's. Jim "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:a34r8f$1557bo$1@ID-84877.news.dfncis.de... > I think Peter triggerd some inner gost of mine. > I want to compute the EXACT number of unique functions possible with a 4 > input LUT. > First start, lets have a look at the 2 input LUT. > Lets call the inputs A and B and the result R, so the truth table looks like > this. > (Use a fixed font) > > B A R > 0 0 R0 > 0 1 R1 > 1 0 R2 > 1 1 R3 > > For two inputs, there is only one permutation. If we change A with B > (or verca vice ;-) we get the following table with the same logic function. > > A B R > 0 0 R0 > 0 1 R2 > 1 0 R1 > 1 1 R3 > > Now we write down all possible 16 combinations for R0..R3 and compare them > to their > permutation. If the are identical, the code is a unique function. > If they differ, we found a permutation function. > > Example 1 > > R permutated > R0 0 0 > R1 0 0 > R2 0 0 > R3 1 1 > > They are identical, so code 1000 is a unique function. > > Example 2 > > R permutated > R0 0 0 > R1 1 0 > R2 0 1 > R3 0 0 > > They are different, so its a permutation function. > Now here the complete list for a 2 input LUT > > U . . . . . . . means unique function > PxA, PxB . . . means Permutation number X, part A / B > > > R3 R2 R1 R0 Type general function name > 0 0 0 0 U LOW > 0 0 0 1 U A NOR B > 0 0 1 0 P1A A AND NOT B > 0 0 1 1 P2A NOT B > 0 1 0 0 P1B B AND NOT A > 0 1 0 1 P2B NOT A > 0 1 1 0 U A XOR B > 0 1 1 1 U A NAND B > 1 0 0 0 U A AND B > 1 0 0 1 U A XNOR B > 1 0 1 0 P3A A > 1 0 1 1 P4A A OR NOT B > 1 1 0 0 P3B B > 1 1 0 1 P4B B OR not A > 1 1 1 0 U A OR B > 1 1 1 1 U HIGH > > So we see, a 2 input LUT has > > 2 fixed codes (LOW / HIGH) > 6 unique functions > 4 permutations of 2 codes > ------------------------------ > 16 functions overall > > OK, this was the first part. Now I will make a small programm to calculate > all permutation > of the 4 inputs of a 4 input LUT (which are 4! = 24), compare them all and > write down a statistic. > Stay tuned folks, I'll be back. > > -- > MfG > Falk > > > >

Peter, Your response is probably what I would have done, but I wanted some verification that I hadn't missed a better solution. Your timely and accurate response is one of the reasons why I personally rate Xilinx so high. (The product quality doesn't hurt either.) It is so rare that a "little guy" can get a response from someone at your level. BTW, thanks to all the others who hang out on this newsgroup and provide such timely and accurate responses. I hope you know who you are. Thanks, Theron Peter Alfke wrote: > The worst thing you might build would be a synchronous counter with the clock > enable fed to every bit in parallel. Don't do that! > > My sugestion is to build any counter you want, synchronous or ripple, but have > a one-bit prescaler toggle-flip-flop generate the clock. This prescaler must > use the Xilinx CE feature, which really is a multiplexer in the D input. > Since CE changes asynchronously, but does not affect the clock, you never get > a runt clock pulse, but you might ( once in a blue moon) get a longer Q > delay. It will be many thousands (millions?) of years between the worst > happening, when this extra metastable delay swallows one incoming clock tick. > > Peter Alfke, Xilinx Applications > ================================== > Theron Hicks wrote: > > > I am looking for some code to define a glitch less clock enable/disable > > circuit. The clock frequency is 100MHz. What I am trying to say is that I > > have a counter with a 100MHz clock and I want to avoid runt pulses on the > > clock. This could either be a clock mux switching between 0 and clock on > > the output or a "safe" clock enable that would eliminate (or at least > > minimize) the possibility of metastability. The counter could be > > asynchronous if that simplifies things. Any ideas, suggestions, sources, > > etc. > > > > Thanks, > > Theron

David Miller wrote: > > I am looking for some code to define a glitch less clock > > enable/disable circuit. The clock frequency is 100MHz. What I am > > trying to say is that I have a counter with a 100MHz clock and I > > want to avoid runt pulses on the clock. This could either be a > > clock mux switching between 0 and clock on the output or a "safe" > > clock enable that would eliminate (or at least minimize) the > > possibility of metastability. The counter could be asynchronous if > > that simplifies things. Any ideas, suggestions, sources, > > SpartanIIs have dedicated clock enable inputs on all flops. You should > use those rather than gating clocks (which is very bad practice anyway) > with logic[1]. Consult your synthesis guide for more info on how to do > that in your HDL. > > Judging from your email address, I assume that you're a student. Reasonable assumption, but actually I am working on a R & D project for a university development of an instrumentation project. I am working on a graduate level degree (MSEE) on a part time basis, but my primary function is as an engineer not a student. Maybe I should get a different non-university E-Mail so people won't automatically assume that my questions are trying to get homework answers. However, your idea of "playing" with the CLBs still has a great deal of merit, and I have used it to study DCMs, DLLs, and SRL16s with substantial benefit. Actually, I had thought I would probably use the CE input, but I just wanted to verify that I had not missed some type of clock gate circuit such as exists on the VirtexII series. Thanks for your help and advice, Theron Hicks > An > interesting exercise is to run the tool fpga_editor, create an empty, > small fpga and play with the CLBs. You can learn alot about how the > fpgas actually implement logic in this way. > > [1] PAR will complain loudly if you do this, because you are no longer > able to use dedicated clock routing resources so, glitches aside, you'll > have big problems with skew. > > -- > David Miller, BCMS (Hons) | When something disturbs you, it isn't the > Endace Measurement Systems | thing that disturbs you; rather, it is > Mobile: +64-21-704-djm | your judgement of it, and you have the > Fax: +64-21-304-djm | power to change that. -- Marcus Aurelius

First of all, thank you all for your answers and help. "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message news:CYu58.6963$O5.17299@nntpserver.swip.net... > > > I'm starting a new design in which I'm using a multi-channel A/D with a > low > > > sampling-rate and Flash memory for the storage and the system is going > to be > > > powered by battery. In this stage, I'm not yet sure if using a FPGA > would be > > > wise, as I'm very concerned with the power consumption. The gate count > of > > You need to tighter specify what your requirements > How much data? I'm going to use 4 channels of A/D at 200Hz, but only to store 3 of them (one is used to monitor the battery). Data is stored on a Flash, MultiMedia Card (i.e. SPI interface...) with 64+Mbytes. That means the the system should be able to function over 15 hours by using a small Litium-Ion battery. > How often do you want to store it. Interface to the MultiMedia card is packet based, so data is going to be soted in packets of 512 bytes.... > Resolution/speed of A/D. 12 bit A/D with 200Hz sampling rate. > An FPGA does not have an ADC internally, so you need to add power for that. > > The Atmel AVR will draw less power than the Atmel 8051. > I'd try out with an ATmega8, which has internal R/C oscillator and power > down mode. > -- > Best Regards > Ulf at atmel dot com > These comments are intended to be my own opinion and they > may, or may not be shared by my employer, Atmel Sweden. > Btw Ulf, What's your idea about MSP430 series suggested by Jim Granville? Best Regards Arash

oooops! so sorry, Actully it was Rickman who suggested MSP430, not Jim Granville.. "Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:3c56c266$1@epflnews.epfl.ch... > First of all, thank you all for your answers and help. > > > "Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message > news:CYu58.6963$O5.17299@nntpserver.swip.net... > > > > I'm starting a new design in which I'm using a multi-channel A/D with > a > > low > > > > sampling-rate and Flash memory for the storage and the system is going > > to be > > > > powered by battery. In this stage, I'm not yet sure if using a FPGA > > would be > > > > wise, as I'm very concerned with the power consumption. The gate count > > of > > > > You need to tighter specify what your requirements > > How much data? > I'm going to use 4 channels of A/D at 200Hz, but only to store 3 of them > (one is used to monitor the battery). Data is stored on a Flash, MultiMedia > Card (i.e. SPI interface...) with 64+Mbytes. That means the the system > should be able to function over 15 hours by using a small Litium-Ion > battery. > > > How often do you want to store it. > Interface to the MultiMedia card is packet based, so data is going to be > soted in packets of 512 bytes.... > > > Resolution/speed of A/D. > 12 bit A/D with 200Hz sampling rate. > > > An FPGA does not have an ADC internally, so you need to add power for > that. > > > > The Atmel AVR will draw less power than the Atmel 8051. > > I'd try out with an ATmega8, which has internal R/C oscillator and power > > down mode. > > > -- > > Best Regards > > Ulf at atmel dot com > > These comments are intended to be my own opinion and they > > may, or may not be shared by my employer, Atmel Sweden. > > > > Btw Ulf, What's your idea about MSP430 series suggested by Jim Granville? > > Best Regards > Arash > >

"Hal Murray" <hmurray-nospam@megapathdsl.net> wrote in message news:u5cqir37sbqve2@corp.supernews.com... > The tri-state long lines go all the way across the chip. > You can't split them up into shorter segments. Small correction: [XC4010] Yes, you can -- into two sets of half long lines. In 1995 I built a 32-bit RISC SoC where 16 rows of CLBs in the left half of the device used their 32 half long-lines and TBUFs for a 32-bit datapath result bux multiplexor, and where 16 rows of CLBs in the right half of the device used their 32 half long-lines and TBUFs for a 32-bit on-chip data bus. See www.fpgacpu.org/papers/j32.pdf, page 21, or the HTML rendering at http://www3.sympatico.ca/jsgray/sld021.htm. Jan Gray, Gray Research LLC

"Theron Hicks" <hicksthe@........edu> wrote > Actually, I had thought I would > probably use the CE input, but I just wanted to verify that I had not missed > some type of clock gate circuit such as exists on the VirtexII series. If you look (via fpga_editor) at the clock buffers you will see that there is a clock gate circuit in SpartanII. At least there is a control pin which looks like a gate input (comp.pin = K.BUFn.CE). There must be some problem with using it and we will have to wait for Peter's memoirs before we get the story. Has anyone managed to (manually) use this resource?

> Small correction: [XC4010] Yes, you can -- into two sets of half long lines. Thanks for the correction. That means you could get four 16 bit busses on there - 2 on the left and 2 on the right. So you could use them for MUXing 4 sets of 16 bit registers. The layout would be horrible if you needed to transfer data from one set of registers to the others. You could interleave two pairs though. ?? -- These are my opinions, not necessarily my employer's. I hate spam.

>From the table of contents (found on http://www.barnesandnoble.com) it appears that basic arithmetic, MACs, and SOPs take up the first 66 pages, then there's about 270 pages on computation of special functions using Cordic, and it ends with about 90 pages of references and source code. Is this an accurate description of the contents? It looks useful to me as I am interested in practical Cordic details and can always use good HDL examples, but I wonder if someone hoping for a more comprehensive treatment of DSP with FPGAs would be disappointed. regards, tom Ray Andraka wrote: > > There is a new book out by Uwe Meyer-Baese titled "Digital Signal Processing with > FIeld Programmable Gate Arrays" ( > http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka/102-6110898-2675311) > that is well written and covers many of the aspects of DSP with FPGAs. It is > featured on the bookstore page on my website (links to Amazon: if you use the > link above or go through my website I get a kickback which helps to support the > website). I very highly recommend this book. > -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3

Looks like they truncated the table of contents. The chapters are: 1. Intro, which goes over FPGA architectures, 25 pages 2. Computer arithmetic. Covers computer arithmetic from the slant of hardware. Includes distributed arithmetic and cordic discussion, 46 pages, 3. FIR filters 34 pages 4. IIR filters 24 pages 5. Multirate signal processing -- decimation &interpolation, polyphase decomp, CIC filters, Multistage decimators, Frequency sampling, filterbanks, wavelets. 59 pages 6. Fourier Transforms -- 42 pages 7. Advanced topics -- Rectangular and number theoretic transforms, error control and cryptography, modulation & demodulation --76 pages 8 . references and source code 76 pages If you decide to buy this book please use this link: http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka/102-6110898-2675311 or go through the link on my website bookstore. The sales commision I get helps to support the website. Thanks. Tom Burgess wrote: > From the table of contents (found on http://www.barnesandnoble.com) it appears that > basic arithmetic, MACs, and SOPs take up the first 66 pages, then there's about 270 > pages on computation of special functions using Cordic, and it ends with about 90 pages > of references and source code. Is this an accurate description of the contents? > > It looks useful to me as I am interested in practical Cordic details and can always use > good HDL examples, but I wonder if someone hoping for a more comprehensive treatment of > DSP with FPGAs would be disappointed. > > regards, tom > > Ray Andraka wrote: > > > > There is a new book out by Uwe Meyer-Baese titled "Digital Signal Processing with > > FIeld Programmable Gate Arrays" ( > > http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka/102-6110898-2675311) > > that is well written and covers many of the aspects of DSP with FPGAs. It is > > featured on the bookstore page on my website (links to Amazon: if you use the > > link above or go through my website I get a kickback which helps to support the > > website). I very highly recommend this book. > > > > -- > Tom Burgess > Digital Engineer > Dominion Radio Astrophysical Observatory > P.O. Box 248, Penticton, B.C. > Canada V2A 6K3 -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Jim Granville wrote: > Error recovery in data blocks is possible with correction, but > how does a system detect config or latch errors ? I can imagine at least 2 possibilities: i) By continously reading the configuration and comparing it with a reference bitstream ii) Built in self-tests and many other fault-tolerant system design concepts (TMR, ..). Michael

I get the following error message from ModelSim. I am clocking the DLL with a 100MHz signal (thus the observed 10 ns period) I am using an XC2S15-6TQ144 device which allow a 100MHz clock frequency. What is happening? By the way this is the input to the DLL. Thanks, Theron Hicks # ** Warning: */X_CLKDLL PERIOD High VIOLATION ON CLKIN; # Expected := 11.111 ns; Observed := 10 ns; At : 4015.663 ns # Time: 4015663 ps Iteration: 0 Instance: /testbench/uut/u2 # ** Warning: */X_CLKDLL PERIOD Low VIOLATION ON CLKIN; # Expected := 11.111 ns; Observed := 10 ns; At : 4020.663 ns # Time: 4020663 ps Iteration: 0 Instance: /testbench/uut/u2 (...repeated for each clock cycle.)

Muzaffer Kal wrote: > > > else > > counter<=counter; > >end > > It is OK except you don't need the final else block. counter remembers > its value when there are no events which change it. > That depends on what synthesis tool is being used. In earlier versions of FPGA Express (I haven't used it in a while, so I don't know if this still applies) an undefined state would cause a latch to be inferred. For example, if the default: option was not provided in a case statement, a latch would be inferred. When I learned Verilog, we were taught the importance of making sure that all states were defined - don't let the synthesis tool guess what to do in the case of an undefined state. -- Davis Moore

Set your simulator resolution to 10 ps. The DLL model requires a fine resolution to make it work right. For modelsim : vsim -t 10ps Theron Hicks wrote: > I get the following error message from ModelSim. I am clocking the DLL with > a 100MHz signal (thus the observed 10 ns period) I am using an > XC2S15-6TQ144 device which allow a 100MHz clock frequency. What is > happening? By the way this is the input to the DLL. > > Thanks, > Theron Hicks > > # ** Warning: */X_CLKDLL PERIOD High VIOLATION ON CLKIN; > # Expected := 11.111 ns; Observed := 10 ns; At : 4015.663 ns > # Time: 4015663 ps Iteration: 0 Instance: /testbench/uut/u2 > # ** Warning: */X_CLKDLL PERIOD Low VIOLATION ON CLKIN; > # Expected := 11.111 ns; Observed := 10 ns; At : 4020.663 ns > # Time: 4020663 ps Iteration: 0 Instance: /testbench/uut/u2 > > (...repeated for each clock cycle.) -- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com "They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

In the 7000, the -7 means clock to output. In the 10K, the -1 means nothing. It is simply the fastest version of that particular part. Altera sells -1, -2 and -3 versions of a part and whatever comes out fastest is a -1. Second fastest is a -2 and third fastest is a -3. When they do a die shrink, all the parts get faster, but the part numbers don't change. The only numbers that matter are the ones that come out of the simulator. If the simulator says it is fast enough, it is. If the simulator says it isn't fast enough, it isn't. Alan Nishioka alann@accom.com Chris Cowdery wrote: >I've got a cut down PCI design which works nicely in a >MAX7256SQC208-7. I have changed device to a FLEX10KA30-1 to port it to >CardBus. > >What I do not understand is why the simulation shows that the design >on the FLEX10K part has delays of about twice that of the 7256, even >though the flex part is a -1, and the max is a -7? Thus the timing >becomes marginal to say the least, yet the datasheet claims PCI 33MHz >compliance. > >Any ideas? > >-- > >Chris Cowdery >e-mail c.cowdery@nxtsound.TAKE-THIS-BIT-OUT.com >

"Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag news:3C566A0E.BE6990C@iprimus.com.au... > > > Falk Brunner wrote: > > > > I think Peter triggerd some inner gost of mine. > > I want to compute the EXACT number of unique functions possible with a 4 > > input LUT... > > It depends on the exact definition of a function. > To get 64k functions from a 4-bit lut, one could > assume that all 4 input bits are dedicated to one > function, and that all combinations of inputs are > valid. Then by defining function as "the set of Hmm, I see what you mean. Like Y = !A and B is also a valid function for a 4I-LUT. > input->output maps", there'd by 2^16. However, NO!! Why? Just look. (Fixed font) DCBA Y Y2 0000 0 0 0001 1 0 0010 0 0 0011 1 0 0100 0 0 0101 1 0 0110 0 0 0111 1 0 1000 0 1 1001 1 1 1010 0 1 1011 1 1 1100 0 1 1101 1 1 1110 0 1 1111 1 1 The function Y and Y2 are IDENTICAL. Y = A Y2 = D This is just a permutation of inputs. > the LUT inputs can be divided between smaller > sub-LUTs, so that for two 2-input LUTs, each > has 16 functions, so the total in this case No, see my last posting. For a 2 input LUT it can be easyly proven on a sheet of paper by writing down all functions as I did. > is 2x16=32 functions. Its easy to give a > seemingly wrong answer if the question > doesn't have enough restrictions. Yes. So, now to the 4I-LUT. For 4 unique elements (the inuts of the LUT), there are 4! = 24 possible permutations, like ABCD, BCDA etc. I hacked a small program to compute for every of the 2^16 codes all 24 permutations and check how much are equal. If they all are the same, the code is unique one (like the very obvious case "0000000000000000"). Iam not 100% sure if my theory is correct and that there is no bug in my small program, but here my first results. For a 4I-LUT there are 32 unique functions (all permutations identical, this includes "0000000000000000" and "1111111111111111") 96 functions with 3 permutations -> giving 96/3 = 32 individual functions 896 functions with 4 permutations -> giving 896/4 = 224 individual functions 1344 functions with 6 permutations -> giving 1344/6 = 224 individual functions 20160 functions with 12 permutations -> giving 20160/12 = 1680 individual functions 40008 functions with 24 permutations -> giving 40008/24 = 1667 individual functions ---------------------------------------------------------------------------- ------------------- 65536 functions total, with 32+32+224+224+1680+1667=3859 different logic functions, this includes all functions using 0,1,2,3,4 inputs. Here is the source code. Its good old TurboPascal. Takes about 1 minute to compute on my Duron 850. program permutation; { A program to compute the number of unique logic functions that can be programmed into a 16 bit ROM (LUT) } uses crt,dos; const A=3; B=2; C=1; D=0; debug=false; const per: array[0..23,0..3] of byte=((A,D,B,C), (A,D,C,B), (A,B,D,C), (A,B,C,D), (A,C,D,B), (A,C,B,D), (B,D,A,C), (B,D,C,A), (B,A,D,C), (B,A,C,D), (B,C,D,A), (B,C,A,D), (C,D,B,A), (C,D,A,B), (C,B,D,A), (C,B,A,D), (C,A,D,B), (C,A,B,D), (D,A,B,C), (D,A,C,B), (D,B,A,C), (D,B,C,A), (D,C,A,B), (D,C,B,A)); type t_bytearray= array [1..65534] of byte; {64 kbyte buffer} p_b = ^t_bytearray; var i,j,k,starttime,endtime,code: longint; h,m,s,s100: word; basic_LUT: array[0..3,0..15] of byte; perm_LUT: array[0..3,0..15] of byte; perm_pos: array [0..23,0..15] of byte; perm_data: array [0..23,0..15] of byte; perm_uni: array [0..23,0..15] of byte; stat: p_b; final_stat: array[1..24] of longint; num_perm: integer; cond: boolean; taste:char; function get_my_time: longint; begin gettime(h,m,s,s100); { get system time } get_my_time:=s100+s*100+m*6000+h*360000; end; function cmp_perm: boolean; { compare two permutations for permutation table } begin if (perm_LUT[0,j]=basic_LUT[0,k] ) and (perm_LUT[1,j]=basic_LUT[1,k] ) and (perm_LUT[2,j]=basic_LUT[2,k] ) and (perm_LUT[3,j]=basic_LUT[3,k] ) then cmp_perm:=true else cmp_perm:=false; end; function cmp_perm_code: boolean; var l_i: integer; begin l_i:=0; while ( (perm_data[j,l_i]=perm_uni[k,l_i]) and (l_i<15)) do inc(l_i); if l_i<15 then cmp_perm_code:=false else begin if perm_data[j,15]=perm_uni[k,15] then cmp_perm_code:=true else cmp_perm_code:=false; end; end; begin while keypressed do taste:=readkey; { clear keyboard buffer } clrscr; starttime:=get_my_time; writeln('Hello World'); writeln('Just kidding ;-)'); writeln('A brute force attempt to solve the magic LUT puzzle'); if debug then writeln('Debug mode OFF'); new(stat); for i:=1 to 65534 do stat^[i]:=0; { clear statistics } for i:=2 to 24 do final_stat[i]:=0; final_stat[1]:=2; { account for LOW and HIGH } writeln(' Initialze the MOTHER table '); if debug then begin writeln(' DCBA'); taste:=readkey; end; For i:=0 to 15 do begin basic_LUT[3,i]:=i and 1; basic_LUT[2,i]:=(i shr 1) and 1; basic_LUT[1,i]:=(i shr 2) and 1; basic_LUT[0,i]:=(i shr 3) and 1; if debug then begin writeln(i:2,' ',basic_LUT[0,i],basic_LUT[1,i],basic_LUT[2,i],basic_LUT[3,i]); end; end; if debug then begin writeln('Hit any key to continue'); taste:=readkey; end; writeln(' Initializing Permutation tables '); { generate all 24 LUT permutations } for i:=0 to 23 do begin { generate permutated truth table } for j:=0 to 15 do begin perm_LUT[A,j]:=basic_LUT[per[i,A],j]; perm_LUT[B,j]:=basic_LUT[per[i,B],j]; perm_LUT[C,j]:=basic_LUT[per[i,C],j]; perm_LUT[D,j]:=basic_LUT[per[i,D],j]; if debug then writeln(perm_LUT[0,j],perm_LUT[1,j],perm_LUT[2,j],perm_LUT[3,j]); end; if debug then taste:=readkey; for j:=0 to 15 do begin k:=-1; repeat inc(k); until cmp_perm; perm_pos[i,j]:=k; end; end; writeln('Done'); if debug then begin writeln(' Permutation table'); for i:=0 to 15 do begin for j:=0 to 23 do begin write(perm_pos[j,i]:2,' '); end; writeln; end; taste:=readkey; end; writeln('Calculation permutations of all codes'); writeln('from "0000000000000001" to "1111111111111110"'); for i:= 1 to 65534 do { code loop } begin if stat^[i]=0 then begin for j:=0 to 23 do { permutation loop } begin for k:=0 to 15 do { truth table loop } begin perm_data[j,k]:=(i shr perm_pos[j,k]) and 1; perm_uni[j,k]:=0; { clear table in parallel } if debug then write(perm_data[j,k]); end; if debug then writeln; end; if debug then taste:=readkey; { check numer of unique permutations } num_perm:=0; for j:=0 to 23 do begin cond:=false; for k:=0 to num_perm do begin if cmp_perm_code then cond:=true; { when equal, set flag } end; if not cond then { a new permutation??} begin for k:=0 to 15 do { copy permutation into database } begin perm_uni[num_perm,k]:=perm_data[j,k]; end; inc(num_perm); end; end; if debug then begin for j:=0 to 23 do begin write(j,' '); for k:=0 to 15 do begin write(perm_uni[j,k]); end; writeln; end; taste:=readkey; writeln(i,' ', num_perm); taste:=readkey; end; stat^[i]:=num_perm; { write down number of permutations } end; if i mod 256=0 then write('.'); end; write('Calculating statistic . . .'); for i:=1 to 65534 do begin if debug then writeln(i,' ',stat^[i]); if stat^[i]=0 then writeln ('Statistic ERROR') else inc(final_stat[stat^[i]]); end; writeln('finished'); { dispose(stat);} J:=0; writeln('4 input LUT statistic');writeln; for i:=1 to 24 do begin if i=1 then begin writeln(final_stat[1]:5,' unique functions (including "1111" and "0000") '); end else begin writeln(final_stat[i]:5,' functions with ',i,' permutations'); end; J:=J+final_stat[i]; end; taste:=readkey; writeln('Sum over all functions = ',j); Writeln('Finished'); endtime:=get_my_time; i:=(endtime-starttime) div (100*60*60); j:=((endtime-starttime) - i*(100*60*60)) div (100*60); k:=((endtime-starttime) - i*(100*60*60)-j*(100*60)) div (100); writeln('Computed in ',i:2,':',j:2,':',k:2); taste:=readkey; end. Comments are very appeciated. -- MfG Falk

Hello everyone, Iam using ISE & modelsim for a few weeks, things are getting better ;-) But doing a plain functional simulation of comparators using dont cares does not work. Yes, there is a warning in the docu of ISE about the use of dont cares, but is thereno workaround for this?? Can I write my own resolution function to make a dont care really dont care?Anyone has done this before and got some code? -- Regards Falk

Thanks! - This is much more like it - Your contents listing would make a useful review comment for other prospective buyers since Amazon didn't provide ANY detailed info, hence my visit to the competition. You can expect your kickback from my purchase whenever Amazon gets around to it :) regards, tom Ray Andraka wrote: > > Looks like they truncated the table of contents. The chapters are: > > 1. Intro, which goes over FPGA architectures, 25 pages > > 2. Computer arithmetic. Covers computer arithmetic from the slant of hardware. Includes > distributed arithmetic and cordic discussion, 46 pages, > > 3. FIR filters 34 pages > > 4. IIR filters 24 pages > > 5. Multirate signal processing -- decimation &interpolation, polyphase decomp, CIC filters, > Multistage decimators, Frequency sampling, filterbanks, wavelets. 59 pages > > 6. Fourier Transforms -- 42 pages > > 7. Advanced topics -- Rectangular and number theoretic transforms, error control and > cryptography, modulation & demodulation --76 pages > > 8 . references and source code 76 pages > > If you decide to buy this book please use this link: > http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka/102-6110898-2675311 > or go through the link on my website bookstore. The sales commision I get helps to support > the website. Thanks. > > Tom Burgess wrote: > > > From the table of contents (found on http://www.barnesandnoble.com) it appears that > > basic arithmetic, MACs, and SOPs take up the first 66 pages, then there's about 270 > > pages on computation of special functions using Cordic, and it ends with about 90 pages > > of references and source code. Is this an accurate description of the contents? > > > > It looks useful to me as I am interested in practical Cordic details and can always use > > good HDL examples, but I wonder if someone hoping for a more comprehensive treatment of > > DSP with FPGAs would be disappointed. > > -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3

I've only tried XST once, the design i used took hours and eventually bombed out. I would only recommend it for the smallest/simplest designs and for 'experimenting' with VHDL perhaps. I predominantly use Leonardo but have used Synplicity a few times. In my experience they produce similar results, Synplicity does sometimes seem to compile a little faster though. All round i prefer Leonardo, mainly due to it's user interface and systhesis control options, the only crashes i've had seem to be related to unplugging the dongle.

Antonio, I do not quite understand your question. You can, of course store your three blocks of data "side-by-side" in a 512 x 36 BlockRAM, and then use a multiplexer to select. But that is obvious. A BlockRAM is also a ROM, and the access time is the same... Ciao Peter Alfke, Xilinx Applications ================================ Antonio wrote: > I've a little bit of confusion on my mind, hope you could help to > clear something to me, this is the problem : > > I've 3 block each large 512x12 bits (... in each of it are stored some > polyphase sum for a different interpolation rate) , depending on the > rate selected I need to connect only one of this to the rest of the > circuit but for this operation is not required an high speed. I've > some idea : > > 1) Arrange each block in a different BlockRAM initialized using CORE > GENERATOR and then switch between them with a case > > 2) Only one RAM not initialized and three constant depending on the > rate I load the ram with the values stored in three different ROM or > defined with a constant (I don't know if it is the same). > > 3) Arrange each block in a ROM using the case construct which is > recognized by XST and mapped on a ROM, by the way which is the > speedest, blockRAM or this kind of ROM ?? For the selection of the ROM > depending on the rate I could use the CASE again. > > 4) Use a constant which I think produde a big multiplexer > > 5) your suggestion > > I'm interested in speed, hope to reach at least 165MHz on VirtexE 600 > -6 , so this is the key of lecture of this post > > Thanks > > Antonio

I am looking for answer to ERROR: MapLab:30 Bad format for LOC constraint <output> ... in ISE 4.1i. To bypass this error set the environment variable to 'XIL_MAP_LOCWARN'. What is a solution to this error?

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