Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
In telecom clock recovery, there's always a "jitter gain" near the PLL's corner point (the frequency where the PLL's VCO stability takes over and no longer tracks the small/fast changes in phase). In a system that has two nodes feeding back to each other so that they feed off each other's timing, it would make sense that the system would go unstable because of the positive gain. If you don't care about phase alignment to the incoming data, just frequency, you might be able to avoid the jitter gain by using a first order filter on the PLL. This pretty much eliminates standard charge pump PLLs. Quite the sticky wicket! Greg Neff wrote: > On Thu, 07 Mar 2002 06:10:09 GMT, > allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote: > > See my reply to John_H as to why we want to implement a democratic > clock. > > I took a quick look at the parts you were kind enough to provide links > to. One part has two clock inputs. The other has many clock inputs. > The problem is that the PLL selects one of the inputs to be the > reference. We would want a PLL that would accept three reference > clocks simultaneously. The PLL output would be a function of all > three clocks. One reference clock would be the local XO. The other > two clocks would be recovered from the two E1 receivers. The output > of the PLL would then provide the clock for both E1 transmitters. > This is the general idea. We are trying to figure out if this idea > will work reliably in practice, and would like to find any information > that exists on this type of scheme. > > (snip) > > > >As the other posters have mentioned, a "democratic" approach to timing > >is unusual, and (to me) doesn't make sense. > > > >Regarding the ITU-T specifications, I think you should look at the > >SONET/SDH specs instead of the E1 ones. > >Try: ITU-T G.707 (SDH) and the G.810 series (SDH timing). > >Also GR-253 (SONET). > > > >Even the Network Time Protocol (RFC1305) that is used to synchronise > >time of day clocks on computers has a hierarchy of timing sources. > >But it might give you some ideas that will help you with your problem. > >http://www.ietf.org/rfc/rfc1305.txt > > > >Oh, you should probably look at the datasheets for chips that are > >designed for phone network timing, e.g. Zarlink (nee Mitel) MT90401 > >http://products.zarlink.com/partfinder/prodprofile.cgi?device=1127 > >or maybe this one from Semtech: > >http://www.semtech.com/products/sets.html > > > >Regards, > >Allan. > > =================================== > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.comArticle: 40476
Nial Stewart <nials@britain.agilent.com> writes: > Petter Gustad wrote: > > > > "Peter Ormsby" <faepete.deletethis@attbi.com> writes: > > > > > Lars Rzymianowicz <larsrzy@atoll-net.de> wrote in message > > > news:3C85C76F.3B5FA1A5@atoll-net.de... > > > > And since Xilinx and most other EDA vendors support Linux now, why > > > > step down to the bluescreen? > > > > > > Just to be clear here, the Xilinx Linux solution is currently limited to > > > command-line only on WINE. For those unfamiliar with this approach, check > > [...snip...] > > > > Does anybody know why Xilinx did this rather than porting their > > Solaris/HP-UX version to Linux? > > > > Petter > > We've found that Xilinx tools running on HP Unix aren't as fast > as those running on a (comparable ?) PC. I've found that the Xilinx tools running on some 5-6 year old SUN machines are not as fast as those running on a 6 month old PC. I expeced this was due to the slow machine. Does anybody here have access to a 900MHz UltraSparc III style machine to do a benchmark against a Windows PC? > I think this is because the tools are written on PCs and ported > to Unix/workstation architecture. I heard some rumors that Xilinx developers used Linux as a development platform internally since it doesn't crash as frequently as Windows. Actually the command line tools (ngdbuild, map, par etc.) appears to be UNIX style programs, at least they use -options rather than /options. The first time I used XACT was on a SPARC/SunOS plattform. > Porting this port back to Linux/PC architecture again might have the > effect of slowing them even more. Somebody (here?) reported a speed increase over Windows when they were running under WINE. This would indicate the contrary it there were no measurement errors. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 40477
Do someone knows what is the clamping diode ? Where is it used ? and Why ? Thanks.Article: 40478
Is it possible to multiply a clock (40MHz) by 3 (or 1.5 will do) in a virtex CLKDLL? Regards, Niv.Article: 40479
Nial Stewart wrote:
>
>
> I wonder how many people use Nativelink? I'm sure it's not a high priority
> for testing, although this isn't good, they should take it out rather than
> have it and it doesn't work.
>
According to this article, Tim Southgate has been saying that
Altera is going to deemphasize internally developed frontend tools, and
will concentrate their software efforts on backend tools.
http://www.ebnews.com/story/OEG20020121S0029
That makes sense, considering that LS-Altera seems to synthesize better
circuit than its in-house QII Verilog synthesis tool in my case.
Then, isn't NativeLink going to be more important than ever?
I don't care how many people actually use NativeLink, but as
long as FLEX10KE/ACEX1K is on the support device list, and NativeLink is
officially supported (assuming that the correct version of LS-Altera is
used. Yes, I used the latest version LS-Altera 2002a_014, and still
didn't work properly until I figured out the workaround from an advise
from someone else who replied to my question.) Altera should test it to
make sure the thing works.
Otherwise, don't officially support such a feature/device.
> > Having seen these software problems, it is not surprising to me
> > that no wonder Altera has only 10% of a highend FPGA market, and rest of
> > 90% belongs to Xilinx.
>
> I'm surprised at this figure. Where did you get it, Xilinx marketing
> literature?
>
These articles should show that Altera is losing ground to
Xilinx in the highend FPGA market.
http://www.eetimes.com/story/OEG20020211S0025
http://www.eet.com/story/OEG20010423S0098
The X 90%/A 10% in the highend FPGA market is a number I heard
anecdotally, and I may have read that somewhere, too, but couldn't not
find an article that gave the 90%/10% number.
If I find it later, I will post that.
One number that came from Xilinx is that for FPGAs with 1.5V supply
voltage (Virtex-II or APEX-II), Xilinx has 97% and rest is likely Altera
has only 3%.
I do understand that Xilinx might be inflating the numbers, but
considering that Altera is losing ground to Xilinx in the highend, I am
not surprised with that number.
Although I forgot if the number is unit volume or revenue.
Regardless, the general consensus of the industry watchers seems
to indicate that Altera is definitely losing ground to Xilinx especially
in the highend.
Also, have you also noticed the number of Altera related questions on
this newsgroup?
They are far fewer than Xilinx related questions, and when you compare
the ratio of Virtex/APEX related questions, it seems to me the 90%/10%
number holds (or close to that to say the least).
Although to be fair, Altera supposedly doesn't pay its employee to
answer questions at news:comp.arch.fpga, so that might contribute to the
lower number of Altera related questions here.
I personally think they should change their policies, and pay their
employees.
> > I read some time ago on EE Times that much of the reason customers
> > choose Virtex instead of APEX20K several years ago is because the
> > quality of Quartus wasn't as good as Xilinx's software offering at the
> > time.
>
> What, you mean when Altera had just brought Quartus out some people
> chose Virtex because the (mature for a year or two) Xilinx tools
> were more stable.
>
I guess you either don't evaluate Xilinx device/software, and
strictly use Altera device/tool, or you don't read industry news.
http://www.eet.com/story/OEG20010423S0098
> This is stating the obvious. When Xilinx bring out their next big release
> of design software I'm sure the same thing will happen only the other
> way.
>
In case of ISE WebPACK 4.1 I tried, yes, there were lots of
Virtex-II related bugs, and I only experienced one serious bugs in the
first release that had to do with guided routing.
I personally don't really use (only accidentally discovered the problem)
guided routing, so I don't really care.
Since then, ISE WebPACK has had three Service Pack releases (now the
latest is 4.1WP3.0), so I will assume that the bug is fixed, but I
haven't tested whether or not guided routing bug is really fixed.
No, I am not saying that Xilinx is perfect, but from my experience, it
has far fewer problems related to software.
> > To me, software stability seems to be Altera's weakest point even now.
> > I believe my past criticisms of Altera, and the complaints I
> > made here are fairly valid ones, from a Xilinx ISE WebPACK user's point
> > of view, because it seem like Altera has lost so many users to Xilinx
> > that the only way it can bring them back will be to listen to customer
> > complaints, and fix the problems.
> > If they don't, they will likely keep loosing market share to Xilinx, and
> > I personally don't like to see Xilinx becoming too dominant (It is
> > always good to have a strong No. 2.).
>
> I've been using Quartus I/II for over a year on two Win98 machines
> and haven't had one crash, but I'm very careful about what gets loaded
> on the two machines.
>
When synthesis/P&R is going on, I rather want to use the
computer for some other purpose, and most of the time, it happens to be
web browsing (reading news:comp.arch.fpga postings or writing E-mails).
Because QII 1.1/2.0 uses a lot of System Resources, I often have far
less System Resources to run Netscape Navigator (that also drains a lot
of System Resources, too).
ISE WebPACK does use some amount of System Resources, but I seems to
keep the consumption near constant versus QII keep draining it.
Yes, I am sure that this System Resources draining issue is a structural
problem of Windows 98 to a lot of extent, Xilinx figured out a way to
limit the consumption, but Altera couldn't.
So, that is why one reason I prefer Xilinx tools over Altera tools.
No, I haven't tried QII on NT/2000/XP, and I don't planning on acquiring
a copy of it, but it will be interesting to see how QII fares on
NT/2000/XP.
> Both companies do some things well and some things not so well.
>
> Try a search in this newsgroup for the message by Jesse Kempa dated
> the 27th Feb in the thread on Xilinx's microblaze for an example.
>
> Nial.
Although I have no intention of defending Xilinx, I don't use
MicroBlaze, so I don't really care even if it is buggy.
Yes, I think Xilinx should have been more careful in debugging their
products.
However, at the end of the day, what I care is the stuff I use (most of
the time ISE WebPACK, and some occasional QII for to ensure my design is
vendor independent), and if brand X does well, and brand A doesn't, then
I just have to call brand A is inferior.
Honestly, I am surprised with some hysterical responses I got
from some die-hard Altera fans.
Please, don't get mad, and try out other vendors tools occasionally to
see if it is better than what you are using right now.
Note: I am paid by Xilinx to post this postings. I don't work at Xilinx
or its distributors, and all the opinions expressed are my personal
ones. If Altera's software was as good as Xilinx or better, I surely
won't be criticizing Altera that much.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 40480
I must say that when did we started to accept software bugs are a thing
to live with?
I suppose you can blame Microsoft/PC industry for that (A crash? Just
press the reset button.)
Yes, I already figured out a workaround for the QII 2.0 WE
(build around 1/22/2002) + LS-Altera 2002.014 (NativeLink) +
FLEX10KE/ACEX1K, but in QII 1.1 WE, NativeLink was totally dead when QII
1.1 WE + LS-Altera 2001a.028 was used.
I know I can workaround this problem, but it is not nice that it
happened considering that both packages came from Altera (Altera
distributed LS-Altera, not Mentor Graphics.).
Speaking of changing brands, Russell, you seem like an Altera
user, but why not use Xilinx Spartan-II instead?
I find Spartan-II easier to deal with then ACEX1K overall, but to some
extent, that is because I have more experiences with Xilinx tools than
Altera tools.
I use ISE WebPACK most of the time, and occasionally QII/LS-Altera to
make sure my design synthesizes properly with LS-Altera or QII's
in-house synthesis tool.
So, I guess I can call me a casual Altera user (like most WE users are),
and not a die-hard one like some people who post in this group (Who
become hysterical even with a small criticism. Please, take it easy.).
Therefore, at the end of the day, I can say that even if I have
problems, who cares because I don't use it that often.
Changing the subject, does QII 2.0 WE come with a user manual in
.PDF?
If not, where do I download it from?
I don't really like QII 1.1/2.0 WE, but I guess to some extent, I have
to live with it occasionally . . .
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Russell Shaw wrote:
>
>
> You can never assume largish software will be bug-free. I find
> and report bugs in all kinds of apps like mechanical/pcb cad packages,
> various compilers, etc. You *must* report bugs so that they get
> included in the next update. Mention you're a newish user so
> that the bug fixer can ask more relevant details. In the meantime,
> try to work around the problem. It's rare for the problem to be
> fatal *and* unavoidable, or it wouldn't be released. It is
> exceedingly frustrating to find a bug that crashes the app,
> but as long as it is acknowledged and logged, it makes you
> feel a little bit better that it'll be fixed some time. If
> it isn't, then think about switching brands.
Article: 40481On a similar note - can WebPack be run too? I've tried it under Debian (Woody), and failed - doesn't spit any error messages, just does nothing?! :-( (again wine works fine on others) Thanks Andy dano wrote: > Yes, I installed and configured WINE. And WINE works fine for many Windows > programs. Then I typed > $ wine setup > in the Installation directory. Then I entered my CDKEY. Then I select the > components I want to use. Everything seemed perfect before the real > installation begun. It just stuck at 0%. Finally, I lose my patience and > ^C-ed the WINE. > The message on console indicated that the whole thing froze when "Create > ProcessA" for the JRE1.2.2 which ISE 4.1 is bundled with. > I checked the Internet, but find nothing about how to install Xilinx ISE 4.1 > on my Debian GNU/Linux box. I am runing unstable dist. > Any suggestion? > Thank you.Article: 40482
"dano" <dano@china.com> wrote in message news:<a67t2q$nsb$1@news.cz.js.cn>... > Yes, I installed and configured WINE. And WINE works fine for many Windows > programs. Then I typed > $ wine setup > in the Installation directory. Then I entered my CDKEY. Then I select the > components I want to use. Everything seemed perfect before the real > installation begun. It just stuck at 0%. Finally, I lose my patience and > ^C-ed the WINE. > The message on console indicated that the whole thing froze when "Create > ProcessA" for the JRE1.2.2 which ISE 4.1 is bundled with. > I checked the Internet, but find nothing about how to install Xilinx ISE 4.1 > on my Debian GNU/Linux box. I am runing unstable dist. > Any suggestion? > Thank you. I saw on the Xilinx Web site that ISE4.2 is now supported on RedHat7.2 NewmanArticle: 40483
Kevin Brace wrote: > > Note: I am paid by Xilinx to post this postings. I don't work at Xilinx ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ So how'd you manage to get paid for posting your opinions??? :-0 > > or its distributors, and all the opinions expressed are my personal > ones. If Altera's software was as good as Xilinx or better, I surely > won't be criticizing Altera that much. >Article: 40484
In the context of digital I/O's, they are part of the I/O cell and put between the pin and the 2 supply rails (power/ground). They prevent (within the limit of the diodes current handling capability) the I/O pin from ever going one diode voltage drop above or below the supplies as this could damage the chip and/or cause latchup. They are normally off, but will turn on when these limits are exceeded. Regards "Zak smith" <zakhama@sympatico.ca> wrote in message news:<5uNh8.13997$4E4.2812181@news20.bellglobal.com>... > Do someone knows what is the clamping diode ? > Where is it used ? and Why ? > > Thanks.Article: 40485
Continuing (or, "IC Design 101, for non-majors"), They (the didoes) are the junctions of the PMOS and NMOS transistors with respect to the body connection of the transistors. They are not separable from the transistors themselves, unless tricks are used to float the body of the device (floating wells). Floating the pmos body is used for "5V tolerance" for example. But once you float the body, you have no clamp, and you may have real problems making your ESD requirements (protection against electro-static discharge). To meet ESD, a separate protection scheme must be used (scr, bipolar, zener, etc) that will meet he 5V tolerance, but protect the devices from ESD destruction. Oh, and a floating well device behaves differently from when the body is tied to something, so predicticting and modeling performance needs to be done very carefully..... To meet 3.3V PCI, you have to have a clamp, so now the floating well has to have a (large) switch in series to clamp the well again when needed. All of that protection stuff, and extra switches, adds capacitance, and slows down the performance of the IO (as well as increases area on the die). If the protection is poor, it may pass 5V (be 5V tolerant) but pop (breakdown) on insertion due to some static discharge. So, you can't have your cake (really fast IOs), and eat it (with 5V tolerance and ESD protection), too. Latchup is related to the parasitic junctions of the CMOS transistors that create a SCR. If you trigger the SCR, it latches up, shorting Vcco to Ground. IC designers have to be extra careful to design their devices so this can not occur. By designing the transistors to have really rotten alphas (or betas if you are unfamiliar with alpha in NPN or PNP devices), you can actually prevent the parasitic SCR from having enough gain to trigger at all. Austin PS: all of this assumes a standard logic cmos process that can be easily and economically made in the world's foundries. Special processes are interesting, but for real products, they are useless. Jay wrote: > In the context of digital I/O's, they are part of the I/O cell and put > between the pin and the 2 supply rails (power/ground). They prevent > (within the limit of the diodes current handling capability) the I/O > pin from ever going one diode voltage drop above or below the supplies > as this could damage the chip and/or cause latchup. They are normally > off, but will turn on when these limits are exceeded. > > Regards > > "Zak smith" <zakhama@sympatico.ca> wrote in message news:<5uNh8.13997$4E4.2812181@news20.bellglobal.com>... > > Do someone knows what is the clamping diode ? > > Where is it used ? and Why ? > > > > Thanks.Article: 40486
I'm getting ERROR:MapLib:93 - Illegal LOC on symbol "ucs" (pad signal=ucs) or BUFGP symbol "ucs_BUFGP" (output signal=ucs_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. and presumably need to tell it I have no intention of using a clock input for that signal. I've dug up old postings but the solutions don't relate to Webpack. How do I fix it with Webpack besides doing something with the signal so it doesn't look like a clock anymore ? JonArticle: 40487
Niv wrote: > Is it possible to multiply a clock (40MHz) by 3 (or 1.5 will do) in a > virtex CLKDLL? This is not possible in the Virtex (or Spartan-II) DLL, but it is very easy in the Virtex-II DCM. Peter AlfkeArticle: 40488
I could not even launch the WebPACK_41wp30_full_installer.exe using WINE. the WebPack installation crashed. And I have not find any word about "Webpack" and "WINE" on the Net. So maybe it is simply one word -- impossible. "Andy Main" <andymain@blueyonder.co.uk> ??????:3C868A77.809930FD@blueyonder.co.uk... > On a similar note - can WebPack be run too? I've tried it under Debian > (Woody), and failed - doesn't spit any error messages, just does nothing?! :-( > (again wine works fine on others) > > Thanks > > Andy >Article: 40489
well said! >so predicticting >and modeling performance needs to be done very carefully.....Article: 40490
Hi David - I would suggest a chat with the Lattice FAE who covers you - we do have some conversion utilities - either the FAE or techsupport@latticesemi.com - which can convert to ABEL equation format - if the changes are simple, you could then modify the ABEL files, or perhaps get some help in converting the DSL to VHDL from techsupport or your local FAE. Dave> But the current design software does not >support the old DSL language. Are there any tools or shortcuts that we >could use to convert the old DSL project to newer VHDL code? We don't >actually need to make any significant changes to the Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.comArticle: 40491
Salman Sheikh wrote:
>
> Hello,
>
> I have a question for anyone out there familiar with Xilinx FPGA design. I am using Xilinx ISE and during the design rule check of the place & route (after writing out the verilog netlists and sdf files for post-route simulation), I get messages like the following:
>
> WARNING: DesignRules: 372 - Netcheck: Gated clock: Clock net fsync1/CPUINTERFACE_0/N_115_inferred_clock is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
How about:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity CPUWRTGEN is
port( RST :in std_logic;
CPU_ADDR :in std_logic_vector (10 downto 0);
WRT :out std_logic_vector (30 downto 0));
end CPUWRTGEN;
architecture BEHAVIOR of CPUWRTGEN is
signal CPU_ADDR_INT: unsigned(5 downto 0);
begin
CPU_ADDR_INT<=unsigned(CPU_ADDR(5 downto 0));
process(CPU_ADDR_INT)
begin
WRT<=(others=>'1');
if CPU_ADDR_INT(10 downto 6)="01000"
then WRT(to_integer(CPU_ADDR_INT-9))<='0';
end if;
end process;
end BEHAVIOR;
-----------------
Article: 40492
In article <f0hh8.26266$eb.1298355@news3.calgary.shaw.ca>, "Albert" <wagain@hotmail.com> wrote:
> Thank you all of your responses. I am new in Canada, so I cant go to USA
> unless getting an offer first. But maybe I should go to Toronto or Ottawa
> 'cause somebody says that it is a little easier to find a job there than in
> Vancouver. Is there anyone from Toronto or Ottawa? Could you please tell a
> little about this kind of job market there? I have no much stuff yet, so I
> can move very easily.
>
Ottawa is not "hot" right now. Call back in six months.
We still have to "digest" those Nortel people :-)
The most unfortunate part about the downturn in high tech, is
that when high tech companies don't need people, they tend to
stop updating their career web pages. Also, generally speaking,
the interesting positions are NOT being placed on the big job
boards, like "monster". You really have to visit the companies
own website to find out what is available (tricky huh!).
For example, Sun Microsystems in CA had positions listed that
I didn't find listed elsewhere.
Good Luck
Mr. "Permanent Vacation In Ottawa"
Article: 40493David Brown wrote: > > Hi, > > We have an old project that used a Mach 5 PLD, programmed in DSL using > MachXL software, around 3 years ago. We are now looking at updating the > project, and using a Mach 4 PLD instead (when we started, there were no Mach > 4 chips that were big enough). But the current design software does not > support the old DSL language. Are there any tools or shortcuts that we > could use to convert the old DSL project to newer VHDL code? We don't > actually need to make any significant changes to the functionality of the > design, just to fit it into a newer chip, so we'd really like to avoid > having to re-write everything in VHDL (or Verilog). The normal 'open' design flow creates a Berkeley PLA file, and then runs a fitter on that. Sometimes these have .TT2 extensions. BLIF format is another variant, that can be selected in ABEL flows. This allows older source files to target newer devices, but lattice may be more 'closed' than that. you are tight, rewrite just to use a new device does not sound a good idea. -jgArticle: 40494
Petter Gustad wrote > Actually the command line tools (ngdbuild, map, par etc.) appears to > be UNIX style programs, at least they use -options rather than > /options. The first time I used XACT was on a SPARC/SunOS plattform. The first time I used XACT was on a 8MHz 8086, running MS-DOS 3.1. If this was developed on UNIX, the boys and girls at Xilinx sure knew a thing or two about writing portable code :-)Article: 40495
Kevin Brace wrote: > > I must say that when did we started to accept software bugs are a thing > to live with? > I suppose you can blame Microsoft/PC industry for that (A crash? Just > press the reset button.) > Yes, I already figured out a workaround for the QII 2.0 WE > (build around 1/22/2002) + LS-Altera 2002.014 (NativeLink) + > FLEX10KE/ACEX1K, but in QII 1.1 WE, NativeLink was totally dead when QII > 1.1 WE + LS-Altera 2001a.028 was used. > I know I can workaround this problem, but it is not nice that it > happened considering that both packages came from Altera (Altera > distributed LS-Altera, not Mentor Graphics.). > Speaking of changing brands, Russell, you seem like an Altera > user, but why not use Xilinx Spartan-II instead? Because altera had free tools a few years ago when xilinx insisted on charging $200 maintenance fees whenever they felt like it (i only wanted to learn fpga techniques and had some projects i could apply it too). > I find Spartan-II easier to deal with then ACEX1K overall, but to some > extent, that is because I have more experiences with Xilinx tools than > Altera tools. I have xilinx webpack on my pc and started to learn it to convert to spartan2 because i got a problem with the acex1k design that i couldn't narrow down without spending a few $k on the exemplar tools just to get a schematic/technology viewer to see how the vhdl was being translated to logic. I was using maxplus2, but acex1k was put into quartus2 a few weeks ago, and it had a much better help system and was easier to learn about timing constraints in it. I also learnt a better way of doing clock division that may fix the bug i had (it only happened when i was using any kind of dual-port ram block in my design). I'm using a different approach now, so i can't test for that bug. If i get the same bug in the future and can't solve it, i'll learn more xilinx webpack;) > I use ISE WebPACK most of the time, and occasionally QII/LS-Altera to > make sure my design synthesizes properly with LS-Altera or QII's > in-house synthesis tool. > So, I guess I can call me a casual Altera user (like most WE users are), > and not a die-hard one like some people who post in this group (Who > become hysterical even with a small criticism. Please, take it easy.). > Therefore, at the end of the day, I can say that even if I have > problems, who cares because I don't use it that often. > Changing the subject, does QII 2.0 WE come with a user manual in > .PDF? > If not, where do I download it from? I haven't seen any. I don't like separate pdf help files. The help system in quartus2 is integrated well into the GUI, so you can get context directed help from anywhere in the application. Separate pdfs are for unix dinasaurs;) > I don't really like QII 1.1/2.0 WE, but I guess to some extent, I have > to live with it occasionally . . . > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.) > > Russell Shaw wrote: > > > > > > You can never assume largish software will be bug-free. I find > > and report bugs in all kinds of apps like mechanical/pcb cad packages, > > various compilers, etc. You *must* report bugs so that they get > > included in the next update. Mention you're a newish user so > > that the bug fixer can ask more relevant details. In the meantime, > > try to work around the problem. It's rare for the problem to be > > fatal *and* unavoidable, or it wouldn't be released. It is > > exceedingly frustrating to find a bug that crashes the app, > > but as long as it is acknowledged and logged, it makes you > > feel a little bit better that it'll be fixed some time. If > > it isn't, then think about switching brands.Article: 40496
newman <newman5382@aol.com> wrote in message news:e6038423.0203071338.2e220f61@posting.google.com... > I saw on the Xilinx Web site that ISE4.2 is now supported on RedHat7.2 > > Newman Newman, This is slightly misleading. See this post: http://groups.google.com/groups?hl=en&scoring=d&selm=D9Bh8.13448%24Or3.14935 91%40typhoon.mn.ipsvc.net -Pete-Article: 40497
On Thu, 7 Mar 2002 15:27:24 -0000, "Tim" <tim@rockylogic.com.nooospam.com> wrote: >Allan Herriman wrote > >> BTW, I see a significant speedup for large designs in Synplify if I >> use the syn_hier attribute, which stops optimisations across module >> boundaries. > >How big a speedup? I have wondered about this but never had an >opportunity to measure it on truly large designs. A single syn_heir on one of the top level modules took the time from 4 hours to about 2.5 hours for one particular design. >Presumably the gain increases as the design size goes up. When >syn_hier is asserted I would expect compilation time to be linear >with design size. Without this attribute, is compilation time >quadratic with size, or worse? > >If the company coding style include flops at the exit of all logic >blocks I would not expect syn_hier to have much effect, though this >style can be pretty hard to enforce for the control logic part of an >application. Synplify will "optimise" to a certain extent across flip flops. It will do things like fanout control, and (optionally) pipelining, which allows it to move combinatorial logic to the other side of a flip flop, to improve the overall cycle time. I always have pipelining turned off though. Regards, Allan.Article: 40498
Hi Salman, The culprit in your code is the following : "if CPU_ADDR (10 downto 6) = "01000" and CPU_ADDR_INT = I then" This is creating a gated clock. Falk has given the right way to code.It's a healthy coding practice. Regds. SANKET. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a68b0c$cjq0g$1@ID-84877.news.dfncis.de>... > "Salman Sheikh" <sheikh@pop500.gsfc.nasa.gov> schrieb im Newsbeitrag > news:20020307102855.29f702fc.sheikh@pop500.gsfc.nasa.gov... > > > WARNING: DesignRules: 372 - Netcheck: Gated clock: Clock net > fsync1/CPUINTERFACE_0/N_115_inferred_clock is sourced by a combinatorial > pin. This is not good design practice. Use the CE pin to control the loading > of data into the flip-flop. > > > > I suspect this is the reason for the inferred clock since there is not clk > controlling the write strobes. > > How do I remedy the controlling the loading of the date into the flip-flop > via the CE pin? > > process (clk) > begin > if clk='1' and clk'event then > if load='1' then > flipflip<=data; > end if; > end if; > end process; > > This gives you a nice clock enable without gated clocks.Article: 40499
Jon Schneider <jschneider@cix.ceeowe.ewekay> wrote in message news:<3C87F0CE.25AD4750@cix.ceeowe.ewekay>... > I'm getting > > ERROR:MapLib:93 - Illegal LOC on symbol "ucs" (pad signal=ucs) or BUFGP > symbol > "ucs_BUFGP" (output signal=ucs_BUFGP), IPAD-IBUFG should only be > LOCed to > GCLKIOB site. > > and presumably need to tell it I have no intention of using a clock > input for that signal. > > I've dug up old postings but the solutions don't relate to Webpack. > > How do I fix it with Webpack besides doing something with the signal so > it doesn't look like a clock anymore ? > > Jon hi jon you better instantiate an input buffer IBUF. pass your input signal through IBUF take the output of IBUF and use that signal internally for your logic. suppose if your external input signal is x and x' is your buffer output then x ---->|IBUF|----> x' . now use x' for your logic enjoy regards MPS
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z