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Messages from 47075

Article: 47075
Subject: Re: Modelsim-Altera gate level simulation
From: "Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl>
Date: Mon, 16 Sep 2002 23:21:23 +0200
Links: << >>  << T >>  << A >>
Hi guys,

> > Thats the problem. If I type add wave -r /* it seems to take hours and
> > yet produces nothing. I have to kill the process in the end.
>
>
> Haven't seen that.

I have.

The problem occurs when you run out of physical RAM and Modelsim starts
swapping. Virtual memory takes about 1000x to access as core memory so...

Ben



Article: 47076
Subject: ISE 4.2i: Some bugs in ECS, State CAD Modelsim_XE.
From: "Adolfo Mora" <amora@ing.unal.edu.co>
Date: Mon, 16 Sep 2002 14:31:35 -0700
Links: << >>  << T >>  << A >>
I have begun to use ISE 4.2i in a course that I´m teaching in the present semester, here at the National University, in Bogotá, Colombia. In previous semesters I used Foundation Software. I have been working with SPARTAN and with XC4000. I have found the followings bugs in ISE 4.2i:

Schematic entry (ECS): - It isn't possible to incorporate logibloxes into an schematic, and there aren´t free cores for SPARTAN family, that could be used in place of logibloxes.
- The process for synthesis of an schematic based design is too slow.

State CAD: - If the state´s outputs are defined like vectors, then errors appear when it is going to generate the VHDL code, that obligate to change the vectors to scalars.
- The VHDL code generated for an FSM is very complex. There are others forms simplier to generate that code.
-There isn't the possibility of configurate one trap state, nor the "safest" option, for the illegal state that appear when "one hot" coding is selected. 

Modelsim_XE: - Frecuently the results of behavioral and post synthesis simulations are different, being, in such cases, the less reliables, that of behavioral simulation.
- Also frecuently the simulations don't agree with the expected results, but when the .bit file is downloaded to the board, the circuit functions correctly.

    Thanks.

          Adolfo Mora

Article: 47077
Subject: Re: Question about Virtex-II DCM's jitter
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Sep 2002 15:21:16 -0700
Links: << >>  << T >>  << A >>
Larry,

Wow.  I'd like to see anything with that low a jitter specification.  It is almost
unbelievable.  We have never seen anything with less than 20 ps P-P jitter in the
lab, once it was properly measured over a few million samples.  Even on parts that
had such wildly optomistic specifications.

RMS to P-P is a magic art, and I would suggest that 15X to 20X is more reasonable
for +/- 6 sigma which is going to be closer to the actual P-P measure once we tail
fit to a guassian curve.  that is one reason why clock oscillator people love
specifying RMS:  it is useless for the application, but it always looks nice.

Also the band limit makes it look nicer.  Unfortunately, digital logic doesn't care
about filtered bands, and a bit error is a bit error.  So in reality that
oscillator is probably 35 ps P-P full bandwidth, no better than any other good xtal
part.......

Austin

Larry Doolittle wrote:

> On Mon, 16 Sep 2002 10:45:52 -0700, Austin Lesea wrote:
> >jakab tanko wrote:
> >> In my oppinion one PLL in a DAC or ADC clock path is one to many..
> >
> >Tests in the lab show it attenuates the jitter from the DCM by 11X to 15X,
> >usually down to the noise floor of 35 ps P-P.
> >PLLs are just fine, you just need to know which ones to use, and when, and how
> >to use them.
>
> Quoting from the data sheet for an M-tron UVVJ Series LVPECL/LVDS
> Compatible Low Jitter VCXO, for f0 in the range 20 MHz to 175 MHz:
>
> Phase jitter 0.35 typical/1.0 Max ps RMS  Integrated 12 kHz - 20 MHz
>
> 0.35 ps RMS would, in engineering practice, normally be translated to
> about 2.8 ps P-P.  Many other manufacturers have similar parts/specs.
>
> 'nuff said.
>
>       - Larry


Article: 47078
Subject: Re: Question about Virtex-II DCM's jitter
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Sep 2002 15:24:06 -0700
Links: << >>  << T >>  << A >>
All,

This by the way is what all cellular base stations do:  synthesize, clean it up,
drive it to the A/D and D/A, and to the FPGAs.  They need sub ns RMS, or sub 10
ps P-P jitter at the A/D and D/A so as not to lose effective bit resolution.

Even a PLL internal to the FPGA is completely inadequate for this task due to
jitter (based on tests made on comparable products with PLL's inside).

Austin

Javier Serrano wrote:

> It was basically what he wrote to the newsgroup (please ask him if you want
> more details :)). I can only speak for myself and I've decided to have an
> external m/d PLL as John_H has suggested in his posting. For our application
> we need extremely low jitter, so we will use a very fine tuned analog PLL
> instead of trying to clean the clock coming from the Virtex-II DCM. The
> output of that PLL will be fanned out both to the Virtex-II and to the DAC.
> We have no choice but to put a PLL in the way because we need to multiply
> the frequency up from 40 MHz to 100 MHz to feed the DAC.
> Cheers,
>     Javier
>
> "jakab tanko" <jtanko@ics-ltd.com> wrote in message
> news:am51ej$iib$1@news.storm.ca...
> > Javier,
> >
> > Could you please share with us Austins reply?
> > In my oppinion one PLL in a DAC or ADC clock path is one to many..
> >
> > jakab
> > Javier Serrano <Javier.Serrano@cern.ch> wrote in message
> > news:am4ut3$s8i$1@sunnews.cern.ch...
> > > Thanks Austin, I will clean up the jitter for the DAC's clock using an
> > > external PLL.
> > > Cheers,
> > >     Javier
> > >
> > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> > > news:3D85EE57.E712CBA2@xilinx.com...
> > > > All,
> > > >
> > > > For people interested in cascading CLKFX, please email directly me
> about
> > > what
> > > > you are tyring to do.
> > > >
> > > > We have not finished characterizing all combinations of two cascaded
> > DCMs,
> > > so I
> > > > can not really comment for the general case here in the newsgroup at
> > this
> > > time
> > > > without knowing details.
> > > >
> > > > In addition to the CLKFX case, there is the CLK0, CLK2X  for the first
> > > stage.
> > > > Have got to test absolutely every combination!  Oh, and every M and D,
> > and
> > > every
> > > > frequency, over P/V/T, and in the worst SI environment allowed by the
> > data
> > > > sheet.....
> > > >
> > > > Javier's case looks like it will work fine (and I responded to him
> > > directly with
> > > > details), but I have other concerns about driving a DAC with a
> jittered
> > > clock
> > > > from an application point of view.
> > > >
> > > > Austin
> > > >
> > > >
> > > > Javier Serrano wrote:
> > > >
> > > > > Hi everyone,
> > > > > I'm trying to produce both a 100 MHz and a 200 MHz clocks from a 40
> > MHz
> > > > > input using the Virtex-II DCM, and I'm a bit worried about the
> jitter
> > > > > figures from the Virtex-II CLKFX online jitter calculator. The
> > solution
> > > I've
> > > > > chosen so far has two DCMs:
> > > > > - In the first DCM I multiply the 40 MHz by 5/2 to obtain 100 MHz,
> > which
> > > I
> > > > > use both internally in my design and as the input to the second DCM.
> > > > > - In the second DCM I multiply the 100 MHz by two to get 200 MHz.
> > > > > Incidentally, the CLK0 (100 MHz) output of this DCM is used to feed
> an
> > > > > external DAC and gets back from off-chip to the feedback input of
> the
> > > DCM.
> > > > > The problem is that, according to the jitter calculator I'll get 760
> > ps
> > > of
> > > > > p-p jitter (speed grade 4) in the 100 MHz clock coming out of the
> > first
> > > DCM.
> > > > > That is period jitter, and it is within the 1 ns jitter that the
> > second
> > > DCM
> > > > > allows for at its input. However, the Virtex-II handbook also
> > specifies
> > > 300
> > > > > ps as the maximum cycle-cycle jitter for the input clock in
> > > low-frequency
> > > > > mode, and I don't know whether my 760 ps of jitter are smoothly
> > varying
> > > or
> > > > > not. Has anyone got experience with this type of problem? Should I
> be
> > > doing
> > > > > it in some other way?
> > > > > Thanks in advance,
> > > > >     Javier
> > > >
> > >
> > >
> >
> >


Article: 47079
Subject: Re: Virtex II packaging, why no QFP?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Sep 2002 15:25:28 -0700
Links: << >>  << T >>  << A >>
Uwe,

Good suggestion.  I passed it along.

Austin

Uwe Bonnes wrote:

> Austin Lesea <austin.lesea@xilinx.com> wrote:
> : Uwe,
>
> : The problem with lead frame packages is that they have about the worst
> : possible signal integrity (SI).  What this means is that switching noise,
> : ground bounce, jitter, etc. all balloon out of control.  As clock speeds
> : increase, all of these SI effects become more and more severe, and lead
> : frame packages become unusable.
>
> Then what about packaging the smaller Virtex II chips in BGA (1.27 mm pitch)
> packages, with a PCB friendly pinout : only outer two row and easily
> accessible pin in the innerest row carry signals that need to brought out,
> other pins are either NC or IO pins that may be traded off for relaxed PCB
> design rules.
>
> ...
> --
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


Article: 47080
Subject: Re: Virtex II packaging, why no QFP?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Sep 2002 15:41:22 -0700
Links: << >>  << T >>  << A >>
Larry!

Hey, folks go into production with FPGAs every day of the week now!  It is
important to us to have a < 15$ entry price point for Virtex II.

Who knows who is going to be successful, and be responsible for a winning product
line and a winning company?

Austin




Larry Doolittle wrote:

> On Mon, 16 Sep 2002 16:43:17 +0000 (UTC), Uwe Bonnes wrote:
> >Perhaps someone can commment, why the Virtex II family has no QFP package
> >option. BGA only means much finer PCB design rules, so the NRE costs for the
> >prototype board soar.  That there is a CS144 package shows that "low pin
> >count" applications are a target for Virtex II and a QFP240 package would
> >even nearly come close to the FGA256 in pin count.
>
> It's Xilinx's way of weeding out the low-budget amateurs.  The big
> players don't mind spending many thousands of dollars to prototype
> a board.  The cost of the prototyping effort, when amortized over
> thousands of units, is irrelevant, as long as it can be done quickly.
>
> As a card-carrying member of the low-budget amateur club, of course,
> this frustrates me.
>
>        - Larry


Article: 47081
Subject: Re: Multiple divide by 10
From: John_H <johnhandwork@mail.com>
Date: Mon, 16 Sep 2002 22:45:29 GMT
Links: << >>  << T >>  << A >>
I hope I don't make this simple item seem too complex, but...

Are you working with a CPLD or an FPGA? (last I looked there is no
comp.arch.cpld)
Are you working with one of the newer Xilinx FPGAs?
Do you want something "very readable" or "with fewest resources"?
Do you want all 6 derived clocks to transition on the same edge or do you want
them offset by a clock?
Do you have any other skew desires?  Aligning the 50MHz edge to the derived
clocks can be done with a DLL, for instance.
Are these square waves that you want to see or are you using them for internal
logic? (which would each want a one clock cycle enable to accompany the master
clock, ideally)
Do you indeed want all 7 clocks active at once or are you interested in using
only one of these clocks?


Denis Gleeson wrote:

> Hello ALL
>
> I have a 50MHz clock that I want to divide by 10 and then by 10
> and so on.
> Actual outputs required are
>
> 50MHz
> 5MHz
> 500KHz
> 50KHz
> 5KHz
> 500Hz
> 50Hz
>
> I think I could do a divide by 10 but I dont know how to achieve
> all these divides.
>
> I also wonder if I can have the main clock driving all flip flops together
> rather than have the MSB output of the first divide by 10 rippeling through
> to the next counter and so on.
>
> Im coding in Verilog so any suggestions there would help.
>
> Thanks
>
> Denis


Article: 47082
Subject: Re: 1.8V regulator needed for Spartan IIE
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 16 Sep 2002 15:45:49 -0700
Links: << >>  << T >>  << A >>
Ray,

The latest regulators that are not current limited, but current trip, or
current foldback are the issue:  if the foldback or trip can be delayed by
20 ms, then these too, also work fine.

If they trip or foldback, they can be fooled into shutting down by the
initial current that the part wants (even though it doesn't need it to
initialize).

See Xapp158 for all of the details:
http://www.support.xilinx.com/xapp/xapp158.pdf
and  http://www.support.xilinx.com/xapp/xapp450.pdf for Spartan II and IIE.

Austin

Ray Andraka wrote:

> True enough.  I missed the "Spartan" in the header.  A linear regulator
> is probably fine for the entier SpartanIIE line.  It is a problem for
> bigger virtexE devices.
>
> Falk Brunner wrote:
>
> > "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
> > news:3D855A81.437CC586@andraka.com...
> > > Much depends on the FPGA device too, if this is a 2000E, the linear
> > regulator is
> >
> > There is no 2000E in the Spartan-IIE family.
> > SCNR
> >
> > --
> > MfG
> > Falk
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 47083
Subject: Re: Multiple divide by 10
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 16 Sep 2002 16:05:28 -0700
Links: << >>  << T >>  << A >>
One simple design ripple-cascades a bunch of decimal counters.
Each decimal counter consists of four flip-flops with a common clock, each LUT
looking at its own Q and those of its three neighbors. You can code it in BCD,
if you so desire, or either of many other codes..
Then you use the MSB of one decade as the clock for the next higher decade.
It's simple, efficient, and repetitive, and uses little power.
The drawback is that it is not synchronous, i.e. all flip-flops do not change
on the same clock edge. Unacceptable in some systems, perfectly alright in
others.
You can do a synchronous design, but it will consume 25% more logic ( unless
you are very clever) and it takes more clock power. And all output changes
will occur within 1 or 2 ns.

Peter Alfke
=================
Denis Gleeson wrote:

> Hello ALL
>
> I have a 50MHz clock that I want to divide by 10 and then by 10
> and so on.
> Actual outputs required are
>
> 50MHz
> 5MHz
> 500KHz
> 50KHz
> 5KHz
> 500Hz
> 50Hz
>
> I think I could do a divide by 10 but I dont know how to achieve
> all these divides.
>
> I also wonder if I can have the main clock driving all flip flops together
> rather than have the MSB output of the first divide by 10 rippeling through
> to the next counter and so on.
>
> Im coding in Verilog so any suggestions there would help.
>
> Thanks
>
> Denis


Article: 47084
Subject: Viewing internal signals during Post route simulation.
From: Brijesh <brijesh_spamNot@vt.edu>
Date: Mon, 16 Sep 2002 23:11:31 GMT
Links: << >>  << T >>  << A >>
hi,

How does one view the internal signals during post route simulation?
Take a specific case.
If you have a 16 bit bus and have instantiated hardware primitives for each bit ( Ibuf and IOB register), how can one view the registered values as a bus?
Or some other internal bus, or even state variable (or register).
I can search the particular instance within top entity and then view a particular bit, but is there a more easier or general way to do it?
Specifucally for the platform: VHDL, Xilinx Device, Modelsim simulator.

Thanks
Brijesh


Article: 47085
Subject: Re: Question about Virtex-II DCM's jitter
From: ldoolitt@recycle.lbl.gov (Larry Doolittle)
Date: Tue, 17 Sep 2002 00:09:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Mon, 16 Sep 2002 15:21:16 -0700, Austin Lesea wrote:
>Wow.  I'd like to see anything with that low a jitter specification.  It
> is almost unbelievable.  We have never seen anything with less than 20 ps
> P-P jitter in the lab, once it was properly measured over a few million
> samples.

The difficult question is always "jitter relative to _what_"?

>RMS to P-P is a magic art, and I would suggest that 15X to 20X is more
>reasonable for +/- 6 sigma which is going to be closer to the actual P-P
>measure once we tail fit to a guassian curve.

If you measure a Gaussian curve, you should quote sigma (same as rms).
P-P is almost always (in analog systems) a lie.  The ratio of P-P to
rms is "application dependent".

>that is one reason why clock oscillator people love specifying RMS:
>it is useless for the application, but it always looks nice.

I must be unusual, because my application is much more sensitive to
rms than to P-P.

>Also the band limit makes it look nicer.  Unfortunately, digital logic
>doesn't care about filtered bands, and a bit error is a bit error.

Again, the question is "jitter relative to _what_".  If the system
is phase locked to a master source, then only jitter above the
PLL crossover point matters.  10 kHz is only a slightly optimisitic
value for such a crossover.  And yes, it does make a crystal look good.

    - Larry

Article: 47086
Subject: Re: 1.8V regulator needed for Spartan IIE
From: Ray Andraka <ray@andraka.com>
Date: Tue, 17 Sep 2002 02:26:34 GMT
Links: << >>  << T >>  << A >>
The issue I've had hasn't been the start up current, rather it has been the
operating current on the larger devices.  I have in my lab a COTS board that
used a linear regulator that folds back at about 7A to supply a pair of 2000E's
off a 5v supply.  It is completely inadequate, especially considering the
miniscule heatsink they put on it (it gets hot enough to discolor the nylon
washer without even loading configurations into the FPGAs).  In another COTS
board, there is an XCV6000 powered by a 10W switching regulator.  It is very
easy to exceed that as well.  At least that one doesn't have the same thermal
problems.  My point is people developing these third party boards are not
paying enough attention to the potential power dissipation of the parts,
especially the big ones.

Austin Lesea wrote:

> Ray,
>
> The latest regulators that are not current limited, but current trip, or
> current foldback are the issue:  if the foldback or trip can be delayed by
> 20 ms, then these too, also work fine.
>
> If they trip or foldback, they can be fooled into shutting down by the
> initial current that the part wants (even though it doesn't need it to
> initialize).
>
> See Xapp158 for all of the details:
> http://www.support.xilinx.com/xapp/xapp158.pdf
> and  http://www.support.xilinx.com/xapp/xapp450.pdf for Spartan II and IIE.
>
> Austin
>
> Ray Andraka wrote:
>
> > True enough.  I missed the "Spartan" in the header.  A linear regulator
> > is probably fine for the entier SpartanIIE line.  It is a problem for
> > bigger virtexE devices.
> >
> > Falk Brunner wrote:
> >
> > > "Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
> > > news:3D855A81.437CC586@andraka.com...
> > > > Much depends on the FPGA device too, if this is a 2000E, the linear
> > > regulator is
> > >
> > > There is no 2000E in the Spartan-IIE family.
> > > SCNR
> > >
> > > --
> > > MfG
> > > Falk
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> >  "They that give up essential liberty to obtain a little
> >   temporary safety deserve neither liberty nor safety."
> >                                           -Benjamin Franklin, 1759

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47087
Subject: Re: 1.8V regulator needed for Spartan IIE
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Tue, 17 Sep 2002 03:17:26 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3D869405.39A4A612@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:
>The issue I've had hasn't been the start up current, rather it has been the
>operating current on the larger devices.  I have in my lab a COTS board that
>used a linear regulator that folds back at about 7A to supply a pair of 2000E's
>off a 5v supply.  It is completely inadequate, especially considering the
>miniscule heatsink they put on it (it gets hot enough to discolor the nylon
>washer without even loading configurations into the FPGAs).  In another COTS
>board, there is an XCV6000 powered by a 10W switching regulator.  It is very
>easy to exceed that as well.  At least that one doesn't have the same thermal
>problems.  My point is people developing these third party boards are not
>paying enough attention to the potential power dissipation of the parts,
>especially the big ones.

Worse, aren't there nice switching regulators which can be cascaded
together to provide for more power?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 47088
Subject: FPGA Design and IP Cores
From: "Tina Falkenberg" <tina.falkenberg@worldnet.att.net>
Date: Tue, 17 Sep 2002 04:08:31 GMT
Links: << >>  << T >>  << A >>
Dear all,
check out the Website www.drfalkenberg.com

Thanks
 God bless
  Andreas Falkenberg



Article: 47089
Subject: Re: Viewing internal signals during Post route simulation.
From: Utku Ozcan <utku.ozcan@netas.com.tr.spam>
Date: Tue, 17 Sep 2002 08:53:56 +0300
Links: << >>  << T >>  << A >>
Brijesh wrote:
> 
> hi,
> 
> How does one view the internal signals during post route simulation?
> Take a specific case.
> If you have a 16 bit bus and have instantiated hardware primitives
> for each bit ( Ibuf and IOB register), how can one view the registered
> values as a bus?

  Find each bit part of the signal, that is connected to your primitive(s),
  in the synthesis output. It is the synthesis tool which modifies the
  name of the signal. Synthesis output is normally EDIF, but if your
  synthesis tool support visualization of output, it is easier to find
  the signal you need.

> Or some other internal bus, or even state variable (or register).

  The same. Synthesis tools normally change the name of the signal
  to indicate optimization occur (by default). You can switch off
  optimization on a signal basis, and thus you can "keep" the name
  of the signal, so that you can find it in Signals Pane of your
  RTL simulator.

> I can search the particular instance within top entity and then view a
> particular bit, but is there a more easier or general way to do it?

  There is not. You have to do it manually. Some guys might have clever
  scripts that match the optimized-out signal names out of the log files
  of synthesis/P&R tool.

> Specifucally for the platform: VHDL, Xilinx Device, Modelsim simulator.

  What is your synthesis tool?
 
> Thanks
> Brijesh

  Utku

Article: 47090
Subject: Re: Question about Virtex-II DCM's jitter
From: "Javier Serrano" <Javier.Serrano@cern.ch>
Date: Tue, 17 Sep 2002 08:42:18 +0200
Links: << >>  << T >>  << A >>
Austin, I've never measured such low jitters either but I always thought it
was my oscilloscope's limitation. Could you specify whether you take that
into account? I would say that if you measure the jitter between a signal
and that same signal delayed by some 1 ns of cable, you should find there
the floor of your measurement device. You could then subtract that straight
(p-p) or quadratically (rms) from whatever you measure afterwards. Is this
correct?
Javier


"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3D86595C.DA17ACBE@xilinx.com...
> Larry,
>
> Wow.  I'd like to see anything with that low a jitter specification.  It
is almost
> unbelievable.  We have never seen anything with less than 20 ps P-P jitter
in the
> lab, once it was properly measured over a few million samples.  Even on
parts that
> had such wildly optomistic specifications.
>
> RMS to P-P is a magic art, and I would suggest that 15X to 20X is more
reasonable
> for +/- 6 sigma which is going to be closer to the actual P-P measure once
we tail
> fit to a guassian curve.  that is one reason why clock oscillator people
love
> specifying RMS:  it is useless for the application, but it always looks
nice.
>
> Also the band limit makes it look nicer.  Unfortunately, digital logic
doesn't care
> about filtered bands, and a bit error is a bit error.  So in reality that
> oscillator is probably 35 ps P-P full bandwidth, no better than any other
good xtal
> part.......
>
> Austin
>
> Larry Doolittle wrote:
>
> > On Mon, 16 Sep 2002 10:45:52 -0700, Austin Lesea wrote:
> > >jakab tanko wrote:
> > >> In my oppinion one PLL in a DAC or ADC clock path is one to many..
> > >
> > >Tests in the lab show it attenuates the jitter from the DCM by 11X to
15X,
> > >usually down to the noise floor of 35 ps P-P.
> > >PLLs are just fine, you just need to know which ones to use, and when,
and how
> > >to use them.
> >
> > Quoting from the data sheet for an M-tron UVVJ Series LVPECL/LVDS
> > Compatible Low Jitter VCXO, for f0 in the range 20 MHz to 175 MHz:
> >
> > Phase jitter 0.35 typical/1.0 Max ps RMS  Integrated 12 kHz - 20 MHz
> >
> > 0.35 ps RMS would, in engineering practice, normally be translated to
> > about 2.8 ps P-P.  Many other manufacturers have similar parts/specs.
> >
> > 'nuff said.
> >
> >       - Larry
>



Article: 47091
Subject: Has ISE 5.1i shipped?
From: lyqin@cti.com.cn (Leon Qin)
Date: 17 Sep 2002 00:19:59 -0700
Links: << >>  << T >>  << A >>
any one knows?

Article: 47092
Subject: Re: Has ISE 5.1i shipped?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 17 Sep 2002 09:25:28 +0100
Links: << >>  << T >>  << A >>


Leon Qin wrote:

> any one knows?

And if it has are there any "user experiences" yet ?  Placer/Router are
worse:same:better than 4.x?


Article: 47093
Subject: Re: Multiple divide by 10
From: dgleeson@utvinternet.com (Denis Gleeson)
Date: 17 Sep 2002 02:06:29 -0700
Links: << >>  << T >>  << A >>
John_H <johnhandwork@mail.com> wrote in message news:<3D865F0B.F7DEDA63@mail.com>...
Hi John 

answers below

> I hope I don't make this simple item seem too complex, but...
> 
> Are you working with a CPLD or an FPGA? (last I looked there is no
> comp.arch.cpld)

FPGA; xilinx Spartan XCS05

> Are you working with one of the newer Xilinx FPGAs?
No
> Do you want something "very readable" or "with fewest resources"?

fewest resources, within reason.

> Do you want all 6 derived clocks to transition on the same edge or do you want
> them offset by a clock?

Transition on the same edge.

> Do you have any other skew desires?  Aligning the 50MHz edge to the derived
> clocks can be done with a DLL, for instance.
No

> Are these square waves that you want to see or are you using them for internal
> logic? (which would each want a one clock cycle enable to accompany the master
> clock, ideally)

50MHz and 5KHz will come out for external use. They will also be used
internally. The others will only be used internally.

> Do you indeed want all 7 clocks active at once or are you interested in using
> only one of these clocks?

One of either 50MHz or 5KHz will be active all the time to clock the
external device. For internal use only one of the 7 will be required
at any one time.


Thanks for your input.

Denis

> 
> 
> Denis Gleeson wrote:
> 
> > Hello ALL
> >
> > I have a 50MHz clock that I want to divide by 10 and then by 10
> > and so on.
> > Actual outputs required are
> >
> > 50MHz
> > 5MHz
> > 500KHz
> > 50KHz
> > 5KHz
> > 500Hz
> > 50Hz
> >
> > I think I could do a divide by 10 but I dont know how to achieve
> > all these divides.
> >
> > I also wonder if I can have the main clock driving all flip flops together
> > rather than have the MSB output of the first divide by 10 rippeling through
> > to the next counter and so on.
> >
> > Im coding in Verilog so any suggestions there would help.
> >
> > Thanks
> >
> > Denis

Article: 47094
Subject: C\C++ to VHDL Converter
From: "DJohn" <deepucjohn@yahoo.com>
Date: Tue, 17 Sep 2002 14:57:21 +0530
Links: << >>  << T >>  << A >>
Hi all VHDL experts,
  Is there any tools which can convert a C\C++ source file to VHDL . For
example If I have a C source code for a MP3 decoder , Can any tool can
convert it into VHDL equivalent. There is some facility in FPGA Advantage to
generate a wrapper VHDL for a  C File , what exactly is that ? Does that
mean I can synthesize a C\C++ file by creating a VHDL Wrapper.
Please help




Article: 47095
Subject: Re: ieee.math_real for presynthesis table calculation in vhdl
From: Brian Gogan <briang@xilinx.com>
Date: Tue, 17 Sep 2002 10:44:29 +0100
Links: << >>  << T >>  << A >>
XST 5.1.01i also supports the ieee.math_real package for constant calculations.
Brian.

Ray Andraka wrote:

> I think synplicity does now too.  My point is I'd like to see it in the LRM so
> that the code can be made portable between tools.
>
> Mike Treseler wrote:
>
> > Pete Dudley wrote:
> >
> > > Hello All,
> >
> > > for i in 0 to 255 loop
> > >   table(i) <= signed(round(64.0*sin(2*pi*i/256)));
> > > end loop;
> > >
> > > What I'm finding is that XST errors out, saying "Undefined symbol 'real'"
> > > when I include the math_real library
> >
> > Leonardo will accept IEEE.MATH_REAL functions but only for
> > constant definitions between IS and BEGIN.
> > See the example below.
> >
> >   -- Mike Treseler
> >
> > -----------------------------
> >
> > library ieee;
> >      use ieee.std_logic_1164.all;
> >      use ieee.numeric_std.all;
> >      USE IEEE.MATH_REAL.all;
> >
> > entity test_math is
> > end    test_math;
> >
> > architecture sim of test_math
> > is
> >
> >     constant pi            : real := 3.141592;
> >     constant vec_max       : real := (2.0)**16;
> >     constant sin_pi_over_8 : natural
> >        := integer(round(vec_max * sin(2.0*pi/16.0)));
> >     constant u_sin_pi_over_8 : unsigned(15 downto 0)
> >        := to_unsigned(sin_pi_over_8, 16);
> >
> > begin
> >   . . .
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 47096
Subject: Re: C\C++ to VHDL Converter
From: "Thomas Vogel" <ThomasVogel@web.de>
Date: Tue, 17 Sep 2002 12:49:26 +0200
Links: << >>  << T >>  << A >>

"DJohn" <deepucjohn@yahoo.com> wrote in message
news:am6s84$303tn$1@ID-159866.news.dfncis.de...
> Hi all VHDL experts,
>   Is there any tools which can convert a C\C++ source file to VHDL . For
> example If I have a C source code for a MP3 decoder , Can any tool can
> convert it into VHDL equivalent. There is some facility in FPGA Advantage
to
> generate a wrapper VHDL for a  C File , what exactly is that ? Does that
> mean I can synthesize a C\C++ file by creating a VHDL Wrapper.
> Please help
>

How about taking a look at SystemC www.systemc.org . As far as i know a
synthezisable subset of systemc exist but i dont find the document at this
moment.
You can also take a look to the following documents:
http://www.systemc.org/projects/sitedocs/document/SystemC_WP20/en/1
http://www.systemc.org/projects/sitedocs/document/E3/en/1

Hope i could help
Ciao



Article: 47097
Subject: Re: 1.8V regulator needed for Spartan IIE
From: Russell <rjshaw@iprimus.com.au>
Date: Tue, 17 Sep 2002 23:26:58 +1000
Links: << >>  << T >>  << A >>
"Nicholas C. Weaver" wrote:
> 
> In article <3D869405.39A4A612@andraka.com>,
> Ray Andraka  <ray@andraka.com> wrote:
> >The issue I've had hasn't been the start up current, rather it has been the
> >operating current on the larger devices.  I have in my lab a COTS board that
> >used a linear regulator that folds back at about 7A to supply a pair of 2000E's
> >off a 5v supply.  It is completely inadequate, especially considering the
> >miniscule heatsink they put on it (it gets hot enough to discolor the nylon
> >washer without even loading configurations into the FPGAs).  In another COTS
> >board, there is an XCV6000 powered by a 10W switching regulator.  It is very
> >easy to exceed that as well.  At least that one doesn't have the same thermal
> >problems.  My point is people developing these third party boards are not
> >paying enough attention to the potential power dissipation of the parts,
> >especially the big ones.
> 
> Worse, aren't there nice switching regulators which can be cascaded
> together to provide for more power?

The easy way is to make a multi-phase switching
regulator like on a pc motherboard.

Article: 47098
Subject: Re: XC2V Embedded Multipliers and Chipscope Usage
From: mark <mark@pac.net>
Date: Tue, 17 Sep 2002 13:54:00 GMT
Links: << >>  << T >>  << A >>
Hi Symon,

Thank you for your reply.  When I started to have the PAR errors, I chose to
reduce the number of signals.  While there were times where the depth was
1024, or more, I didn't look at the block RAMs to see what the width was in
those situations.  I'll definitely look at it today!

Sincerely,
Mark

Symon wrote:

> Dear Mark,
>          Try setting the depth of the chipscope sample storage  memory
> to 1024 or more. In my VirtexII design this forces the ILA BRAMS to be
> less than 36 bits wide. So, 1024 is 18 bits wide, 2048 is 9 bits wide
> etc.
>                     HTH, Syms.
>
> mark <mark@pac.net> wrote in message news:<3D7EDEFE.AC422DC8@pac.net>...
> > Hello,
> >
> > I'm working on a Xilinx XC2V6000 design which will make use of nearly
> > all (144) of the embedded multipliers and am trying to use Chipscope at
> > the same time.  I believe that Chipscope uses the block ram in a x36
> > configuration, because I am getting PAR "unroutable" errors now that the
> > number of multipliers is growing, due to design module integration.
> > When the number of multipliers + the number of Chipscope block rams is
> > about 144, or less, there are no PAR errors.  Also, I've read (in Google
> > and the Xilinx datasheets) that if a block ram and the adjacent
> > multiplier are used, then the width of the block ram is limited to x18
> > or less, so that the multiplier can be used, due to routing between the
> > multiplier and block ram.
> >
> > The basic flow is: VHDL -> synthesis -> Chipscope Inserter -> Xilinx
> > tools.  I've looked at the fpga using FPGA editor and it does seem that
> > the block ram is used in a x36 configuration.
> >
> > Could anyone tell me if this sort of issue is true when using the
> > embedded multipliers and Chipscope?  If so, is there a work-around, for
> > validation/debugging?  Can Chipscope use the block ram in a different
> > configuration?
> >
> > Thank you for your time,
> > Mark


Article: 47099
Subject: Re: Multiple divide by 10
From: "sweir" <weirsp@yahoo.com>
Date: Tue, 17 Sep 2002 13:55:01 GMT
Links: << >>  << T >>  << A >>
Denis, you can do a little better than the following for area, ( about 2
luts ) at the price of speed.  You can delete the test input if you like.
It is provided to limit test time by breaking-up the divider chain.  You
should change the state of test only while asserting rst.

reg             cla ;                   // divide by 10 carry look ahead
reg             bin1 ;                  //
...
reg             bin6 ;                  //
reg     [2:0]   pent1 ;                 //
...
reg     [2:0]   pent6 ;                 //

wire            bin1_ce ;               //
...
wire            bin6_ce ;               //
wire            pent3_ce ;              //
...
wire            pent6_ce ;              //

  assign  bin1_ce   = ( pent1 == 4'd0 ) | test;
  assign  bin2_ce   = ( cla && ( pent2 == ( 4'd0 ) | test ;
  assign  pent3_ce  = ( bin2_ce & ~bin2 ) | test ;
  assign  bin3_ce   = ( pent3_ce && ( pent3 == ( 4'd0 ) ) | test ;
  assign  pent4_ce  = ( bin3_ce & ~bin3 ) | test ;
  assign  bin4_ce   = ( pent4_c3 && ( pent4 == ( 4'd0 ) ) | test ;
  assign  pent5_ce  = ( bin5_ce & ~bin5 ) | test ;
  assign  bin5_ce   = ( pent4_c4 && ( pent5 == ( 4'd0 ) ) | test ;
  assign  pent6_ce  = ( bin5_ce & ~bin5 ) | test ;
  assign  bin6_ce   = ( pent4_c5 && ( pent6 == ( 4'd0 ) ) | test ;

  assign  clk_5m    = bin1 ;
  assign  clk_500k  = bin2 ;
  assign  clk_50k   = bin3 ;
  assign  clk_5k    = bin4 ;
  assign  clk_500   = bin5 ;
  assign  clk_50    = bin6 ;


/*--------------------------------------------------------------------------
--
  -- Always
  --------------------------------------------------------------------------
--*/
  always  @( posedge clk ) begin
    if( rst ) begin
      pent1 = 3'd4 ;
      pent2 = 3'd4 ;
      pent3 = 3'd4 ;
      pent4 = 3'd4 ;
      pent5 = 3'd4 ;
      pent6 = 3'd4 ;

      bin1  = 1'b1 ;
      bin2  = 1'b1 ;
      bin3  = 1'b1 ;
      bin4  = 1'b1 ;
      bin5  = 1'b1 ;
      bin6  = 1'b1 ;
    end
    else begin
      cla   = ( bin1 == 1'b0 ) && ( pent1 == 4'd1 ) ;
      pent1 = pent1 - 1 ;
      bin1  = bin1 ^ bin1_ce ;
      bin2  = bin2 ^ bin2_ce ;
      bin3  = bin3 ^ bin3_ce ;
      bin4  = bin4 ^ bin4_ce ;
      bin5  = bin5 ^ bin5_ce ;
      bin6  = bin6 ^ bin6_ce ;

      if( clu )       pent2 = pent2 - 1 ;
      if( pent3_ce )  pent3 = pent3 - 1 ;
      if( pent4_ce )  pent4 = pent4 - 1 ;
      if( pent5_ce )  pent5 = pent5 - 1 ;
      if( pent6_ce )  pent6 = pent6 - 1 ;
    end
endmodule


"Denis Gleeson" <dgleeson@utvinternet.com> wrote in message
news:6f080894.0209170106.5bf9216f@posting.google.com...
> John_H <johnhandwork@mail.com> wrote in message
news:<3D865F0B.F7DEDA63@mail.com>...
> Hi John
>
> answers below
>
> > I hope I don't make this simple item seem too complex, but...
> >
> > Are you working with a CPLD or an FPGA? (last I looked there is no
> > comp.arch.cpld)
>
> FPGA; xilinx Spartan XCS05
>
> > Are you working with one of the newer Xilinx FPGAs?
> No
> > Do you want something "very readable" or "with fewest resources"?
>
> fewest resources, within reason.
>
> > Do you want all 6 derived clocks to transition on the same edge or do
you want
> > them offset by a clock?
>
> Transition on the same edge.
>
> > Do you have any other skew desires?  Aligning the 50MHz edge to the
derived
> > clocks can be done with a DLL, for instance.
> No
>
> > Are these square waves that you want to see or are you using them for
internal
> > logic? (which would each want a one clock cycle enable to accompany the
master
> > clock, ideally)
>
> 50MHz and 5KHz will come out for external use. They will also be used
> internally. The others will only be used internally.
>
> > Do you indeed want all 7 clocks active at once or are you interested in
using
> > only one of these clocks?
>
> One of either 50MHz or 5KHz will be active all the time to clock the
> external device. For internal use only one of the 7 will be required
> at any one time.
>
>
> Thanks for your input.
>
> Denis
>
> >
> >
> > Denis Gleeson wrote:
> >
> > > Hello ALL
> > >
> > > I have a 50MHz clock that I want to divide by 10 and then by 10
> > > and so on.
> > > Actual outputs required are
> > >
> > > 50MHz
> > > 5MHz
> > > 500KHz
> > > 50KHz
> > > 5KHz
> > > 500Hz
> > > 50Hz
> > >
> > > I think I could do a divide by 10 but I dont know how to achieve
> > > all these divides.
> > >
> > > I also wonder if I can have the main clock driving all flip flops
together
> > > rather than have the MSB output of the first divide by 10 rippeling
through
> > > to the next counter and so on.
> > >
> > > Im coding in Verilog so any suggestions there would help.
> > >
> > > Thanks
> > >
> > > Denis





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