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HI all, I am familiar with VHDL . I found the following terms in the syllabus of a VLSI training School 1)standard cell based design 2)Gate array based design. Can somebody explain what are these ??Article: 48001
Hi, Modelsim kernel allows you simulate designs that are written in VHDL and/or Verilog, the top level design unit has to be either VHDL or Verilog and as you traverse the design hierarchy instantiations may freely switch between VHDL and Verilog. I am talking about Modelsim SE Plus 5.6d, in ISE you might have a license issue. Regards -- Ulises Hernandez Design Engineer ECS Technology Limited ulisesh@ecs-tech.com "Spam Hater" <spam_hater_7@email.com> wrote in message news:ed46qu0n35k65p0l9t1v37v54dn9905ng6@4ax.com... > > The description of ModelSim for (Xilinx) ISE specifically states that > this is not possible. (Probably a licensing issue with Mentor.) > > I would be very interested if someone could figure out a -legitimate- > way around it. > > SH7 > > On Tue, 8 Oct 2002 17:18:48 +0200, "Nico Toender" <n.toender@tuhh.de> > wrote: > > >Hi! > > > >Does anyone have experiences with above topic in ISE 4.x or 5.x? > > > >How about simulation with ModelSim? > > > > > >Thanks very much! > > Nico > > >Article: 48002
Petter Gustad wrote: > > kevinbraceusenet@hotmail.com (Kevin Brace) writes: > > > While I agree that Quartus II's help system is better than > > ISE's, Altera doesn't seem to have detailed manuals of their software > > available for download unlike Xilinx. > > I don't use the Quartus II GUI much other than for floorplanning and > building megafunctions. I do most of my work with Tcl scripts. Hence, > I wish they had the documentation available as PDF files. > > I would rather see improved functionality such as SMP and cluster > support for large PAR jobs rather than a fancier GUI. > > One big plus: Quartus II runs under Linux in native mode! > > The Quartus II Linux edition GUI behaves rather odd (at least under > fvwm2). It will always stay on top of all other windows. There is no > way to raise other windows like xterms on top of Quartus. Even when > minimized it punches through all other windows on the desktop. Have > anybody else experienced this behavior? I think there are various ways of overiding this involving X resources settings.Article: 48003
Hi skillwood, check this white paper, it will help u understand what they are. http://www.techaccel.com/v_whitepapers.html kiran. Kiran V Bulusu 11 LakeView Ave, #3, Reading,MA-01867 US. www.srikiran.net "skillwood" <skillwood@hotmail.com> wrote in message news:ao115k$ghqdk$1@ID-159866.news.dfncis.de... > > HI all, > > I am familiar with VHDL . > > I found the following terms in the syllabus of a VLSI training School > > 1)standard cell based design > 2)Gate array based design. > > Can somebody explain what are these ?? > >Article: 48004
Mike R. <mrandelzhofer@uumail.de> wrote: > The new ISE IDE is also worse than the old Foundation IDE. Use the command line. Simple, powerful and consistent between versions. > Furthermore a xilinx FAE told me that the fpga editor also died because of a > canceled contract with the manufacturer. This is a core tool which is a must > for fast verification of correct synthesis etc. ?? Do you mean that 5.1 has no FPGA editor? Or are you referring to Webpack? Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in anticipation. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 48005
I'm not a proffesional, CPLDs are just a jobby for me. All the sw tools I downloaded from configurable logic manufacturers are awkward. I use Aldec's Active-HDL tool to desing VHDL files and then refer to these files from Xilinx WebPack. Everything is integrated perfectly including simulator and schematic editor (directly saves circuits as vhdl netlists), error messages are comprehensive.Article: 48006
The 10K series routability is highly design dependent. For a heavily
arithmetic design, you hit a brick wall at slightly over 50% utilization with
reasonably high clock rates. It is not a function of the tool so much as the
routing structure of the device. That said, max plus's hide all the nasties
from the user is great if you aren't trying to push the part, but severely
gets in the way when you are. I've looked at the latest Quartus, but haven't
used it in a design yet. It looks like it is an improvement, but I can't say
how much.
As for the Xilinx SW, I have been very disappointed with the regression in
the last few releases. As far as I am concerned, 3.3sp8 was the last decent
software release Xilinx had, and unfortunately it doesn't handle virtexII
designs well (no sync multiply support, for example). 4.x has numerous bugs
that are show stoppers on big designs as well as on designs that push the
performance (floorplanner is seriously broken, mapper does a lousy job
packing, router no longer finds anywhere near as good a route given a
floorplanned placement as earlier versions did, and so on). 4.2 also has a
serious memory conflict problem under windows2K that causes it to fail on
larger designs. The official "fix" for many of the problems in the 4.2
software is to 'upgrade' to Version 5.1. Unfortunately, that software
introduces a whole new set of bugs, one of which increases map execution
time over 10 fold for designs with large or many RPMs, despite the patch in
sp1. I haven't gotten far enough through 5.1 to tell how badly it mangles
the result compared with previous versions....it takes way too long to get
through a carefully placed design.
The point is both manufacturers are merrily chasing the big green pushbutton
flow mirage, and the usability of the software for challenging designs is
suffering as a result. We don't need gratuitous changes to the user
interface, new bells and whistles, or even faster compile time at the expense
of quality of results. What we need is solid tools that don't barf with
every curve ball thrown at them. Let's get the bugs fixed in the current
features before going off and adding new stuff, then when you do add new
stuff don't leave the regression testing to the field.
Bob W wrote:
> I have had a different experience with MaxPlus.I have used the MaxPlus
> on many 10K50 designs. I have been able to fit with high utilizations
> (up top 90%) . The simulator showed me results that agreed with my
> logic analyzer and the scope on the final product.
>
> I have a Xilinx design in a Coolrunner CPLD. It is only using 55% of
> the resouces. However, I find that adding or deleting a few gates
> causes the design to fail on routing. Then if have to try rearranging
> the design until I can get a fit. I took the fitted design, done in
> ISE 4.2 and converted it to the new ISE 5.1 and it wouldn't fit. I put
> the fitter into "Exhaustive fit" mode. This is supposed to try all of
> the combinations of fitter parameters in a sequential fashion to
> determine the best fit. I let it run for 2 hours and it crashed when
> it finally consumed all of virtual memory on a Win2K 512Mb system.
> There must be a memory leak through each iteration of the fitter.
>
> >I can't say that the Xilinx tools are perfect. But when you do tough
> >designs I find it a lot easier to see what is going on with the P&R and
> >to find ways to deal with any problems. The pushbutton Altera approach
> >seems to get in the way of seeing what is actually happening under the
> >hood of your design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48007Russell <rjshaw@iprimus.com.au> writes: > Petter Gustad wrote: [...snip...] > > One big plus: Quartus II runs under Linux in native mode! > > > > The Quartus II Linux edition GUI behaves rather odd (at least under > > fvwm2). It will always stay on top of all other windows. There is no > > way to raise other windows like xterms on top of Quartus. Even when > > minimized it punches through all other windows on the desktop. Have > > anybody else experienced this behavior? > > I think there are various ways of overiding this involving > X resources settings. Do you know where these are documented? Quartus appears to be built using some kind of Windows compatible library since I see a process called "mwrpcss" running while Quartus is running. If I could get documentation on the X11 resources for this library I might figure out how to make it a well behaved X11 application. This behavior is specific for Quartus. All other applications like signalscan, emacs, xterm, opera, netscape etc. does *not* behave in this odd way. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48008
In article <anus53$hkp3q$1@ID-92522.news.dfncis.de>, Jensniemann@gmx.de
says...
> Hello,
> is there somewhere a reference design or some information about booting a
> SRAM-based FPGA via a USB interface?
> I am thinking to use one of Cypress's USB interfaces to programm a Spartan
> 2 via JTAG. This would be a very convenient solution for further programm
> updates.
> Any suggestions ?
>
I would ship over JTAG and use slave serial mode, MUCH faster than JTAG
and less software/firmware. I've not done it, but I think it would be
pretty easy to get one of the Cypress EZ-USB devices to do this.
Let us know what you come up with !!!
--
gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
=-=
= Greg Deuerling, Fermi National Accelerator Laboratory
=
= P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-
5406 =
= Electronic Systems Engineering Group
=
= Work: egads@fnal.gov Personal: gad@elnet.com
=
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
=-=
Article: 48009valentin tihomirov wrote > I use Aldec's Active-HDL tool to desing VHDL files and then refer to these > files from Xilinx WebPack. It is a great shame that Aldec and Xilinx do not love each other any more.Article: 48010
Petter Gustad wrote: > > Russell <rjshaw@iprimus.com.au> writes: > > > Petter Gustad wrote: > [...snip...] > > > One big plus: Quartus II runs under Linux in native mode! > > > > > > The Quartus II Linux edition GUI behaves rather odd (at least under > > > fvwm2). It will always stay on top of all other windows. There is no > > > way to raise other windows like xterms on top of Quartus. Even when > > > minimized it punches through all other windows on the desktop. Have > > > anybody else experienced this behavior? > > > > I think there are various ways of overiding this involving > > X resources settings. > > Do you know where these are documented? Quartus appears to be built > using some kind of Windows compatible library since I see a process > called "mwrpcss" running while Quartus is running. If I could get > documentation on the X11 resources for this library I might figure out > how to make it a well behaved X11 application. > > This behavior is specific for Quartus. All other applications like > signalscan, emacs, xterm, opera, netscape etc. does *not* behave in > this odd way. I've been looking for a list of *all* xresource variables. I can't find a specific layering setting now, but your window manager may say something. You can set layering in fvwm. Various linux admin books have a section on setting xresources. http://www.google.com/search?hl=en&lr=&ie=ISO-8859-1&q=xresourcesArticle: 48011
There is no problem using subranged integers for counters or other uses. Synplify will do a good job of using only the needed number of bits. - Ken Clyde R. Shappee wrote: > Hello, > > I working a design with some small counters in a design operating at 50 > MHz. They are at most 4 bits. Some 2. Some operate only at 10 MHz. > > The counters are written in my design in a behavioral style, and the > signals used for counting are integers, and never leave the chip. This > has been my style for a long time (years) and I have never worried about > it, and never had a problem. I always declare the range of the integers > used, so no wild 32 bit counters get inferred. > > I have been advised from both Apps engineers at Synplicity and Memec > Design Services that this is not an issue, that the tools will infer a > binary counter and be efficient about it. > > Another engineer says this is a bad idea, and that I should use only > std_logic_vector for these simple counters. > > I have yet to try implementing the design differently and look at the > RTL that Synplify generates, but will do tomorrow. > > Any thoughts? > > Clyde > >Article: 48012
Hamish, be careful with that. 4.2 has a bug where designs with large ncds gets a
memory conflict under win2K. We made that mistake, and had to run under NT4 in
order to continue on with the design. That 2v6000 design gets through map in an
hour and 40 minutes on an old 800 MHz P3 with 1GB (paging like crazy) under 4.2i
on NT, won't run on 4.2i under win2K, and takes over 25 hrs under 5.1 running on a
2GHz K7 with 2GB memory .
hamish@cloud.net.au wrote:
> Mike R. <mrandelzhofer@uumail.de> wrote:
> > The new ISE IDE is also worse than the old Foundation IDE.
>
> Use the command line. Simple, powerful and consistent between versions.
>
> > Furthermore a xilinx FAE told me that the fpga editor also died because of a
> > canceled contract with the manufacturer. This is a core tool which is a must
> > for fast verification of correct synthesis etc.
>
> ?? Do you mean that 5.1 has no FPGA editor? Or are you referring to
> Webpack?
>
> Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in
> anticipation.
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48013Bob W <fa@_NO_SPAM_AskTheOracle.com> wrote in message news:<4027qu8c300tboq2levt57s9t1sc51q2k7@4ax.com>... > On Tue, 08 Oct 2002 18:31:38 GMT, Bob W <fa@_NO_SPAM_AskTheOracle.com> > wrote: > > >Why can't Xilinx Software be as good as Altera Software? > > > P.S. I failed to mention that I am using (and comparing) the Altera > MaxPlus II software to the Xilinx ISE. > > Interesting discussion going on this topic. Howdy all, Frankly Im not Altera's fan, may be I'm bias, but this is my opinion: 1) Neither Altera or Xilinx SW is perfect. Both have some week points 2) Do not blame only on FPGA tools when tons of ugly thing still in your Windows 4) A normal sword in a good hand is always dangerous 5) Live and learn 6) No free lunch in USA 7) Expensive lunch is not always delicious 8) Let your wife choose her own flavor 9) Have a nice day... :)Article: 48014
Petter Gustad wrote: > > Russell <rjshaw@iprimus.com.au> writes: > > > Petter Gustad wrote: > [...snip...] > > > One big plus: Quartus II runs under Linux in native mode! > > > > > > The Quartus II Linux edition GUI behaves rather odd (at least under > > > fvwm2). It will always stay on top of all other windows. There is no > > > way to raise other windows like xterms on top of Quartus. Even when > > > minimized it punches through all other windows on the desktop. Have > > > anybody else experienced this behavior? > > > > I think there are various ways of overiding this involving > > X resources settings. > > Do you know where these are documented? Quartus appears to be built > using some kind of Windows compatible library since I see a process > called "mwrpcss" running while Quartus is running. If I could get > documentation on the X11 resources for this library I might figure out > how to make it a well behaved X11 application. > > This behavior is specific for Quartus. All other applications like > signalscan, emacs, xterm, opera, netscape etc. does *not* behave in > this odd way. Look for something like a ~/.quartus2rc or /usr/X11R6/lib/X11/app-defaults/quartus2 file. I think the xresource parameters are defined case-by-case by applications. http://www.student.math.uwaterloo.ca/~mtrudel/xtutorial.html http://www.ibiblio.org/pub/Linux/docs/HOWTO/other-formats/html_single/XWindow-User-HOWTO.html#XRESOURCESArticle: 48015
Clyde R. Shappee wrote: > I have been advised from both Apps engineers at Synplicity and Memec > Design Services that this is not an issue, that the tools will infer a > binary counter and be efficient about it. This is true. Integer/natural counters are easy and effective if you get the range right. > Another engineer says this is a bad idea, and that I should use only > std_logic_vector for these simple counters. This is a popular opinion, but I don't agree. A vector type does have the advantage of no range problems, but consider the [un]signed type with numeric_std functions. This lets you mix vectors and integer types without conversion, and, for a counter, gives you automatic roll-over to zero. -- Mike TreselerArticle: 48016
Hello Jens, I have recently done just this and had very good luck with it. We used the Cypress EZ-USB-FX to program a Spartan XCS20XL. This is the approach we used. Instead of using the JTAG Programmer to generate an SVF file, I used the PROM file creator to make a BIT file. This only contains the data to be written into the part. (The SVF files contain the bit patterns for the mode and clock lines.) This BIT file resides on the host hard disk. During initialization the file is sent over the USB with a bulk transfer. The 8051 in the Cypress chip takes each byte and shifts it out and clocks it into the Spartan using the OUTA function.( We mapped the Spartan onto five bits of port A). Here are the connections I used... PA0 : To the base of a FET that pulls INIT* low. ( 4K pullup on INIT*) PA1: DONE PA2: CCLK PA3: DIN PA4: INIT* PROG* has a 10K pullup. This means that I cannot reprogram the Spartan without powering down. Hope this helps. Regards, Chris Harthan Jens Niemann wrote: >Hello, >is there somewhere a reference design or some information about booting a >SRAM-based FPGA via a USB interface? >I am thinking to use one of Cypress's USB interfaces to programm a Spartan >2 via JTAG. This would be a very convenient solution for further programm >updates. >Any suggestions ? > >Regards, >Jens Niemann > >Article: 48017
Xu Qijun, your question seems pretty broad and may not be applicable to comp.arch.fpga. MP3 decoding (as far as I understand) is pretty complex, and you would be hard put to compete in the high volume end-consumer market where there exist low cost MP3 decoder ASICs. Take a look at www.pjrc.com for a public domain design of a hard drive based MP3 player. I think Paul shares the Xilinx code that interfaces between hard drive, SIMM buffer, 8051 controller, and MP3 decoder. Regards, -Steen "Karl" <Far@East.Design> wrote in message news:<3da385c5@news.starhub.net.sg>... > Hi, > > I have come across a low-end portable MP3 player, which uses a parallel > cable to load > songs into the SmartMedia cards and the player's internal memory. Can > anybody tell what > are the steps involved in designing this MP3 player? What core expertise do > I need to > design this toy? > > -- > Xu QijunArticle: 48018
Yepp, this helps definitely. Thanks, Jens Niemann > > Hope this helps. > > Regards, > Chris Harthan >Article: 48019
We stayed away from the phillips device because it has a PCI interface. PCI is
fine if you are hanging it on a PCI bus, lousy if you need to make a PCI
controller in the FPGA to talk to it. The NS part has a more conventional
microcontroller style interface.
bulletdog7 wrote:
> Theron,
>
> If you go the external route, you might look at Philips Semiconductors.
> I think they've got one with a PCI interface but I have no idea on price
> or availability. Just giving yet another vendor choice.
>
> Jerry
>
> Theron Hicks wrote:
>
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:3DA21E5F.8DD5ED3@andraka.com...
> >
> >>A while back we considered USB in the FPGA, but when push came to shove,
> >>
> > it was
> >
> >>cheaper to use an external USB chip. In our case, it was the original
> >>
> > USB, and
> >
> >>we used a National Semi chip, I think it was a USBN9603 which has both the
> >>controller and the PHY in one package for about $2.25. When we sized the
> >>
> > USB
> >
> >>for putting in the FPGA we still needed an external PHY, and it would have
> >>pushed us into a larger part costing far more than the off the shelf chip.
> >>
> > I
> >
> >>don't know if the situation is similar for USB2 or not, although I suspect
> >>
> > that
> >
> >>it is.
> >>
> >>
> > Ray,
> > I am beginning to think along the same lines. The chips are about the
> > same price ($2 to $3 or so) and the USB2 chip is proven. Why re-invent the
> > wheel, especially when the quantities are so low. Just for grins I priced a
> > USB2 core from MEMIC and the cost for net list only, was $30000. Then it
> > takes about 1500 slices to implement it. That would more than quadruple the
> > gate count on that particular card and we aren't using all that in the first
> > place.
> >
> > Has anyone tried out any of the new USB2 chips? Any comments on support and
> > availability for the small guy? (10 to 12 systems a year or less
> > initially...) Even experience with USB1 would be of interest as I am
> > uncertain as to exactly what I might be getting into in terms of degree of
> > complexity.
> >
> > Thanks,
> > Theron
> >
> >
> >>Theron Hicks wrote:
> >>
> >>
> >>>Hello,
> >>> I am developing an instrument that is currently communicating over a
> >>>special high speed parallel board. The data rate is 6.4 million 8 bit
> >>>
> > words
> >
> >>>per second. The board works great but it costs in excess of $1600 US
> >>>
> > per
> >
> >>>copy. It also occupies a full sized PCI slot. We are considering
> >>>implementing an alternative I/O arrangement such as USB2 or ethernet
> >>>(TCP/IP). Is anyone aware of free-ware USB2 implemented in VHDL or some
> >>>other FPGA friendly technology? Note: target FPGA is a Spartan2E (or
> >>>
> > if
> >
> >>>absolutely necessary, Virtex2).
> >>>
> >>>Thanks,
> >>>Theron
> >>>
> >>--
> >>--Ray Andraka, P.E.
> >>President, the Andraka Consulting Group, Inc.
> >>401/884-7930 Fax 401/884-7950
> >>email ray@andraka.com
> >>http://www.andraka.com
> >>
> >> "They that give up essential liberty to obtain a little
> >> temporary safety deserve neither liberty nor safety."
> >> -Benjamin Franklin, 1759
> >>
> >>
> >>
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48020Ray Andraka wrote: > > We stayed away from the phillips device because it has a PCI interface. PCI is > fine if you are hanging it on a PCI bus, lousy if you need to make a PCI > controller in the FPGA to talk to it. The NS part has a more conventional > microcontroller style interface. So, anybody knows of a USB2 host controller without PCI ? cheers & thanksArticle: 48021
Russell <rjshaw@iprimus.com.au> writes: > I've been looking for a list of *all* xresource variables. I can't These are application dependent. You would then need a list of resources used by all X11 applications. For example for FrameMaker I have the following entry in the file read by xrdb: Maker*background: gray85 Maker*winRect.background: gray85 For emacs I have: Emacs.background: gray85 Emacs.pane.menubar.background: gray85 and so on... Then you can run xrdb -merge filename. To get a list of all your active resource settings you can do xrdb -query > find a specific layering setting now, but your window manager may say > something. You can set layering in fvwm. Various linux admin books > have a section on setting xresources. > http://www.google.com/search?hl=en&lr=&ie=ISO-8859-1&q=xresources I know how to set X11 resources using xrdb. The problem is to know which resources are read by Quartus (if any). I don't think it's a problem with settings in fvwm2 since no application behaves this way other than Quartus (unless there is an option used by Quartus only). Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48022
Russell <rjshaw@iprimus.com.au> writes: > Look for something like a ~/.quartus2rc or > /usr/X11R6/lib/X11/app-defaults/quartus2 file. There is no such thing. Quartus installs itself in a separate directory tree and does not install anything under X11 or in your home directory. Everything related to the Quartus windows layer appears to be located in the directory called mw. Quartus does not seem to behave like a typical X11 application in this sense. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 48023
Hi! > is there somewhere a reference design or some information about booting > a SRAM-based FPGA via a USB interface? I am thinking to use one of > Cypress's USB interfaces to programm a Spartan 2 via JTAG. This would be > a very convenient solution for further programm updates. > Any suggestions ? The eval board from CESYS at http://www.cesys.com/ebene2/x2s_usb.htm has a Cypress EZ-USB (AN2131Q) chip on it. I wrote a small downloader which is available at http://www.johann-glaser.at/projects/X2S_USB/. It runs on Linux and uses libusb (http://libusb.sf.net/). Additionally it contains the 8051 program for the Cypress chip which does the work on the board. For another project (http://www.johann-glaser.at/projects/DSO/) I'm planning to use the same microcontroller. There I'd use the D0-D7 program pins of the FPGA to feed in the bitstream in slave parallel mode (extremely fast). You can use the FWR# line of the EZ-USB connected to the CLK line of the FPGA to toggle in the data. Look at my digital schematic at http://www.johann-glaser.at/projects/DSO/schematic/MainSchematic.png All these signals can be re-used after configuration is done to transport massive data from the PC to the FPGA and vice versa (see my DSO). Disclaimer: I didn't actually try this yet, so please don't hit me if it doesn't work. If you succeed with my infos, I'd be happy if you tell me of it. Bye HansiArticle: 48024
hamish@cloud.net.au wrote: : Mike R. <mrandelzhofer@uumail.de> wrote: :> The new ISE IDE is also worse than the old Foundation IDE. : Use the command line. Simple, powerful and consistent between versions. :> Furthermore a xilinx FAE told me that the fpga editor also died because of a :> canceled contract with the manufacturer. This is a core tool which is a must :> for fast verification of correct synthesis etc. : ?? Do you mean that 5.1 has no FPGA editor? Or are you referring to : Webpack? : Still waiting for v5.1 to arrive. Upgrading all machines to Win2000 in : anticipation. For a start, use the free downloadable Webpack, which is based on 5.1. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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