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Messages from 49300

Article: 49300
(removed)


Article: 49301
Subject: Re: LU-decomposition
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 08 Nov 2002 17:13:56 GMT
Links: << >>  << T >>  << A >>
On Fri, 08 Nov 2002 14:06:15 +0200, Utku Ozcan
<utku.ozcan@netas.com.tr.SPAMELA> wrote:

>
>> Hi anyone,
>> 
>> I'm trying to do a LU-decomposition with xilinx FPGA.
>> It's inside matlab but it's not in the xilinx blockset
>> which mean i cannot implement it using sysgen, any idea?
>
>Is the "decomposition" the one related to logic theory?
>Is it an academic research? Would you please more specific? 
>
>Utku

LU-decomposition is a matrix manipulation technique where a matrix A
is generated by multiplying two matrices L, U:

	L X U = A where L is a lower triangular (all elements on the
diagonal or below) and U is upper triangular. It is used in solving
linear equations more easily. The book numerical recipes gives good
algorithms for LU decomposition which have to be implemented in
hardware.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 49302
Subject: Help on using multiple ABEL sources
From: mx400@cox.net (Kirk)
Date: 8 Nov 2002 09:35:31 -0800
Links: << >>  << T >>  << A >>
Hi,
 I need a couple of pointers on using multiple source modules in an
ABEL design. I'm using Xilinx Webpack 5.1.  My basic question is, when
using ABEL design flow (only ABEL sources, no schematic)can multiple
source files be used to generate a single design? And, how do I
organize these in the sources window of the project navigator?

  Here's what brought up the question:  I have a design all in a
single .abl file to which I wanted to add a state machine.  I used
StateCAD to generate the state machine logic and an ABEL source module
with the state machine logic.  What's the best way to get the StateCAD
generated source to be part of my top level ABEL source?  For now,
just to get it to work, I cut and pasted the text of the StateCAD
generated file into my top level source.  This works but it is
inconvenient to have to re-paste the code every time I make a change
in StateCAD.

There must be a better way.  Thanks, 
Kirk

Article: 49303
Subject: Re: BUFT bus contention
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 8 Nov 2002 18:38:29 +0100
Links: << >>  << T >>  << A >>
"hiro" <hiro-ta@pd6.so-net.ne.jp> schrieb im Newsbeitrag
news:aqggl5$9b8$1@news01ch.so-net.ne.jp...

>   At this time, does bus contention occur on data_bus and hence
>   any damages to device?

The internal tristates on Virtex-II are no real tristates. They can't be
damaged.

--
MfG
Falk





Article: 49304
Subject: Re: Online pinouts of glue chips
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 08 Nov 2002 18:09:52 -0000
Links: << >>  << T >>  << A >>
>                                          The chip in question is
>the Phillips 74HCT245N, a non-inverting buffer. Seems the designed
>schematic does not aggree with the wired hardware. Has not been
>powered for that reason.

Most manufacturers have their data sheets on the web.  It may take
a bit of work to find them.  Sometimes google helps.

Usually the last character or several like the "N" above is the
package and/or packaging (tube vs tape and reel), so sometimes
it helps to remove it when searching.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 49305
Subject: Re: Modular Design for Project Manager 5.1.02
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Fri, 08 Nov 2002 11:40:20 -0700
Links: << >>  << T >>  << A >>
Philippe,

Modular design isn't completely intergrated with 5.1i yet. There are times that
you will still need to use commend lines.
Gui are used when you're doing initialy floorplanning, psudo port assignment,
code synthesis.
Individual gui can be called to assist you during individual module
implementation, but project navigator isn't well integrated with the whole flow
yet.

Regards, Wei

Philippe Robert wrote:

> Hello,
>
> I have recently installed Version 5.1 of Project Manager and two service
> packs. I am now about to start a big design. It has been split into blocks.
> It is a team work that we are aiming at. The idea here is to use Modular
> design.
> All I could from the Xilinx website is documents for Modular Design 4.2,
> which only works by typing command lines.
>
> Is there any GUI version of Modular Design for 5.1i ?
>
> That would be great really !
> Anybody can help me ?
>
> Thanks in advance.
> Philippe.


Article: 49306
Subject: functional test for Xilinx virtex II Pro
From: "Max K." <skmax@t2.technion.ac.il>
Date: Fri, 8 Nov 2002 20:49:59 +0200
Links: << >>  << T >>  << A >>
hello,
me & my partner need to test this chip.

is there a systematic way of functional testing of an FPGA chip ?

we need to test xilinx's virtex II Pro, and so far we have reached to the
point where we know its general structure,
but how fully is the control of place & route for such a complex device ?

how much area should we use in order to say -
"this is good enough for me" ?
(how do i qualify  "goodness" ?)

we also understand we probably cannot test it in one "burn", and it will
have to perform repeating tests of each logical/communication device in
separate runs.

is there a point of trying to find out a way to test the chip in 1
complicated "go" ?

another issue:
is there any PowerPC 405 functionality test available on WWW somewhere ?

thanks in advance.

Max & Mati




Article: 49307
Subject: Re: functional test for Xilinx virtex II Pro
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Nov 2002 11:21:35 -0800
Links: << >>  << T >>  << A >>
Max, why do you want to test the chip yourself ? Xilinx has done that for
you, throwing millions of test vectors at the chip. Test development is a
major, major design effort, and I do not understand why you want to
duplicate it. Do like all other customers, trust us...:-)
BTW, would you ever consider testing a Pentium chip???

Peter Alfke, Xilinx Applications
===========================
"Max K." wrote:

> hello,
> me & my partner need to test this chip.
>
> is there a systematic way of functional testing of an FPGA chip ?
>
> we need to test xilinx's virtex II Pro, and so far we have reached to the
> point where we know its general structure,
> but how fully is the control of place & route for such a complex device ?
>
> how much area should we use in order to say -
> "this is good enough for me" ?
> (how do i qualify  "goodness" ?)
>
> we also understand we probably cannot test it in one "burn", and it will
> have to perform repeating tests of each logical/communication device in
> separate runs.
>
> is there a point of trying to find out a way to test the chip in 1
> complicated "go" ?
>
> another issue:
> is there any PowerPC 405 functionality test available on WWW somewhere ?
>
> thanks in advance.
>
> Max & Mati


Article: 49308
Subject: Re: functional test for Xilinx virtex II Pro
From: "Max K." <skmax@t2.technion.ac.il>
Date: Fri, 8 Nov 2002 21:53:56 +0200
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter@xilinx.com> wrote in message
news:3DCC0EBF.1B2C826B@xilinx.com...
> Max, why do you want to test the chip yourself ? Xilinx has done that for
> you, throwing millions of test vectors at the chip. Test development is a
> major, major design effort, and I do not understand why you want to
> duplicate it. Do like all other customers, trust us...:-)
i don't need to know that the chip works in normal conditions.
(i really trust this)
our test will be ran under different conditions, thus testing certain
technology limits.
(radiation, accelleration, temperature etc.)
besides, there's a certain probability of fault delivery/handling between
Xilinx test stage
and our usage stage.
so inspite factory tests, you must see the chip bares the conditions you
need it to bare.
(before making a big effort on designing a machine based on it)

don't you agreee with this approach?

> BTW, would you ever consider testing a Pentium chip???
>
> Peter Alfke, Xilinx Applications
> ===========================




Article: 49309
Subject: Re: functional test for Xilinx virtex II Pro
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 08 Nov 2002 12:34:22 -0800
Links: << >>  << T >>  << A >>
Max, if you want to test some specific parameter (SEU, high-temp operation,
radiation effects, etc), then just design a specific test circuit. But do not
try to test the functionality and performance of the whole chip.
My old question: What would you do with a Pentium ?
An FPGA has an advantage over the Pentium: You can reconfigure it many ways,
and you can thus isolate practically any parameter you want.
But the first thing is to know what you are after... "Everything" is not a
good answer.

Peter Alfke
===================
"Max K." wrote:

> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3DCC0EBF.1B2C826B@xilinx.com...
> > Max, why do you want to test the chip yourself ? Xilinx has done that for
> > you, throwing millions of test vectors at the chip. Test development is a
> > major, major design effort, and I do not understand why you want to
> > duplicate it. Do like all other customers, trust us...:-)
> i don't need to know that the chip works in normal conditions.
> (i really trust this)
> our test will be ran under different conditions, thus testing certain
> technology limits.
> (radiation, accelleration, temperature etc.)
> besides, there's a certain probability of fault delivery/handling between
> Xilinx test stage
> and our usage stage.
> so inspite factory tests, you must see the chip bares the conditions you
> need it to bare.
> (before making a big effort on designing a machine based on it)
>
> don't you agreee with this approach?
>
> > BTW, would you ever consider testing a Pentium chip???
> >
> > Peter Alfke, Xilinx Applications
> > ===========================


Article: 49310
Subject: Spartan I with ISE Webpack
From: "Saffary" <a.saffary@wanadoo.fr>
Date: Fri, 8 Nov 2002 22:48:43 +0100
Links: << >>  << T >>  << A >>
Hi there

If somebody know, if i can use spartan(1) chips with ISE WebPack?.

Thanks



Article: 49311
Subject: Pros and Cons of using Xilinx CoreGen components
From: amyks@sgi.com (Amy Mitby)
Date: 8 Nov 2002 14:03:59 -0800
Links: << >>  << T >>  << A >>
I'd like answers to the following questions:

1) Are there significant benefits (in terms of resource 
   use and performance, not just saving time) to using some
   of Xilinx's Core Gen components, or are they not much
   better than a hand-design?

2) Have there been a lot of problems with buggy cores, or
   cores that cause resource issues (timing / area conflicts),
   etc?

3) Are there certain cores that you would recommend absolutely
   not using (bad experiences), or some that are particularly good?

4) Have there been any problems in using cores when migrating to
   different Xilinx tool versions?

Article: 49312
Subject: Spartan I with ISE Webpack
From: "Saffary" <a.saffary@wanadoo.fr>
Date: Fri, 8 Nov 2002 23:08:12 +0100
Links: << >>  << T >>  << A >>
Hi there

If somebody know, if i can use spartan(1) chips with ISE WebPack?.

Thanks




Article: 49313
Subject: Re: Spartan I with ISE Webpack
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 8 Nov 2002 23:18:00 +0100
Links: << >>  << T >>  << A >>
"Saffary" <a.saffary@wanadoo.fr> schrieb im Newsbeitrag
news:aqhcgm$hac$1@news-reader10.wanadoo.fr...
> Hi there
>
> If somebody know, if i can use spartan(1) chips with ISE WebPack?.

Someone said that that there is some kind of legacy pack for webpack, which
allows the development of 4K,Spartan and SpartanXL.

--
MfG
Falk





Article: 49314
Subject: External memory or on-chip?
From: lmicken@eng.morgan.edu (lpm)
Date: 8 Nov 2002 14:21:14 -0800
Links: << >>  << T >>  << A >>
Hello all,

I'm graduate student (and a FPGA newbie) designing a image processing
system using a Spartan-II FPGA and have a question regarding where I
should store the images that I'll be processing. Should I use an off
board memory chip, and if so what's the best way to interface to it?
Or, should I just store the image on the FPGA? Thanks for any
assistance.

-Lisa

Article: 49315
Subject: Re: Pros and Cons of using Xilinx CoreGen components
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Fri, 08 Nov 2002 14:59:58 -0800
Links: << >>  << T >>  << A >>
Amy Mitby wrote:


> 1) Are there significant benefits (in terms of resource 
>    use and performance, not just saving time) to using some
>    of Xilinx's Core Gen components, or are they not much
>    better than a hand-design?


A core gen is likely to have optimum resource usage.
It will save you time only if you can't afford or
don't know how to infer the same structures using hdl synthesis.
It will complicate simulation and design clarity.

Your own hand-design will have the advantage
of being portable, changeable and copyrightable.


>
> 2) Have there been a lot of problems with buggy cores, or
>    cores that cause resource issues (timing / area conflicts),
>    etc?


Not that I know of.


> 3) Are there certain cores that you would recommend absolutely
>    not using (bad experiences), or some that are particularly good?


Consider not using simple cores like shifters, counters, roms etc.,
just because inferred versions work fine and are much easier to code and sim.


> 
> 4) Have there been any problems in using cores when migrating to
>    different Xilinx tool versions?


I would expect that there are some device-specific limitations.
The migration to worry about is to an ASIC or to brand A because
you have no right to any part of the core design in other devices.

  -- Mike Treseler






Article: 49316
Subject: Re: BUFT bus contention
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Sat, 09 Nov 2002 01:49:23 GMT
Links: << >>  << T >>  << A >>
hiro wrote:

>   Next, aftre re-assigning '1' and '0' to ctrl1 and ctrl2 simutaneously,
>   the circuit transition may also start simutaneously.
>   At this time, does bus contention occur on data_bus and hence
>   any damages to device?


BUFT's are not really bidirectional buffers.  As the data sheet says:

http://direct.xilinx.com/bvdocs/publications/ds031-2.pdf

(Page 21)
"The 3-state buffer logic is implemented using AND-OR logic
rather than 3-state drivers, so that timing is more predictable
and less load dependant especially with larger devices."


-- 
Phil Hays

Article: 49317
Subject: Re: functional test for Xilinx virtex II Pro
From: rk <stellare@NOSPAMPLEASE.erols.com>
Date: 9 Nov 2002 02:00:38 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

         [ snip ]

>                                               Do like all other
> customers, trust us...:-) BTW, would you ever consider testing a
> Pentium chip??? 

Couldn't resist:

   http://www.ku.edu/cwis/units/IPPBR/pentium_fdiv/pentgrph.html

Now back to our regularly scheduled program.

-- 
rk, Just an OldEngineer
"A good engineer gets stale very fast if he doesn't keep his hands 
dirty."  -- Wernher von Braun, 1964 


Article: 49318
Subject: Re: External memory or on-chip?
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Sat, 09 Nov 2002 02:23:54 GMT
Links: << >>  << T >>  << A >>
lpm wrote:

> I'm graduate student (and a FPGA newbie) designing a image processing
> system using a Spartan-II FPGA and have a question regarding where I
> should store the images that I'll be processing. Should I use an off
> board memory chip, and if so what's the best way to interface to it?
> Or, should I just store the image on the FPGA? Thanks for any
> assistance.

How big is your image?  If it fits into the FPGA memory (read the data
sheet), and you have no other uses for that memory, use the FPGA memory
as it will be faster and easier.  If it doesn't, synchronous static RAM
(SSRAM) is fast and fairly easy to interface to, but is limited in
size.  SDRAM is larger, has higher latency and is much more complex. 
DDR SDRAM and Disks and flash memories are probably not of interest.

Did this help?


-- 
Phil Hays

Article: 49319
Subject: Has anyone tried Lattice's chips?
From: Altogether_Andrews <juglugs@hotmail.com>
Date: Sat, 09 Nov 2002 02:43:10 GMT
Links: << >>  << T >>  << A >>
Lattice seem to have the best SERDES, and don't try to hide behind the 
Marketroid BS like others do.

Altera's GX seems close, but no cigar...


-- 
"There are 10 types of people in the world - Those who understand binary, 
and those who don't"

Article: 49320
Subject: Re: functional test for Xilinx virtex II Pro
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Sat, 09 Nov 2002 02:59:26 GMT
Links: << >>  << T >>  << A >>
"Max K." wrote:

> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3DCC0EBF.1B2C826B@xilinx.com...
> > Max, why do you want to test the chip yourself ? Xilinx has done that for
> > you, throwing millions of test vectors at the chip. Test development is a
> > major, major design effort, and I do not understand why you want to
> > duplicate it. Do like all other customers, trust us...:-)
> i don't need to know that the chip works in normal conditions.
> (i really trust this)
> our test will be ran under different conditions, thus testing certain
> technology limits.
> (radiation, accelleration, temperature etc.)
> besides, there's a certain probability of fault delivery/handling between
> Xilinx test stage
> and our usage stage.

Max, I've heard that Xilinx used to offer for an older FPGA family,
under NDA, a limited set of test vectors that could be run over JTAG. 
There were a subset of the vectors Xilinx used to test these parts in
the factory.  These vectors would not test for performance (that's
really very hard), and didn't do a full functional test (that's also
really very hard).  Your best bet to get use of something like this, if
they exist for your part, is to talk to your local Xilinx FAE.  BTW:
Most handling problems are gross damage (look for shorts or opens on the
pins, and visually look for big holes or cracks in the package), or are
due to electric static discharge or ESD (can very hard to find, even
with fancy test equipment), so I wouldn't suggest using test vectors to
find handling problems.


> so inspite factory tests, you must see the chip bares the conditions you
> need it to bare.
> (before making a big effort on designing a machine based on it)
> 
> don't you agreee with this approach?
> 
> > BTW, would you ever consider testing a Pentium chip???

Peter, it would depend on how much I needed to trust the answer from a
divide (-;).  For most purposes Intel does just fine, as does Xilinx.  A
few people may well have a real need for more, or for verification that
something awful didn't happen, or that something awful doesn't happen in
a "beyond data sheet" type environment.


-- 
Phil Hays

Article: 49321
Subject: Re: functional test for Xilinx virtex II Pro
From: Altogether_Andrews <juglugs@hotmail.com>
Date: Sat, 09 Nov 2002 03:05:07 GMT
Links: << >>  << T >>  << A >>
Max K. wrote:

> 
> "Peter Alfke" <peter@xilinx.com> wrote in message
> news:3DCC0EBF.1B2C826B@xilinx.com...
>> Max, why do you want to test the chip yourself ? Xilinx has done that for
>> you, throwing millions of test vectors at the chip.
> 
> ok, "test vectors" will be checked.
> 
>>Test development is a
>> major, major design effort, and I do not understand why you want to
>> duplicate it. Do like all other customers, trust us...:-)
> 
> i have no problem with this.
> where can i find more info on "test vectors" ?
> (i have all the available pdfs)
> 
>> BTW, would you ever consider testing a Pentium chip???
> i would, if it were my project's goal  :-)
>>
>> Peter Alfke, Xilinx Applications
>> ===========================
>> "Max K." wrote:
>>
>> > hello,
>> > me & my partner need to test this chip.
>> >
>> > is there a systematic way of functional testing of an FPGA chip ?
>> >
>> > we need to test xilinx's virtex II Pro, and so far we have reached to
> the
>> > point where we know its general structure,
>> > but how fully is the control of place & route for such a complex device
> ?
>> >
>> > how much area should we use in order to say -
>> > "this is good enough for me" ?
>> > (how do i qualify  "goodness" ?)
>> >
>> > we also understand we probably cannot test it in one "burn", and it
>> > will have to perform repeating tests of each logical/communication
>> > device in separate runs.
>> >
>> > is there a point of trying to find out a way to test the chip in 1
>> > complicated "go" ?
>> >
>> > another issue:
>> > is there any PowerPC 405 functionality test available on WWW somewhere
>> > ?
>> >
>> > thanks in advance.
>> >
>> > Max & Mati
>>

Max,

With FPGA's there's a disadvantage - They are programmable, so how do you 
test every possible configuration?

Unfortunatley you are going to have to develop some IP that will be 
intensive for every block within the device - the memory, the SERDES, the 
LUTs, the I/O's etc, etc.

You can't trust marketroids (marketing folk) as their bound to present the 
best case senarios and say things like " trust us...:-)"

But then, you can work around this - Ask them for their Environmental Test 
Plan - this will show what they are compliant to for a batch of devices - I 
doubt if Radiation or Acceleration immunity have been tested, but the 
temperature/humidity type stuff will be.

BTW - If you do develop a representative IP core, a) sell it to Xilinx and 
b) try testing it to MIL-STD-810E (The military environmental standard)


-- 
"There are 10 types of people in the world - Those who understand binary, 
and those who don't"

Article: 49322
Subject: Re: glue logic device
From: Altogether_Andrews <juglugs@hotmail.com>
Date: Sat, 09 Nov 2002 03:43:16 GMT
Links: << >>  << T >>  << A >>
hristo wrote:

> Many thanks Tullio for the answer
> could you please highlight one of this functionalities. was it used
> for routing or reconfiguration, and why FPGA?
> 
> thanks
> Tullio Grassi <tullio@physics.umd.edu> wrote in message
> news:<3DC9AF0E.508F0411@physics.umd.edu>...
>> hristo wrote:
>> > 
>> > hello,
>> > i often go through this expression, but never see what it means
>> > any explanations
>> > thanks
>> 
>> More or less it's a jargon to indicate a device that does not perform
>> any central function, but simply is a bridge to interface between more
>> powerful subsystems (CPU, DSP, ASIC, etc).
>> In the old days this was one of the main use of FPGAs.
>> 
>> --
>> 
>> Tullio Grassi
>> 
>> ======================================
>> Univ. of Maryland - Dept. of Physics
>> College Park, MD 20742 - US
>> Tel +1 301 405 5970
>> Fax +1 301 699 9195
>> ======================================

Hi hristo,

Not sure about Roland's explanation...

Tullio is correct...

It is exactly what is says - it is the glue, or adhesive (not sure what the 
term you use in your language is) that bonds two logic entities together. 
For example, if you have a POS-PHY interface on one device, and a PL-3 
interface on the other, the 'glue logic' would provide the adapter betwen 
the two.

FPGA's are ideal as they enable the user to design the right 'glue logic' 
for their application, and as standard's change (as they invariably do in 
Comms) you can adapt to keep your system current.

The best FPGA's are those who supprt the highest range of I/O standards - 
try Lattices's range - http://www.latticesemi.com/products/fpga/index.cfm

Also, in today's market, FPGA vendors are implementing 'hard' IP for 
specific functions or standards, and again, I'd recommend Lattice's FPSC's



-- 
"There are 10 types of people in the world - Those who understand binary, 
and those who don't"

Article: 49323
Subject: Re: 250MHz Data Bus connected directly to Xilinx Virtex-II
From: Altogether_Andrews <juglugs@hotmail.com>
Date: Sat, 09 Nov 2002 03:54:17 GMT
Links: << >>  << T >>  << A >>
Song Qian wrote:

> Hi, everyone
> 
> I want to connect a 300MHz data bus directly to Xilinx Virtex-II FPGA,
> but I am not very sure about the stability. Is here anybody who have
> done it before? I plan to store the datas into FIFOs in FPGA, generated
> from dual-port BlockRAM. The timing seems very tight, and would you
> point out whether it is worth my effort? Or should I just use a external
> demux logic to half the data rate? Welcome all comments.
> 
> Song Qian

Use one of the Lattice devices

-- 
"There are 10 types of people in the world - Those who understand binary, 
and those who don't"

Article: 49324
Subject: Re: Instruction sets to implement instruction sets
From: "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com>
Date: Sat, 9 Nov 2002 17:43:35 +1300
Links: << >>  << T >>  << A >>
"emanuel stiebler" <emu@ecubics.com> wrote in message
news:3DCAB8BC.4030909@ecubics.com...
> Peter Alfke wrote:

> > It's called BIT-SLICE Microprocessor Design by Mick and Brick
> > published by McGraw Hill , ISBN 0-07-041781-4 in 1980
> >
> > also you might want to look at Bit Slice Design:Controllers and ALU's
> > by Donnamaie E. White ISBN 0-8240-7103-4 ( known as the white book ! )
>
> And if you really don't have it in your bookshelf, at least the second
> one is online. Just google around for Donnamaies webpage.

Thanks for the pointer, lead me to this

http://www10.dacafe.com/book/parse_book.php?article=BITSLICE/index.html

This is exactly the kind of stuff I was looking for.  Very useful in a fgpa
with lots of block ram.

Is this the way most CISC is implemented?

Now off to hook up a array of 40 PROM ;-)

Ralph






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