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Messages from 51500

Article: 51500
Subject: How to add pins in ISE 4.2
From: Kuan Zhou <zhouk@rpi.edu>
Date: Tue, 14 Jan 2003 21:16:41 -0500
Links: << >>  << T >>  << A >>
Hi,
   I am using ISE 4.2 student version.But I can not find output pad in the 
schematic tools.Does any one know how to add pins in the schematic design?
The help says you can find "add pins" from the Add menu,but I can not find
it.

   Thank you very much!

sincerely
-------------
Kuan Zhou
ECSE department



Article: 51501
Subject: Re: SChematic design approach compared to VHDL entry approach
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Tue, 14 Jan 2003 21:27:19 -0500
Links: << >>  << T >>  << A >>
Keith,

> > Well, it depends.  If you have a schematic library that allows you to
draw a
> > flow diagram and makes it drag and drop, it's REALLY easy...and easy to
> > do...and easy to read.
>
> Doesn't that make it more of an HDL rather than schematic?

How?  There's no HDL involved at all.  Symply schematic blocks and symbols.

> There is
> some "synthesis" going on then.  Perhaps I don't understand your tool.

There is no synthesis.  Simply hierarchical symbols, and underneath those
symbols are schematics, or other blocks.  The very bottom level is gates,
but above that, it's functional blocks.  Like a single symbol for a counter,
or a single symbol for a CRC generator...

> > > The design is simply too large
> > > to make it practical though.
>
> I believe that generating schematics from this VHDL would be
> impractical.

Ah, yes.  I understood that to mean that using schematics FOR that design
was impractical because of the size of the design.

> > > Again, schematics are nice for dataflow.  I very much dislike
> > > schematics for state machines.
> >
> > It depends on how it's drawn.  Any tool can be abused, or used properly.
> > Fought with, or worked with.
>
> Very true.  I'd like to learn some of the tools you work with.  Perhaps
> I'd be an easy convert.

As Ray, Philip and other use, I use ViewDraw, with a symbol library that
I've managed to accumulate over the past 10+ years.  It is unfortunate that
schematics have been pretty much supplanted as the tool of choice, because
there is really no incentive for people to sell/releast/provide these symbol
libraries.  All of us who have been doing this for a while, have amassed a
large arsenal of symbols.  Philip even had a very excellent state machine
generator and function generator that would make your symbols, and the
underlying, schematics for you for a list of different functions.

> > Er, yeah.  That's why the fast PCI cores are done in schematics ;-)
>
> PCI is fast?!

In a 4k, getting it to run at 33MHz is fast, and getting PCI-X to run at
133MHz is fast as well.  So, yes, PCI IS fast.

> > > I'll dissent here.  Documentation means something.  My comfort
> > > isn't everything.
> >
> > Hum.  I think we strap you to a chair, and make you drink four 2L
bottles of
> > Diet Coke and see you say that after a few hours...
>
> Gee, you work in a nice relaxed atmosphere. I could get to enjoy such
> enlightened management. ;-)

Why, thank you ;-)

> Again, I'd like to see your schematics.  I'm always open to new ways of
> doing things. I get bored with the old ones. ;-)

Ha ha...schematics ARE the old way.

> > Well, then...DON'T USE ORDAD!
>
> Ordad? Tell us how you really feel! Don't hold it in!

I can't believe that they actually have the nerve to charge for such a gross
schematic package...as $9.99 shareware, it's pretty good, but as a real
schematic tool, it just doesn't work well.  The PCB tools are excellent
though...which I find kind of funny.

>One of the best decisions I made was to go
> with the Synplicity tools.

Yes, they, specifically, have come a LONG way and as far as for FPGA use,
are exceptional, especially with the RTL viewer.  I am very happy with
Synplicity.

Regards,

Austin



Article: 51502
Subject: Re: SChematic design approach compared to VHDL entry approach
From: Phil Hays <SpamPostmaster@attbi.com>
Date: Wed, 15 Jan 2003 02:49:18 GMT
Links: << >>  << T >>  << A >>
Michael S wrote:
 
> Basically, schematic entry tools are still in use only because people
> without a software background are still allowed into a FPGA design
> field. The day management will finally realize how much money can be
> saved by keeping these people (a.k.a. hardware engineers) out of all
> but the simplest FPGA designs - the time of the schematics will be
> over.
> These HW guys can't spell "version control" !!! Enough said.

I'm a "HW guy" that thinks in both code and in the physical layout,
rather than visual gates (schematics).  I have found it easier to teach
HW types to use VHDL and put code into CVS than to teach SW types why
the output enable FF needs to be in the IOB, and how to code to get this
to happen.  Not to mention how to do a reasonable data paths, or how to
parallelize tasks and pipeline a design.

I've only been working with FPGAs for eleven years or so.  Austin must
be getting close to the fifteen year point.  But I'm sure you know
more.  So educate us.


-- 
Phil Hays

Article: 51503
Subject: Re: Open FPGA please!
From: Ray Andraka <ray@andraka.com>
Date: Wed, 15 Jan 2003 03:09:07 GMT
Links: << >>  << T >>  << A >>


Steve Lass wrote:

> I'll need some more info on this.  Did the design meet timing?  That is the
> goal of our tools, not getting the best route for each net.

Problem is for dense designs, the route strategy used in 4.x and 5.1 tools falls short.
The older router did a much better job of getting nearly best routes, especially on
floorplanned data path.  The new router makes circuitous routes on signals that should be
straight connections, and as a result it is difficult or impossible to predict the
critical path.  Paths that should have plenty of margin often come up with only a few ns
slack.  While the average user who is not pushing speed or density probably doesn't care
(even he might if he realized how much the power consumption is affected), the power user,
especially one who is trying to put out IP guaranteed to run at a particular clock, gets
very frustrated with this.  There needs to be a switch to offer a routing algorithm
similar to what was done in 3.3 and earlier tools.  I have several designs that met timing
under 3.3 but fall short under later tools, and it is a routing problem as these are
extensively floorplanned designs.  With power becoming a persistent problem, I think
getting near optimal routing on every net is even more important.  It wouldn't be as much
of  thorn if it had never been done, but the fact of the matter is that the 3.3 router is
a better router for heavily floorplanned data path designs.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 51504
Subject: Re: Open FPGA please!
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Tue, 14 Jan 2003 22:34:14 -0500
Links: << >>  << T >>  << A >>
On Sun, 12 Jan 2003 06:03:17 -0500, Andrew Rogers wrote:

> It would seem that the Open Source software developers haven't quite
> managed to produce a complete tool chain for programming FPGAs. The
> remaining issue seems to be that FPGA manufactures are not willing to
> supply the necessary bit-stream specification and make excuses, giving
> the details of the bit-stream would allow reverse engineering of
> commercial products that use their FPGAs. That's probably true, but any
> one wishing to clone such a product only has to duplicate the bit-stream
> and no reverse engineering is required.
> 
> If FPGA manufactures continue this ridiculous trend then maybe the only
> option is to develop a new FPGA which has all of its specifications
> available.
> 
> I know that this issue has been raised in the past, but this time I am
> following up a different approach, the development of an Open FPGA.
> 
> Can anyone (Xilinx maybe) estimate the cost and time involved in
> development of a new and open FPGA?
> 
> Maybe I could test out the new Open FPGA with my University Ph.D. work
> on Turbo codecs!
> 
> Thanks
> Andrew Rogers
 
In my experience Xilinx is very forthcoming with technical details, you
just have to know who to ask. As for the idea of an open source FPGA,
that's just silly. Open source software is feasible because there aren't
any capital requirements, just the willingness of programmers to spend
time on the project. ASICs are a completely different story, a single .13u
mask set costs in the neighborhood of half a million dollars, no one is
going to make that kind of investment in something that has no pay off.
Also there isn't the same kind of need for alternative FPGA sources. The
FPGA world is blessed with two nearly equal sized competitors who have
been going at it tooth and nail since their foundings. Real competition
makes for real advancements, and more importantly it prevents the
competitors from exploiting their customers. That's very different from
the OS world where Microsoft has had a monopoly. The lack of competition
has allowed Microsoft to get away with selling Soviet quality software.
Linux has been able to snatch significant market share because the world
desparately needed a high quality alternative, and more crucially there
is no one company that Microsoft can put out of business which would kill
off Linux.

Article: 51505
Subject: Re: Simulate Virtex Primitive using ModelSim
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 15 Jan 2003 04:36:52 GMT
Links: << >>  << T >>  << A >>
On Tue, 14 Jan 2003 17:23:53 GMT, Ken McElvain <ken@synplicity.com>
wrote:

>library unisim;
>use unisim.vcomponents.all;
>
>Is supported in Synplify after 7.2.1

FYI, this also worked in versions prior to 7.2.1 if you compiled
unisim_vcomp.vhd into the unisim library.

My Synplify project files now contain something similar to:

if {([llength [info commands program_version]] && ([program_version]
>= 7.2))} {
    # using a version of synplify that has unisim built-in
} else {
    # using a version of synplify that doesn't have unisim built-in
    add_file -vhdl -lib unisim <somepath>/unisim_vcomp.vhd;
}


Regards,
Allan.


>- Ken McElvain
>
>
>Barry Brown wrote:
>
>> 1. You have to compile the xilinx unisim library in Modelsim.  Check the
>> Xilinx answers database for record #2561.  I had to do this, but I cannot
>> remember the exact commands I used in Modelsim (wish I had written them
>> down!).  I do remember that Xilinx's TCL script did not work for me.  The
>> Xilinx source is in your directory $Xilinx\vhdl\src\unisims.  I also just
>> noticed that they include a perl script in  $Xilinx\vhdl\bin\nt which
>> purports to compile the libraries.  Could be worth a try if you have perl
>> installed.
>> 
>> 2. Modify your modelsim.ini file to include lines like these:
>> simprim = $MODEL_TECH/../simprim
>> unisim = $MODEL_TECH/../unisim
>> 
>> 3. Include the library in your source file:
>> -- synthesis translate_off
>> library unisim;
>> use unisim.vcomponents.all;
>> -- synthesis translate_on
>> 
>> Those pragmas are for Synplify.
>> 
>> Note: my computer is running pathetic ol' NT4, so the directory paths I have
>> given may not be exactly the same on your computer.
>> 
>> Barry Brown
>> 
>> 
>> "Jim Raynor" <chris_cheung66@hotmail.com> wrote in message
>> news:JfDU9.24993$8V5.2262500@news1.telusplanet.net...
>> 
>>>hi,
>>>
>>>    I am having problem in simulating the Virtex's Primitive (e.g CLKDLL,
>>>BUFG...) using Modelsim.  Could anyone tell me how to do it?  I got errors
>>>in the Modelsim like
>>>
>>>    # WARNING[1]: main.vhd(244): No default binding for component:
>>>
>> "ibufg".
>> 
>>>(No entity named "ibufg" was found)
>>># WARNING[1]: main.vhd(247): No default binding for component: "clkdll".
>>>
>> (No
>> 
>>>entity named "clkdll" was found)
>>># WARNING[1]: main.vhd(248): No default binding for component: "bufg". (No
>>>entity named "bufg" was found)
>>>
>>>    Thanks.....
>>>
>>>    Chris
>>>
>>>
>>>
>>>
>> 
>> 
>


Article: 51506
Subject: Re: SChematic design approach compared to VHDL entry approach
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Wed, 15 Jan 2003 00:15:18 -0500
Links: << >>  << T >>  << A >>

"Tim" <tim@rockylogic.com.nooospam.com> wrote in message
news:b028d5$ag5$1$8300dec7@news.demon.co.uk...
> Austin Franklin wrote
> > For most designs, it is better to simply use what you are most
comfortable
> > with.  As with any thing engineering, any tool can be used exceptionally
as
> > well as poorly.
>
> I can see how you can mimic the functionality of a schematic
> in a programming language.  But the other way round seems tough.

Hi Tim,

If I understand what you mean...I can tell you that I USED to get a LOT of
jobs doing exactly that...taking VHDL and converting it to schematics.

Up until about five years ago, people were told that HDLs were what they
should be using for FPGA designs, but the recommending party failed to tell
their unsuspecting clients that the most they could get out of synthesis was
about 5MHz...so they needed a quick solution.  Sometimes that was looking at
the design using FPGA Editor and finding out what was causing the problem,
and then simply re-writing the HDL, after hours of playing guessing games as
to what syntax would create what output...to get the HDL to "work" as it
simply should have in the first place.

The other solution was to take the VHDL and implement it in schematics.  The
later was actually done FAR more than the former.  So, yes, I have taken a
LOT of VHDL and implemented it in schematics, only to make give the client a
design that ran vastly faster than the HDL, in a slower speed grade, and
used far less resources, so they could use smaller, cheaper, chips.

Regards,

Austin



Article: 51507
Subject: Re: Spartan II found on Ebay
From: "Austin Franklin" <austin@da98rkroom.com>
Date: Wed, 15 Jan 2003 00:20:39 -0500
Links: << >>  << T >>  << A >>
Yeah, but the starting price is $10k...so it doesn't seem like much of a
bargain!

"Emile" <banktrade2002@yahoo.com> wrote in message
news:952209fb.0301141312.5b347ad3@posting.google.com...
> There is a listing for 360 new XC2S150-5FG456C on Ebay - I think that
> someone here posted a message asking for some.



Article: 51508
Subject: Re: Spartan II found on Ebay
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Wed, 15 Jan 2003 05:58:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <v29rt7d7v0qnbf@corp.supernews.com>,
Austin Franklin <austin@da98rkroom.com> wrote:
>Yeah, but the starting price is $10k...so it doesn't seem like much of a
>bargain!

Actually, seems quite cruddy.  300 is enough to start getting
interesting, at 10,000 Xilinx will probably sell em for <$10 each.

>"Emile" <banktrade2002@yahoo.com> wrote in message
>news:952209fb.0301141312.5b347ad3@posting.google.com...
>> There is a listing for 360 new XC2S150-5FG456C on Ebay - I think that
>> someone here posted a message asking for some.
>
>


-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 51509
Subject: Re: SChematic design approach compared to VHDL entry approach
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Wed, 15 Jan 2003 07:02:32 +0100
Links: << >>  << T >>  << A >>
Michael S wrote:
> Basically, schematic entry tools are still in use only because people
> without a software background are still allowed into a FPGA design
> field. The day management will finally realize how much money can be
> saved by keeping these people (a.k.a. hardware engineers) out of all
> but the simplest FPGA designs - the time of the schematics will be
> over.
> These HW guys can't spell "version control" !!! Enough said.
> 

Interesting.
I'm doing mixed stuff. Microcontrollers, Analog & RF, Windows GUIs,
and FPGAs. I'm quite capable of several ASM and highlevel languages.
Yet, I wasn't convinced to learn another language for my FPGAs.
As long as the schematic approach works, why bother.
It might happen one day when there is an advantage, though.

I'd rather consider the fast FPGAs given to software people to be
'pearls before pigs'. If you havent spent weeks on tweaking
nanoseconds on ECL, you aren't worth the FPGAs.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 51510
Subject: Re: SChematic design approach compared to VHDL entry approach
From: Spam Hater <spam_hater_7@email.com>
Date: Wed, 15 Jan 2003 08:03:00 GMT
Links: << >>  << T >>  << A >>

I don't doubt you for a second. 

There's a thread in 'comp.arch.embedded' about low quality software.

Just as a Language Reference Manual won't make you a C programmer, it
won't make you a HDL designer.

$.02,
SH

On Wed, 15 Jan 2003 00:15:18 -0500, "Austin Franklin"
<austin@da98rkroom.com> wrote:

>
>The other solution was to take the VHDL and implement it in schematics.  The
>later was actually done FAR more than the former.  So, yes, I have taken a
>LOT of VHDL and implemented it in schematics, only to make give the client a
>design that ran vastly faster than the HDL, in a slower speed grade, and
>used far less resources, so they could use smaller, cheaper, chips.
>
>Regards,
>
>Austin
>


Article: 51511
Subject: Re: Open FPGA please!
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 15 Jan 2003 21:04:30 +1300
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Steve Lass wrote:
> 
> > I'll need some more info on this.  Did the design meet timing?  That is the
> > goal of our tools, not getting the best route for each net.
> 
> Problem is for dense designs, the route strategy used in 4.x and 5.1 tools falls short.
> The older router did a much better job of getting nearly best routes, especially on
> floorplanned data path.  The new router makes circuitous routes on signals that should be
> straight connections, and as a result it is difficult or impossible to predict the
> critical path.  Paths that should have plenty of margin often come up with only a few ns
> slack.  While the average user who is not pushing speed or density probably doesn't care
> (even he might if he realized how much the power consumption is affected), the power user,
> especially one who is trying to put out IP guaranteed to run at a particular clock, gets
> very frustrated with this.  There needs to be a switch to offer a routing algorithm
> similar to what was done in 3.3 and earlier tools.  I have several designs that met timing
> under 3.3 but fall short under later tools, and it is a routing problem as these are
> extensively floorplanned designs.  With power becoming a persistent problem, I think
> getting near optimal routing on every net is even more important.  It wouldn't be as much
> of  thorn if it had never been done, but the fact of the matter is that the 3.3 router is
> a better router for heavily floorplanned data path designs.

 Since a 'heavily floorplanned designs' has most of placement the work
done,
one could expect the routers to finish much faster.

 Do you see much difference in the completion times of the 3.3 tools, vs
5.1 tools ?

 It's a common problem, supposedly smarter tools being harder to
control, and/or
giving dumber results..

-jg

Article: 51512
Subject: Re: filter coefficient multiplication in vhdl
From: Ken Chapman <chapman@xilinx.com>
Date: Wed, 15 Jan 2003 10:15:28 +0000
Links: << >>  << T >>  << A >>

Dear David,

I think you would find the Xilinx DSP Techniques Course most useful and
interesting. All of module 2 (there are 7 modules in 3 days) is devoted to
understanding different ways to represent numbers and how to make correct
decisions about required precision.

Of course, I'm biased because I wrote it! However, I have personally taught it
to hundreds of people and the feedback has been excellent, albeit that most of
them complain that they have a headache!

Have a look at the course description and see if it is running near you soon.

http://support.xilinx.com/support/training/abstracts/v4/atp-dsp.htm

For a quick understanding of number representation take a look at my TechX
article.

http://www.xilinx.com/support/techxclusives/DCoffset1-1-techX14.htm

Yours sincerely,

Ken Chapman




Article: 51513
Subject: what is a Systolic Array
From: "Skillwood" <skillwood@hotmail.com>
Date: Wed, 15 Jan 2003 16:46:50 +0530
Links: << >>  << T >>  << A >>
HI all,
 Can anyone tell me  what is a systolic array . My idea is that it is a
array of computing elements used for complex applications.

CAN any one give me more details??
Also any lnks, whitepapers


Thanks in Advance
Skillie



Article: 51514
Subject: Short FIFO in Verilog / Spartan IIE
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Wed, 15 Jan 2003 12:46:05 +0100
Links: << >>  << T >>  << A >>
I'm working on a digital oversampling filter where I need some really small
FIFOs (2 to 16 words long). The width is 16 to 24 bits.

What is the recommended way to implement such FIFOs in a Spartan IIE? I will
probably need at least 8 of them. The FIFOs in the Core Generator are
generally longer that what I need. Latency is no problem in my design, and
the clock speed is rather low. Reads and writes to/from the FIFO will be
synchronous to the clock.

Any feedback wellcome!

Regards,

BÝrge



Article: 51515
Subject: Re: Student development board
From: "geeko" <jibin@ushustech.com>
Date: Wed, 15 Jan 2003 17:29:45 +0530
Links: << >>  << T >>  << A >>
Hi all
 I tried to procure the components for the Berkeley  board but failed
 Is this board is available in assembled form or as a kit with pcb and all
components

with regrds

"Austin Lesea" <austin.lesea@xilinx.com> wrote in message
news:3E1F0E35.D99D6FA0@xilinx.com...
> All,
>
> A very nice platform for FPGAs was developed by UC Berkeley (in
cooperation we
> Xilinx):
>
>  http://kamsky.eecs.berkeley.edu/calinx/pdf/Manual.pdf
>
> I would suggest you contact UCB, or myself, if you are interested in
making some
> for your school.
>
> There are many platforms that are much less capable, and perhaps any one
of
> those would be suitable for an introductory level course.  Please review:
>
>  http://www.xilinx.com/univ/index.htm
>
> Austin
>
> Rene Tschaggelar wrote:
>
> > David wrote:
> > > Hi,
> > > Does anyone know what is the best choice for an fpga developement kit?
> > > Altera offers this kit for University student :
> > > http://www.altera.com/education/univ/kits/unv-kits.html
> > > I wonder if there are other supplier of boards like this (could be
Xilinx
> > > too) that could compete with this. Are there third party manufacturer
that
> > > are worth considering?
> >
> > All these offers are comparable.
> > The software usually can be downloaded, at least reduced versions.
> > The programmers can be selfbuilt or purchased.
> > And finally you need some chip on a board.
> > While 150$ is not much you should base your preference based on
> > who is going to help you and who is going to introduce you into this
> > technology. A colleague is best as you'll spent a few feeks at least.
> >
> > Rene
> > --
> > Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> > & commercial newsgroups - http://www.talkto.net
>



Article: 51516
Subject: Re: Short FIFO in Verilog / Spartan IIE
From: Frank Hoffmann <fh215@xxx.cam.ac.uk>
Date: Wed, 15 Jan 2003 12:26:28 +0000
Links: << >>  << T >>  << A >>

Hi,

Ken Chapman's Picoblaze project and files (at Xilinx) contain a small 
and compact fifo (bbfifo_16x8). It stores max. 16 words, 8-bit wide, but 
the word width can be easily expanded to any width you want.

It is currently written in VHDL but since it is all instantiation of 
Xilinx primitives anyway, it's not too hard ('tho tedious) to transcribe.

- Frank

PS:
Replace 'xxx' with 'eng' to send no-spam email.



BÝrge Strand wrote:
> I'm working on a digital oversampling filter where I need some really small
> FIFOs (2 to 16 words long). The width is 16 to 24 bits.
> 
> What is the recommended way to implement such FIFOs in a Spartan IIE? I will
> probably need at least 8 of them. The FIFOs in the Core Generator are
> generally longer that what I need. Latency is no problem in my design, and
> the clock speed is rather low. Reads and writes to/from the FIFO will be
> synchronous to the clock.
> 
> Any feedback wellcome!
> 
> Regards,
> 
> BÝrge
> 
> 


Article: 51517
Subject: How can I use DCM to 1/24 freq-division?
From: Cisa <yxjiang2002@sina.com>
Date: Wed, 15 Jan 2003 05:01:23 -0800
Links: << >>  << T >>  << A >>
Now I have a clk whose frequency is 30.72,and I want to use DCM 
to generate another clk whose frequency is 1.28MHz. 
How can I get it?I failed  in reality.Pls give me some advance.

Article: 51518
Subject: Re: Short FIFO in Verilog / Spartan IIE
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Wed, 15 Jan 2003 14:54:31 +0100
Links: << >>  << T >>  << A >>
Thanks Frank!

I'll have a look at it tonight.

--
BÝrge

"Frank Hoffmann" <fh215@xxx.cam.ac.uk> wrote in message
news:b03jqt$a07$1@pegasus.csx.cam.ac.uk...
>
> Hi,
>
> Ken Chapman's Picoblaze project and files (at Xilinx) contain a small
> and compact fifo (bbfifo_16x8). It stores max. 16 words, 8-bit wide, but
> the word width can be easily expanded to any width you want.
>
> It is currently written in VHDL but since it is all instantiation of
> Xilinx primitives anyway, it's not too hard ('tho tedious) to transcribe.
>
> - Frank
>
> PS:
> Replace 'xxx' with 'eng' to send no-spam email.
>
>
>
> BÝrge Strand wrote:
> > I'm working on a digital oversampling filter where I need some really
small
> > FIFOs (2 to 16 words long). The width is 16 to 24 bits.
> >
> > What is the recommended way to implement such FIFOs in a Spartan IIE? I
will
> > probably need at least 8 of them. The FIFOs in the Core Generator are
> > generally longer that what I need. Latency is no problem in my design,
and
> > the clock speed is rather low. Reads and writes to/from the FIFO will be
> > synchronous to the clock.
> >
> > Any feedback wellcome!
> >
> > Regards,
> >
> > BÝrge
> >
> >
>



Article: 51519
Subject: Re: SChematic design approach compared to VHDL entry approach
From: ccon67@netscape.net (Marlboro)
Date: 15 Jan 2003 07:30:31 -0800
Links: << >>  << T >>  << A >>
Well, Im happy since there's still alot Schematic guys in this world.
Most of pure HDL guys now had entered the FPGA industry with no 
chance/success with schematic. Let ask some (few) HDL experts how they 
tackle a big-complex design?  I bet they will mention some kind of flow chart
or block diagram first.  Ah, what is that? A SCHEMATIC...

I think I have enough of silly words ( HDL heheh )

Article: 51520
Subject: Re: Short FIFO in Verilog / Spartan IIE
From: Ken Chapman <chapman@xilinx.com>
Date: Wed, 15 Jan 2003 15:33:32 +0000
Links: << >>  << T >>  << A >>

The background to how the BBFIFO works is explained in my TechX on using the
SRL16E.

http://www.xilinx.com/support/techxclusives/SRL16-techxclusive4.htm

The fact that a FIFO can be implemented using only one counter is fantastic for
keeping the control logic small and also provides an accurate measure of how full
the FIFO is at all times.

Ken Chapman




Article: 51521
Subject: Re: How can I use DCM to 1/24 freq-division?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 15 Jan 2003 07:54:13 -0800
Links: << >>  << T >>  << A >>
Cisa,

The DCM outputs (all execpt for the CLKDV and CLK2X) have a minimum
output frequency of 24 MHz.

CLK2X is 48 MHx min, and CLKDV is 24/16 MHz (1.5) min.

I suggest to use a simple synchronous counter to simply divide by 24
(synchronously).  At these low frequencies, you do not need the 100 ps
alignment offered by the DCM.

Austin

Cisa wrote:

> Now I have a clk whose frequency is 30.72,and I want to use DCM
> to generate another clk whose frequency is 1.28MHz.
> How can I get it?I failed in reality.Pls give me some advance.


Article: 51522
Subject: Re: Student development board
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Wed, 15 Jan 2003 08:08:19 -0800
Links: << >>  << T >>  << A >>


geeko,

This board is not available as a kit, and is not offered assembled or for sale
by Xilinx.  The documentation is public, and if anyone wants to make their own,
please email me at austin@xilinx.com for the pcb artwork files.  Note that the
Berkeley Logo is copyright the Regents of the University of California, so you
must put your own logo on the artwork.

We (Xilinx) offer no support on this, but will work with a university if they
wish to duplicate/modify this design in terms of offering advice, and reviewing
the engineering and artwork if this is to be used for undergraduate instruction
(classes).

The builder takes all responsibility for getting it to work, but we will advise
if you do encounter any issues (just like any pcb built by anyone that uses our
parts).

As noted in the link to the university program, there are many platforms that
can do the job.  This one was intended to support a number of different classes,
and has features that allow for ethernet, video, DSP, etc.

OK, so it is really sexy.  I can't help liking it, I helped design it.

Since I taught EECS 150 about 28 years ago, and I remember the lab with its
'superstrips' and 7400 logic (MSI!), leds, and 20 MHz scopes, it was a really
fun project to assist the folks at UCB who took on the arduous task of
redesigning the lab.

PS:  All of the components should be available 'over the counter' from
distributors.

Austin

geeko wrote:

> Hi all
>  I tried to procure the components for the Berkeley  board but failed
>  Is this board is available in assembled form or as a kit with pcb and all
> components
>
> with regrds
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3E1F0E35.D99D6FA0@xilinx.com...
> > All,
> >
> > A very nice platform for FPGAs was developed by UC Berkeley (in
> cooperation we
> > Xilinx):
> >
> >  http://kamsky.eecs.berkeley.edu/calinx/pdf/Manual.pdf
> >
> > I would suggest you contact UCB, or myself, if you are interested in
> making some
> > for your school.
> >
> > There are many platforms that are much less capable, and perhaps any one
> of
> > those would be suitable for an introductory level course.  Please review:
> >
> >  http://www.xilinx.com/univ/index.htm
> >
> > Austin
> >
> > Rene Tschaggelar wrote:
> >
> > > David wrote:
> > > > Hi,
> > > > Does anyone know what is the best choice for an fpga developement kit?
> > > > Altera offers this kit for University student :
> > > > http://www.altera.com/education/univ/kits/unv-kits.html
> > > > I wonder if there are other supplier of boards like this (could be
> Xilinx
> > > > too) that could compete with this. Are there third party manufacturer
> that
> > > > are worth considering?
> > >
> > > All these offers are comparable.
> > > The software usually can be downloaded, at least reduced versions.
> > > The programmers can be selfbuilt or purchased.
> > > And finally you need some chip on a board.
> > > While 150$ is not much you should base your preference based on
> > > who is going to help you and who is going to introduce you into this
> > > technology. A colleague is best as you'll spent a few feeks at least.
> > >
> > > Rene
> > > --
> > > Ing.Buero R.Tschaggelar - http://www.ibrtses.com
> > > & commercial newsgroups - http://www.talkto.net
> >



Article: 51523
Subject: implementation of a switcher
From: nicemanYep@yahoo.co.uk (Anonymous4)
Date: 15 Jan 2003 08:20:08 -0800
Links: << >>  << T >>  << A >>
Hello,
Looking to implement a 2-Input-2-output switcher or router.
Bascially the sought Block receives 2 parallel inputs and output the
same inputs in parallel but in different orders
sometimes[ Out1,Out2] in parallel, sometimes [Out2,Out1] in parallel

Obviously 2 parallel multiplexer can implement it, wondering on any
other exiciting trick

thanks

Article: 51524
Subject: Re: Open FPGA please!
From: Ray Andraka <ray@andraka.com>
Date: Wed, 15 Jan 2003 16:21:14 GMT
Links: << >>  << T >>  << A >>


No, the router actually takes considerably longer than it did under 3.3 if the timing
constraints are tight.  Unfortunately, one is forced to use the later versions for any of the
virtex2 or spartan2E devices.

Jim Granville wrote: Since a 'heavily floorplanned designs' has most of placement the work

> done,
> one could expect the routers to finish much faster.
>
>  Do you see much difference in the completion times of the 3.3 tools, vs
> 5.1 tools ?
>
>  It's a common problem, supposedly smarter tools being harder to
> control, and/or
> giving dumber results..
>
> -jg

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759





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