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Depends heavily on your design and requirements. I've done many filters over
the years with no multipliers or RAM (see the distributed arithmetic tutorial
on my website).
Nick Campregher wrote:
> Hi all,
> what do you think is the most efficient multipliers - Ram ratio to
> implment good FIR/IIR filters?
>
> I'd assume the multipliers are 18x18, and the ram blocks will be of around
> 512 locations.
>
> Thanks very much
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56451EU, The simple answer, no there are no "fuses" in a standard CMOS process. The more complex answer is later (perhaps two years) after a process is introduced, they may then perfect the fuse (antifuse) and have a standard cell fuse available in the design library (only maybe). Might still require an extra mask, or a process tweak. Too late then. Like I already said, if it was there, it would be in our chips. Austin EU wrote: > Hi All... > > I really donīt have any decent knowledge in silicon design, but iīm > just wondering... > Even in a standard CMOS process, would it be possible to sneak in some > antifuse(or similar) bits that are write-only? Maybe something like a > public/private key could do the job. The public key could be read from > the device, in order to encrypt the bitsteam, but the decryption > procces would need the private key, wich is not readable. > By the way, I really like the idea of having some level of protection > in the lower costs design, but I think they donīt need to be as good > as the top of line products... My specific needs are that it canīt be > copied by a tecnician in a repair shop. > > bye... > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3EDE21BD.D1E0129B@xilinx.com>... > > Raymund, > > > > Laser popping of fuses is a well known, and well used technology in low cost > > manufacturing, but as a means of keying the device, pretty lousy security. > > Imagine just popping the lid and examining the blown holes in the polyamide? > > > > Basically, remember that we really really really want to do what you are > > suggesting, and it isn't for lack of trying, or experimentation, that it isn't > > there. > > > > We have two issues: no good practical low cost secure way to put keys into a > > standard CMOS process, and very few customers willing to pay a premium. > > > > Right now we have the feature in V2 and V2P with the battery backed up RAM. > > Cost? One lithium coin cell, (coind cell holder), a diode, and a capacitor (to > > prevent memory loss when you replace the battery). Maybe throw in a 1Mohm > > resistor in series to help prevent memory loss if someone shorts out the battery > > while replacing it. > > > > Not the best solution (I would love to have NVRAM in standard CMOS, too), but > > > one that allows folks who absolutely have to have triple DES level encryption to > > succeed. > > > > Austin > > > > raymund hofmann wrote: > > > > > "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag > > > news:3EDB8423.29CA2C46@xilinx.com... > > > > > > > > > > > > emanuel stiebler wrote: > > > > > > > > > But, anybody out here has an idea, why there is no bitstream encryption > > > > > on the spartan 3 ? With all this gates & memory, you could do impressive > > > > > designs, but to keep them for safe you still have to go to the virtex > > > > > chips ... > > > > > > > > It's really quite simple: > > > > The priorities for Spartan are: Low cost first, features and speed second. > > > > For Virtex the priorities are reversed. > > > > Makes a lot of sense, avoids unproductive overlap, and gives the user a > > > > fair choice. Cheap or fancy. There is no free lunch... > > > > > > > > Now, if encryption were a popular feature in the low-cost market (please > > > > tell us), then it would make sense to dedicate some silicon and a pin > > > > for the on-chip decryption. > > > > > > Why don't put a kind of "Host ID/Serialnumber" on the FPGA in some kind of > > > "one time programmable" way at Manufacturing the FPGA ? > > > I think Intel CPU's already each have different ID's since some time. > > > > > > I doubt this is a cost/performance penalty like manufacturing a FPGA on a > > > flash-process. > > > > > > This ID can then be used to decrypt a bitstream. > > > And the device should accept two kinds of bitstreams: > > > Encrypted with it's ID + Unencrypted. > > > And this ID should be electronically readeable off the FPGA. > > > > > > I think it is only a matter of time when one FPGA company starts such a > > > thing even for the "low cost" Parts. > > > > > > Of course will the FPGA Customer have to care about generating individual > > > Bitstreams for each device ID of the Part's used, if he wants "security". > > > As there often is a MCU with the FPGA(s) on Board there is additional > > > flexibility in handling the "design security". > > > Or he may choose not to encrypt. > > > > > > Raymund HofmannArticle: 56452
"parity bit" is just a name, suggesting one possible application. We might have called it "extra bit", or "Xilinx Ninth"... Use to store parity must be very rare. Peter Alfke Kevin Neilson wrote: > > The extra bits turn out to be really convenient in many cases. I've used > them often for start-of-packet and end-of-packet flags. > > If these are intended to be used for parity, I've wondered why Xilinx didn't > build in a hard-core parity generator/checker. For high-speed applications, > you have to pipeline the parity-check logic, and then use a lot of flops to > delay the RAM output. > > -Kevin > > "Muthu" <muthu_nano@yahoo.co.in> wrote in message > news:28c66cd3.0306041955.76ef7d8d@posting.google.com... > > Hi, > > > > In all Xilinx block RAM Primitives, they have allocated Parity bits (1 > > per byte) for each locations. If we see the 32bits with RAM, > > additional 4 bits being provided for the Parity. > > > > In most of the cases, we are not using this. This is because, all our > > RAM is internal, there is not possibility of data corruption. > > > > If this is the case, why they have provided that parity bits. > > > > Regards, > > MuthuArticle: 56453
"Kevin Neilson" <kevin_neilson@removethistextattbi.com> wrote in message news:<eiBDa.1133510$S_4.1168146@rwcrnsc53>... > I've been studying Galois fields, and I wondered if this branch of > mathematics has any other application besides forward correction encoders > (and maybe encryption circuitry). Galois lived a long time ago; did he have > any use in mind for his fields? Would they just be a curiosity if not for > error correction? > -Kevin Galois theory is just a piece of the larger group theory which has dozens of applications today in chemistry, physics, engineering, etc. So while the major apps for finite fields has been cryto, random number generation, and coding theory, group theory reaches well beyond these narrow areas. JakeArticle: 56454
Thank you for your reply. I have looked at a number of ways to implement filters in FPGAs, and was now wondering, if I had as many multipliers as possible, what amount of RAM I needed..... It's all theoretical work, and I just wanted to know a good ration not to waste any resource because of unavailability of another...... There is no particular design to be implemented, just find a solution ideal for all filter sizes and speeds. Thanks, Nick "Ray Andraka" <ray@andraka.com> wrote in message news:3EDF5FE7.9504022A@andraka.com... > Depends heavily on your design and requirements. I've done many filters over > the years with no multipliers or RAM (see the distributed arithmetic tutorial > on my website). > > Nick Campregher wrote: > > > Hi all, > > what do you think is the most efficient multipliers - Ram ratio to > > implment good FIR/IIR filters? > > > > I'd assume the multipliers are 18x18, and the ram blocks will be of around > > 512 locations. > > > > Thanks very much > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 56455
Muthu wrote: > My question is: this a <= a is reduntand assignment. But it is really > required because we have put the case as full_case. > > Else, when this state comes the output may not be un known. Is this > correct? Why not run a simulation and find out? > Will any sythesis tool could generate error on this reduntant > assignment. Don't worry about synthesis until you have a successful sim. -- Mike TreselerArticle: 56456
Does anyone know how to use DSTROBE to clock data in CRC generator and FIFO? I try to build a host ATA-6 udma controller in virtex. ThanksArticle: 56457
Priyal wrote: > > Hi, > I am a graduate student in Electrical and Computer Engineering. > I still have 1 more year to graduate. > I want to design hardware which has some practical application. > I am looking for topics in Digital Design/VLSI on which i can do my final project. > Can anyone suggest some related topics? I would suggest that you take a look at www.opencores.org. There are lots of projects that you can work on. Or you can come up with your own and get a lot of support there. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56458
Muthu wrote: > > Hi, > > The sequential block which generates the output signals will be > written as below. > > case(1) // synthesis full_case > preset_state[s0]: > begin > a <= 1'b1; > end > > present_state[s1]: > begin > a <= 1'b0; > end > > present_state[s2]: > begin > a <= a; > end > endcase > > In the above piece of code, signal a is getting varied only in S0 and > S1. But in S2 it remains unchanged. > > My question is: this a <= a is reduntand assignment. But it is really > required because we have put the case as full_case. > > Else, when this state comes the output may not be un known. Is this > correct? > > Will any sythesis tool could generate error on this reduntant > assignment. I am not sure what you are concerned about. The assignment a <= a; is only meaningful within a sequential block which will synthesize a FF. In case s2, the FF will not be enabled. This is not an error, this is a valid and often used mode of operation for FFs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56459
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:bbfuh0$92f2j$1@ID-84877.news.dfncis.de... > "Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag > news:3EDB6220.5E6F03FE@xilinx.com... > > > If we went "whole hog" we could be like Intel, with 50% of the power in DC > leakage. > > ??? > Sure? > You mean, all those Pentiums -III/IV/whatever to come burn 50% of their > power, eben if the clock is disabled?? Many intel processors in the past used dynamic logic, so you couldn't stop the clock. Processors with PLL clock generators also will be restricted in allowable clock frequencies. -- glenArticle: 56460
naderimisc@yahoo.com (Masoud Naderi) wrote in message news:<2ba3bbea.0306011137.4e9857fc@posting.google.com>... > Hi all, > I want to do some basic sonet/sdh mapping, framing, pointer processing > on xilinx spartan IIE. I see PMC-Sierra chipset on SDH, they are do > many different things that I do not need for a basic STM-1 link. ( I > want do multiplex 16*16Mhz signal on STM-1 frame). PMC-Sierra temux > and spectra chipset are very complex and expensive ( $600 for both ). > Does anybody has practical experince on this. I look for a more clear > perspective on FPGA implementation. > Best Regrads. > M. Naderi Hi Masoud, I designed recently an STM4 frame. To start you need the ITU-T G.707. The design it could be 6 mounths long or more. If you want to design the framer and the deframer in a Xilinx FPGA you need at least 300 kgates or more (if you want other feature inyour FPGA.) The transmitter is not so hard to design. Do you need to change the pointer on the TX? the RX is more complex, the problem are: 1)IF with the optical rx 2)FAS Framing allineament 3)pointer detection. 4) managment of AIS, RDI, REI,etc. (in auto or manual) If you need some help, just ask regards, FrancescoArticle: 56461
I have a simple CPLD, that does a ROM function. I need several different versions, and am using Excel to create the different ROM tables. I would like to export them out to a text file and then have them read by my VHDL code.This would let me easily create different versions of my CPLD without alot of typing or cut and pasting. My ROM takes an 8 bit address and re-maps its value to another 8 bit value. It seems doable, and was hoping a simple example exists. Does anyone have a design example of code where variables can read in from a text file and then be synthesized?Article: 56462
Depends on what you want each multiplier to do. If you have one tap per
multiplier per clock, you only need a constant. If you are using one
multiplier over N clocks to do N taps, then you need an N word deep memory
associated with the multiplier....
Nick Campregher wrote:
> Thank you for your reply. I have looked at a number of ways to implement
> filters in FPGAs, and was now wondering, if I had as many multipliers as
> possible, what amount of RAM I needed..... It's all theoretical work, and I
> just wanted to know a good ration not to waste any resource because of
> unavailability of another......
>
> There is no particular design to be implemented, just find a solution ideal
> for all filter sizes and speeds.
>
> Thanks,
>
> Nick
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3EDF5FE7.9504022A@andraka.com...
> > Depends heavily on your design and requirements. I've done many filters
> over
> > the years with no multipliers or RAM (see the distributed arithmetic
> tutorial
> > on my website).
> >
> > Nick Campregher wrote:
> >
> > > Hi all,
> > > what do you think is the most efficient multipliers - Ram ratio to
> > > implment good FIR/IIR filters?
> > >
> > > I'd assume the multipliers are 18x18, and the ram blocks will be of
> around
> > > 512 locations.
> > >
> > > Thanks very much
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56463I absolute agree /w Murray, a FIFO is simple solution to cross clock domain like that.Article: 56464
flamarca wrote:
> I have a simple CPLD, that does a ROM function. I need several
> different versions, and am using Excel to create the different ROM
> tables. I would like to export them out to a text file and then have
> them read by my VHDL code.This would let me easily create different
> versions of my CPLD without alot of typing or cut and pasting.
Consider getting a text editor that does scripts or keyboard macros.
Editing constant arrays should not be a problem.
see: http://groups.google.com/groups?q=vhdl+this_rom
-- Mike Treseler
Article: 56465Agreed, provided you can drive one of the two clocks across the chip boundary. The FIFO needs access to both clocks, and preferrably should also drive a handshake (FULL or EMPTY) across the chip boundary. Peter Alfke =========== Lnguen wrote: > > I absolute agree /w Murray, a FIFO is simple solution to cross clock > domain like that.Article: 56467
Mike Treseler wrote: > > flamarca wrote: > > I have a simple CPLD, that does a ROM function. I need several > > different versions, and am using Excel to create the different ROM > > tables. I would like to export them out to a text file and then have > > them read by my VHDL code.This would let me easily create different > > versions of my CPLD without alot of typing or cut and pasting. > > Consider getting a text editor that does scripts or keyboard macros. > Editing constant arrays should not be a problem. > > see: http://groups.google.com/groups?q=vhdl+this_rom > > -- Mike Treseler Or with just a bit of work, you should be able to get your spreadsheet to output a VHDL module text file. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56468
Thank you guys. I guess the FIFO should solve the problem. I did read the article by Peter and that was helpful too. PrashantArticle: 56469
I want to congratulate Harry Foster, Adam Krolnik, and David Lacey on an excellent job in the writing of the book "Assertion-Based Design" published by Kluwer. This book addresses, among other things, the assertion methodology, properties and assertion patterns for PSL, OVL, and PLI-based assertions. I highly recommend it. --------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Using PSL/Sugar with Verilog and VHDL Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 56470
I've run into an odd problem with the third stage of a 12-bit synchronous binary counter simulation. This circuit consists of an FTRSE driving the CE inputs of each of three CB4RE counters, concatenated in the obvious way. An the FTRSE and the three counters are all clocked with a common clock, and the counters' enable is driven from the output of the FTRSE which is set from an external start strobe two clocks long, and cleared when the last stage generates its CEO (count enable out). Unfortunately this output, clearly an entire clock cycle long (not one of the infamous glitches these can generate) occurs when the LSB of the third stage is false, which is not what one would expect, since this output is not registered, but is gated from the synchronous outputs AND the quite static input. Has anyone else encountered this apparent anomaly? thanks, Richard ErlacherArticle: 56471
muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0306041946.37cce689@posting.google.com>... > Hi, > > Is "defparam" is synthesizable or not? I have tried with xilinx XST. > But it is giving some errors. Ummm, what's the error? > So, currently i am passing parameters with #(). > > Any one used defparam in the design? Yes. However, the more interesting question is: does the synthesis tool let you set the value of the parameter? In other words, say your top-level file has a parameter called FOOSIZE, and you'd like to be able to set the parameter FOOSIZE from either the command line, a synthesis script or the synth-tool GUI. Score: Leonardo: Yes. Synplify: No. Of course, both allow VHDL generics to be set from the command-line or GUI. Did I just violate some arcane no-benchmarking license clause? --aArticle: 56472
vishker@yahoo.com (Vishker) wrote in message news:<9ea7e3a3.0306041058.6d799d58@posting.google.com>... > Can we generate Post P&R Verilog or VHDL netlist from ISE that can be > synthesiable ? I used ngd2ver but the output verilog netlist contains > lots of statements that are not synthesizable. Same is the case with > VHDL. You're missing the point of the post P&R HDL file. The design has already been synthesized (and placed and routed). You use this file (with the .sdf) to perform a post-layout timing simulation on your design. -aArticle: 56473
Cheny <wucheny@netscape.net> wrote in message news:<bbike4$3td$1@news.storm.ca>... > leon qin wrote: > > Are they the same ? > > > > > > > they are different that SVF player accepts SVF files while stapl player > accepts jam files. SVF and STAPL players are very different, but both can be used to program CPLDS: SVF (serial vector format) is a file format used by in-circuit testers. The programming data and algorithm for a CPLD can be written into SVF format so in-circuit testers can program CPLDs via JTAG during in-circuit test flow. An SVF player/interpreter, as it pertains to PCs, would "play" the SVF file's algorithm and program the device through a PC's parallel port during prototype. The problems with SVF is that was not created for programming CPLDs but rather for in-circuit test. SVF does not support branching in its language constructs resulting in longer programming times for CPLDs. It's also a sequential text file format - it does not support loops, resulting in very large sequential based files. As a whole SVF would really only be used if you were planning to production program devices through in-circuit testers that do not support STAPL. STAPL is a high level language designed specifically for CPLD ISP programming. It supports branching - which means faster programming times. A CPLDs programming algorithm and data is stored in ASCII STAPL or compressed byte code STAPL format. STAPL language also supports loops (e.g. FOR). This combined with compressed byte code means very small files. This is ideal for embedded programming where an intelligent host or microprocessor can use the STAPL player/interpreter to ISP program CPLDs. The STAPL player is also available to play through DOS executable or through Altera's MAX+PLUS II or Quartus tools in windows or UNIX environment. The Altera MAX+PLUS II or Quartus software Programmer Tools support "playing" STAPL files. Altera also supports generating SVF files. The original name of STAPL was Jam (as in Jam Player). STAPL is the name assigned to this language during the JEDEC standardization process. Sincerely, Greg Steinke Altera Applications gregs@altera.comArticle: 56474
H. Peter Anvin wrote: >> But you know before it leaves the programmer and gets on the >> board. The reliability after passing programming is quite >> excellent. If you had to test on the board for the 2-3% dropout >> then that would be bad. As an aside, something I've looked into, >> fault coverage pre-programming for antifuse FPGAs can be quite >> excellent through on-chip test support. > > Sure. It just means that you have to program (and test) the > devices before board assembly, which isn't possible in all > production flows. Definitely not an issue for everyone, but it is > an issue for some users, and should be kept in mind. The integrity testing is automatic on the programmer so that part is transparent. Having to program on a programmer obviously is not. -- rk, Citizen, Noooo Yawk "Sometimes when you connect the dots you get a picture. Other times you just have a bunch of dots." -- rk, January 23, 2003
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