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"..:: Gabster ::.." <gabsterblue@hotmail.com> wrote in message news:aeGPa.22934$Pe2.782024@wagner.videotron.net... > This is really an appropriate reply and I feel confident to start the design > of my board. > > Thanks, this is really appreciated. > Gabriel > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F0F2A63.C758E3FE@yahoo.com... > > One other point I would like to make. A lot of people will tell you to > > use multiple Tantalum caps, including the Xilinx app notes. But > > Tantalum caps are inherently slow compared to the noise on the board. > > So you can get away with a single cap anywhere on each power plane it > > will fit. But 10 uF may be a bit small. I build a board with a 10 uF > > cap and found that the power line impedance coming to the board created > > voltage spikes enough to show up in the analog circuits. A larger > > Tantalum cap on the board would have prevented this. Of course better > > power conductors solved the problem as well. > > > > -- AND if noone mentioned it the most important part is lots of 47nF ceramic caps distributed and centered at the EMI generating components. I don't aggree with the statement that the supplies should be joined in a " star" connection. Thats asking for trouble. If you have a solid power/ground plane with addequate decoupling there is no reason to split the power-plane up. Allthough other rules apply when you are talking microvolt analog circuits and if the board get so big that the ressonace of the powerplanes will kick in. Cheers KlausArticle: 58026
Hallo, I'm just making my first steps in FPGA programming. So, I bought myself a development board with a SpartanIIE. My first try was to use the DLL. It works pretty well except the additional CLK2X180 output in the CLKDLLE macro. What I figured out so far is that in the FPGA Editor the so called CLK2X180 output doesn't exit at the DLL. There is just another output called CLK2X90. Not the same like the Libraries Guide says. Is there maybe a bug? I'm using the 5.1 Webpack with Service Pack 3. Another small question. When I connect to the FPGA via Boundary Scan the device found is a xcv200e although the print on my IC says it is a xc2s200e. So, its reading a work device ID. Can that happen? Thanks Thomas FuchsArticle: 58027
Hi Thomas, concerning the DLL problem I don't know, however concerning the JTAG chip type name, this is ok. The similiar thing happens if you connect through JTAG a Spartan-II chip. It's saying it's a Virtex device. I don't know the reason for this identification mismatch, however Spartan-II is being derived from Virtex as Spartan-IIE is being derived from Virtex-E markus "Thomas Fuchs" <thomasfuchs77@t-online.de> schrieb im Newsbeitrag news:bep5ud$spu$04$1@news.t-online.com... > Hallo, > > I'm just making my first steps in FPGA programming. So, I bought myself > a development board with a SpartanIIE. My first try was to use the DLL. > It works pretty well except the additional CLK2X180 output in the > CLKDLLE macro. What I figured out so far is that in the FPGA Editor the > so called CLK2X180 output doesn't exit at the DLL. There is just another > output called CLK2X90. Not the same like the Libraries Guide says. Is > there maybe a bug? I'm using the 5.1 Webpack with Service Pack 3. > Another small question. When I connect to the FPGA via Boundary Scan the > device found is a xcv200e although the print on my IC says it is a > xc2s200e. So, its reading a work device ID. Can that happen? > > Thanks > Thomas Fuchs >Article: 58028
brad@tinyboot.com (Brad Eckert) wrote in message news:<4da09e32.0307111552.189961b8@posting.google.com>... Hello Brad. Firstly, why do you need a synthesizable testbench? You wrote you only need it for simulation. Do you plan to synthesize it as well? Secondly - I think you are being far too pessimistic about the static timing analysis tools. From my experience, they are quite reliable - if you constrain them correctly. What you should do, is apply multi-cycle path and false path constraints where needed, and just let the tool perform the analysis based on the clock frequency you specify. This is a much better approach than attempting to perform exhaustive post-fit simulation, for a two reasons (I can think of): 1. How can you be sure you have tested all of the paths. You could have easily forgotten a path that occurs in some extreme scenario your testbench does not cover. 2. It takes significantly less time to perform static timing analysis. Once you have constrained your design, every change in it can easily be analyzed again. With post P&R simulation, you have to run all of the tests all over again. For large designs, this could take weeks. Sometimes you must peform post P&R simulation, but I don't see any reason it should replace static timing analysis. Gilad Cohen. gilad_coh@walla.co.il.Article: 58029
I have experience with Xilinx, Altera and Lattice but no Actel's. I'm on a project that committed to an APA series part. After an initial route I am getting what I would consider (after recently using Virtex 2) poor timing, especially on high fannouts that need buffering. Question: is 80Mhz an overly optimistic clk speed target (in general) for these parts? Thanx in advance, JPArticle: 58030
Rick, You are missing something. Any shred of digital design capability or ability to solve any problem on your own. Why don't you just give up? McDonald's is always looking for someone with your ability. I would recommend you go to college and get a BSEE. Concentrate on digital design techniques. Is Arius even a company? I'd be embarassed if my boss could see my incompetence so publicly. You must be the CEO, President, VP of Engineering and lone grunt at Arius all rolled into one. Good luck buddy. Stifler rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F0EEEC8.D5038C4B@yahoo.com>... > Amontec Team wrote: > > > > For myself, I never use both ieee.numeric_std.all and > > ieee.STD_LOGIC_ARITH together ... can produce many troubles since there > > describe same functions. It is very dangerous, because the compiler or > > syntheziser can interprete different things. > > > > For your code, why > > ELSE STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z'); > > > > and not > > ELSE (others => 'Z'); > > > > maybe this casting can be not so nice, try to skip it, you very don't > > need that! > > I need to sit back down with my books! It has been so long since I have > written VHDL that I don't remember what all the libraries do. I do > remember that you want to use numeric_std rather than the Synopsis > signed and unsigned libraries. > > The type cast was held over from where I started with this example. I > started with a 16 bit data bus and an 8 bit register. I had it written > to force the unused bits to 0 like this... > > Data <= STD_LOGIC_VECTOR (7 downto 0)'(others => 'Z') & ScratchReg; > > This is the sort of thing that is not always obvious in VHDL since the > strong typing can get in the way of what you want to do. I remember > that aggregates and concatenation could give errors very easily between > the language *features* and the compiler bugs. > > Now my work is to build this up into a useful circuit while mapping out > all the quirks of the tools. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58031
I understand that Modelsim is capable of running on server farms in order to accelerate processing. Can Xilinx Foundation take advantage of disributed processing as well? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 58032
I found there are many FPGA devices, how to choose a good one for myself?Article: 58033
Hi, Mike, Could please enlighten me on your usage integer'image(null_vec'left) What's it doing? Is image the function that Ben Cohen provides on his CD with his books? What is integer' doing? type casting? Have I been asleep, or why don't I know about this from all of my reading. Please advise, and thank you. Clyde Mike Treseler wrote: > Alan Fitch wrote: > > > > > I personally don't think it should be a warning, as it's quite legal > > to declare null vectors > > I agree. > > A bad assignment to a null vector will cause other errors. > A null vector declaration alone is innocuous. > > If one bit is 0 to 0 then > no bits must be 0 to -1 > > Let's see: > ------------------- > > entity null_string is > end null_string; > > architecture sim of null_string > is > constant null_vec : std_logic_vector := ""; > constant one_vec : std_logic_vector := "0"; > constant two_vec : std_logic_vector := "00"; > > begin > > what : process is > begin > report "null_vec is "& integer'image(null_vec'left) > & " to "& integer'image(null_vec'right); > report " one_vec is "& integer'image( one_vec'left) > & " to "& integer'image( one_vec'right); > report " two_vec is "& integer'image( two_vec'left) > & " to "& integer'image( two_vec'right); > wait; > end process what; > > end sim; > > --VSIM 1> run > --# ** Note: null_vec is 0 to -1 > --# ** Note: one_vec is 0 to 0 > --# ** Note: two_vec is 0 to 1 > > ------------------------ > > I suppose that null vectors are rare as signals > but null vector constants and variables are necessary to make > clean vector functions. > > --Mike TreselerArticle: 58034
Clyde R. Shappee wrote:
> Hi, Mike,
>
> Could please enlighten me on your usage
>
> integer'image(null_vec'left)
It an integer, the left index of the vector.
> What's it doing? Is image the function that Ben Cohen provides on his CD
> with his books?
No. Standard VHDL. Supported by all the sim and synth tools I have tried.
> What is integer' doing? type casting?
No. It's a built in VHDL "attribute" , a kind of function.
> Have I been asleep, or why don't I know about this from all of my reading.
A lot of the cool parts of VHDL-93 were neglected, because
they didn't work with every version of every tool.
They now work with most versions of most tools, so
feel free to use them.
-- Mike Treseler
Article: 58035On 12 Jul 2003 14:27:22 -0700, yijun_lily@yahoo.com (yxl) wrote: >I found there are many FPGA devices, how to choose a good one for myself? Try this: http://www.fpga-faq.com/FAQ_Pages/0014_Xilinx_vs_Altera.htm =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 58036
"Klaus Vestergaard Kragelund" <klauskvik@hotmail.com> wrote in message news:3f0fb7bf$0$24657 (snip) > AND if noone mentioned it the most important part is lots of 47nF ceramic > caps distributed and centered at the EMI generating components. > > I don't aggree with the statement that the supplies should be joined in a " > star" connection. Thats asking for trouble. If you have a solid power/ground > plane with addequate decoupling there is no reason to split the power-plane > up. Allthough other rules apply when you are talking microvolt analog > circuits and if the board get so big that the ressonace of the powerplanes > will kick in. I thought that was because there are multiple power voltages. If you can't afford a separate power plane for each, and I don't believe many do that, then you have to split them up somehow. If you can arrange all the parts for for each voltage together, it should be easier. Then put the regulators near the junction between the different voltage planes. That is what I thought was meant by star pattern. -- glenArticle: 58037
Hi,
I am in the process of doing a re-design on a multi-board system that I
have working right now. We are redesigning to convert to USB2.0 and to add
some features. The system is a low noise data acquistion system using a
pulse width modulator to control the sensor. The current generation unit
uses a ribbon cable with alternating signal/ground connections for the
backplane and the clock is being distributed as a LVPECL differential signal
using two 50 ohm coaxes and MCX connectors. I am being pushed to go to an
edge card connector to use for power, logic signal and clock distribution
(200 MHz clock). The connectors would be put on a real backplane. I should
note that the bus has as many as 18 daughter cards and 1 master card. Some
of the logic signals are bi-directional (tri-state drivers from a spartan2e
FPGA). My concerns are two-fold. First is can the clock be distributed
adequately over an edge card (for example something like an AGP connector).
Second, can I get the bus working correctly for the data stuff. Note: the
bus uses standard lvttl (3.3v) for logic signals at a minimum pulse width of
about 40 ns. I am quite concerned that I not get into any signal integrity
issues. I tried to do something like this earlier and had some problems.
One concern is that the data strobe could ring and generate a false data
write condition. Does anyone have any experience with this sort of thing?
Especially with getting edge card connectors with a known characteristic
impedance? The bus has a total of 19 connectors spaced at about .75" apart.
Some of the connectors could be left open and also there will be a sort stub
on the individual cards that must be terminated in some fashion.
Thanks,
Theron Hicks
Article: 58038>If you can arrange all the parts for for each voltage together, it should be >easier. Then put the regulators near the junction between the different >voltage planes. I think the star approach comes from the analog guys. The idea is that heavy currents in one section won't add IR drop on the ground traces of another section that is processing low level signals. The cost is another (ground) wire for the low level signal. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 58039
Hi, If someone know where I could find the orcad capture symbol for the XC2S300E in PQ208 package it would save me a lot of trouble and time. Thanks, GabrielArticle: 58040
"t hicks" <hicksthe@egr.msu.edu> wrote in message
news:beqgl8$8m8$1@msunews.cl.msu.edu...
> Hi,
> I am in the process of doing a re-design on a multi-board system that
I
> have working right now. We are redesigning to convert to USB2.0 and to
add
[SNIP]
> Thanks,
> Theron Hicks
Just some anecdotal evidence. We had a fairly simple multi-card PCI
setup where we had to use very short line-lengths to an on-card PCI bridge
for each card because the signals with simple daughter cards were unusable.
Known impedance and proper termination is critical even at the PCI's 33/66
MHz. 200 MHz would be many times worse.
Norm
Article: 58041Well.. first decide the supplier and then the toolset .. Do you want Xilinx ? or Altera ? as they are two of the biggest. This might be a decision based upon the evaluation boards available and the price you are prepared to pay for them or what the university / company use. The tools then comes down to cost.. free or $$$$.. the $$$$ tools will generally cost lots for one FPGA supplier ... or add a few (more) zero's to the end of the price for multi-vendor support. But if your starting to learn.. consider Cyclone or Spartan-II or Spartan-3.. there should be evaluation boards for both all of which will set you back less than $500, all 3 chips have good and bad features but if your starting, it doesn't really matter, its not like you will push the technology (much). IMHO the Altera free tools are easier to use and have a useful, if very slow, simulator with entry by schematic, AHDL, VHDL and Verilog so its hard to beat. The licensing does require you to have a network card so you might have to buy one if you don't already have one. You might also have to build yourself an Altera download cable. Its quite easy on a vero board or even CAD. I do have PCB's for both Xilinx and Altera downloader's but am not sure there's the volumes required to build more as they cost me money for getting them built :-) Simon "Philip Freidin" <philip@fliptronics.com> wrote in message news:hkd1hvcl64n2ue7v8cldne7rims4cnp10r@4ax.com... > On 12 Jul 2003 14:27:22 -0700, yijun_lily@yahoo.com (yxl) wrote: > >I found there are many FPGA devices, how to choose a good one for myself? > > Try this: > > http://www.fpga-faq.com/FAQ_Pages/0014_Xilinx_vs_Altera.htm > > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COMArticle: 58042
Hello all, thanks for your valuable suggestions. I did go with the ISP -EPROM option chosing the XC18VXX device. I had to keep it low-cost and hence it wasnt that expensive. I do have to use Xilinx Parallel IV cable for ISP and I am going to use the JTAG option for programming too, to keep it as a backup. Thanks and cheers Anup Ashok Chotai wrote: > Hello Anup, > For existing designs, we would suggest you to keep using the > Spartan-XL PROM(OTP) or the XC18V(ISP) PROMs. If it's a new design, > then use the Platform Flash ISP PROMs. See here for more info on Flash > PROMs. > Ashok > > > Spam Hater wrote: > >> If the little XC18V's will do it, the big ones will too. Just >> ignore >> the extra bits. The Spartan will stop clocking when it's done. >> >> What you're really looking for doesn't exist, and won't. The >> Spartan >> and the SpartanXL are dead parts (in Xilinx's view). >> >> Sorry, >> SH >> >> On Thu, 10 Jul 2003 12:36:57 +0930, Anup Kumar Raghavan >> <> wrote: >> >> >I need to select a Configuration solution for programming the >> Spartan XL >> >XCS10XL device. I have chosen to use the Master Serial Mode >> >configuration using the PROM XC17S10XL, which is OTP. I havent >> found any >> >reference to ISP (EPROM) solutions for the Spartan XL and hence >> need >> >some advice on this. I know there is this device XC18V256PC20C, but >> >> >Xilinx mentions that this is not supported anymore. >> > >> >Thanks and regards >> >Anup >Article: 58043
Hello, is there a way to verify Virtex bitstreams before they are downloaded onto the device? I am modifying Virtex bitstreams using JBits and want to verify or simulate my modify design at this level? Thanks AnupArticle: 58044
I don't think you want to do that. The proper way to do this is to create the symbol with heterogenous parts; you make each sub-symbol match what the circuit is doing. I make part-A have the power and ground pins. Part-B has the configuration and JTAG pins. Parts C through X are specific to the design. Take a look at the way Tony did it: www.burched.com SH7 On Sun, 13 Jul 2003 01:00:50 -0400, "..:: Gabster ::.." <gabsterblue@hotmail.com> wrote: >Hi, > >If someone know where I could find the orcad capture symbol for the XC2S300E >in PQ208 package it would save me a lot of trouble and time. > >Thanks, >Gabriel >Article: 58045
On Sat, 12 Jul 2003 20:45:12 -0700, t hicks wrote: > Hi, > I am in the process of doing a re-design on a multi-board system > that I > have working right now. We are redesigning to convert to USB2.0 and to > add some features. The system is a low noise data acquistion system > using a pulse width modulator to control the sensor. The current > generation unit uses a ribbon cable with alternating signal/ground > connections for the backplane and the clock is being distributed as a > LVPECL differential signal using two 50 ohm coaxes and MCX connectors. I > am being pushed to go to an edge card connector to use for power, logic > signal and clock distribution (200 MHz clock). The connectors would be > put on a real backplane. I should note that the bus has as many as 18 > daughter cards and 1 master card. Some of the logic signals are > bi-directional (tri-state drivers from a spartan2e FPGA). My concerns > are two-fold. First is can the clock be distributed adequately over an > edge card (for example something like an AGP connector). Second, can I > get the bus working correctly for the data stuff. Note: the bus uses > standard lvttl (3.3v) for logic signals at a minimum pulse width of > about 40 ns. I am quite concerned that I not get into any signal > integrity issues. I tried to do something like this earlier and had > some problems. One concern is that the data strobe could ring and > generate a false data write condition. Does anyone have any experience > with this sort of thing? Especially with getting edge card connectors > with a known characteristic impedance? The bus has a total of 19 > connectors spaced at about .75" apart. Some of the connectors could be > left open and also there will be a sort stub on the individual cards > that must be terminated in some fashion. > > Thanks, > Theron Hicks You will probably have to have one 200MHz clock line per card to have any thing like controlled impedance in the clock distribution net.... PCWArticle: 58046
Hello All
I have a combinational logic circuit generating a number of waveforms
from the main clock input. There are a number of external inputs to
this circuit controlling the turning on and off of different outputs.
My problem is that I need a certain timing relationship between four of
the outputs.
I realise that normally to obtain a given timing relationship one would
use synchronous logic. But in this case as I require signals with the
same frequency as the main clock I must use combinational logic.
From the output of my logic simulator I am seeing some issues which
confuse me:
(a) Different logic gates have different delays, A NOT has less delay than
an OR gate. May be this should have been obvious to me. Is it correct?
(b) If I add a gate to create a delay, it seems to be getting optimised out.
Is there some way to stop a gate added for this purpose from being removed?
Thanks for all assistance in advance.
Denis
Article: 58047Thanks... I guess there are features in VHDL 93 that I have not been aware of. I'll have to read up and give them a try. CRS Mike Treseler wrote: > Clyde R. Shappee wrote: > > Hi, Mike, > > > > Could please enlighten me on your usage > > > > integer'image(null_vec'left) > > It an integer, the left index of the vector. > > > What's it doing? Is image the function that Ben Cohen provides on his CD > > with his books? > > No. Standard VHDL. Supported by all the sim and synth tools I have tried. > > > What is integer' doing? type casting? > > No. It's a built in VHDL "attribute" , a kind of function. > > > Have I been asleep, or why don't I know about this from all of my reading. > > A lot of the cool parts of VHDL-93 were neglected, because > they didn't work with every version of every tool. > They now work with most versions of most tools, so > feel free to use them. > > -- Mike TreselerArticle: 58048
I've been unable to find what you are talking about on burchED website (no schematics). "Spam Hater" <spam_hater_7@email.com> wrote in message news:dir2hvkbr1lnbkrdb2gm1dpb8slmd6impf@4ax.com... > > I don't think you want to do that. > > The proper way to do this is to create the symbol with heterogenous > parts; you make each sub-symbol match what the circuit is doing. > > I make part-A have the power and ground pins. Part-B has the > configuration and JTAG pins. Parts C through X are specific to the > design. > > Take a look at the way Tony did it: www.burched.com > > SH7 > > On Sun, 13 Jul 2003 01:00:50 -0400, "..:: Gabster ::.." > <gabsterblue@hotmail.com> wrote: > > >Hi, > > > >If someone know where I could find the orcad capture symbol for the XC2S300E > >in PQ208 package it would save me a lot of trouble and time. > > > >Thanks, > >Gabriel > > >Article: 58049
> If someone know where I could find the orcad capture symbol for the XC2S300E > in PQ208 package it would save me a lot of trouble and time. You'll find an easy technique for making any large OrCAD symbol, which I've used for Spartan IIEs, at Philip Freidin's fpga-faq.com: http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htm --Mike
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