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Try this:
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port( Load: in std_logic;
Rst: in std_logic;
LED: out std_logic_vector(0 to 7));
end counter;
architecture behaviour of counter is
begin
cnt : process(Rst, Load)
variable count : std_logic_vector(7 downto 0);
begin
if (Rst = '1' then) then
count := "00000000";
else if (Load'event and Load='1') then
count := count + 1;
end if;
LED <= count;
end process cnt;
end behaviour;
Now make sure that Load is 'locked' to a clock input on the FPGA, or
you'll probably get complaints of a logic line driving clock inputs.
Try using something like:
attribute LOC : string;
attribute LOC of signal Load : signal is "pin number";
Every time that a rising edge of Lock occurs, the variable count is
incremented. LED will be loaded with the value of count each time the
process 'runs' (I assume this is what you want?).
Georges Konstantinidis wrote:
> What do you mean by saying "asserted"?
> "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de
> news:9a2c3a75.0401301451.70df14a6@posting.google.com...
>
>>"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in
>
> message news:<401ab556$0$777$ba620e4c@news.skynet.be>...
>
>>>Dear all
>>>I'm deseprately trying to make an asynchronous counter to count the
>
> number
>
>>>of inputs I have on a pin. I also want a reset input.
>>>I copied the last version of my code at this e-mail .
>>>The synthesis looks good but an error comes at the implementation
>
> design. I
>
>>>don't kow to to do any more.
>>>Thank you for fixing my bugs, Georges.
>>>
>>>
>>>library ieee;
>>>use ieee.std_logic_1164.all;
>>>
>>>entity counter is
>>> port(Load, Rst: in std_logic;
>>> LED: out std_logic_vector(0 to 7)
>>>);
>>>end counter;
>>>
>>>architecture behaviour of counter is
>>> signal Qreg: std_logic_vector(0 to 7);
>>>
>>>begin
>>> process(Rst, Load)
>>> begin
>>> if Rst = '1' then -- Async reset
>>> Qreg <= "00000000";
>>> elsif Load='1' then
>>> Qreg<=Qreg+1;
>>> end if;
>>>
>>> end process;
>>>
>>> LED <= Qreg;
>>>
>>>end behaviour;
>>
>>Why do you want to do an async counter? No clock available?
>>
>>What is the implementation error? (Actually, I know what it is -- but
>>I want to know what you think it is.)
>>
>>Think about:
>>
>>What happens if neither Rst nor Load are asserted?
>>
>>--a
>
>
>
Article: 65551Dear colleagues, I need to find out that which verification tool would be better (overall) for the (Co)-Verification of the SoC/ASIC. We are thinking of making comparison between Seamless and Quickturn/Cadence product i.e. Cobalt. I know Cobalt has certain benefits such as: faster speed, Higher capacity. But still I need to know the following: - complexity in setting-up the environment (Seamless&Specman both) - User friendly - Nature of the results (% wrong values in result) - Effort required to make the environment working for simulation - Whether valid for synchronous designs only or more - Debug capability I will really appreciate help from the gurus of the design/verification community. Best regards, rajanArticle: 65552
Andrew Greensted <ajg112@ohm.york.ac.uk> wrote: : Thanks for the help. : Just to get things going, I've (grumblingly) gone for the windows : approach. Tech Support at Xilinx basically said this was the only option : available until ISE6.2. Lets hope that's soon. : For those who want to know, the links from Uwe that might help were: : http://www.nahitech.com/nahitafu/naxjp/naxjp-e.html : Can do svf playing : http://www.asics.ws/tools/ljp.c.gz : Writes bit streams directly, but needs a little hacking if you've got a : complex JTAG chain. I think Rudolf will be glad to hear those tricks needed. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65553
Jean Nicolle <j.nicolle@sbcglobal.net> wrote: : > You can use Iverilog for Xilinx too. And Cver also for both. Cver alos : knows : > about SDF and can be use for post layout simulation. : Sounds interesting. : Here, right? : http://www.pragmatic-c.com/commercial-cver/cver.htm : It doesn't seem available for free anymore though, even for non-commercial : use. There's a GPL-Cver version -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 65554
chuk wrote: > Can anyone recommend a suitable clocking circuitry, crystal or clock > component for clocking an fpga at 100MHz. Thanks Besides a straight Quartz Oscillator, available with HCMOS output, the newer parts have internal PLLs that allow you to feed them with 20 to 50MHz or so. Otherwise there are PLL chips such as the Cypress CY27EE16 plus many more. Micrel also comes to my mind. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 65555
hi all:
I am using Xilinx Virtex2 V6000 BF957 , ISE 5.1.03i.
Now I have met hold timeing violation after PAR.The error message is like
below:
TIMESPEC TS_CLKA = PERIOD CLKA_grp 60 ns HIGH 50% ;
TIMESPEC TS_CLKB = PERIOD CLKB_grp 60 ns HIGH 50% ;
TIMESPEC TS_CLKA_TO_CLKB = FROM CLKA_grp TO CLKB_grp 60 ns ;
Data path delay : 1.752 ns
Source clock : CLKA ; Destination clock CLKB
Clock Skew : 2.789 ns
Well , both CLKA and CLKB are global clock, they have the same frequence
and the same phase.
Three methods I could think out to correct this problem :
1) tp longer the data path ,
in pratice, the ISE should have known this , however my resources
usage is up to 95%, could this be the reason that the tool
failed to longer the data path to meet this timing constraint ?
2) to reduce the clock skew :
both clock are global global clock ,and have the same frequeces, but how
to write constraints to let the tool reduce the clock skew?
3) use only one clock with clock enable .
Well , this design is too large , and the worse is that most of the RTL
is not written by me , doing this really takes time .
I am looking foward to your response , any suggestion will be highly
appreciated!
--
BestRegards
Black Huang
Article: 65556Jean Nicolle wrote: > Hi all, > > I tried to summarize the differences in a table. > http://www.fpga4fun.com/table.html > > Sorry about the link, it wasn't easy to duplicate the table in text form for > this posting. > > Things I'd be interesting to hear about: > 1. is the info accurate? > 2. did I miss important features that differentiate the 2 software? (without > getting into details, these are big software...) > > The table is intended as a beginner's guide to FPGA's software. > Thanks for any help/comments. Thanks, that is great. A minor note : AHDL is standing for Altera Highlevel language. AFAIK, the free version only supports Megawizard function to be output in AHDL. Some pricetags would help too. The license restrictions would also be of interest. AFAIK, the Quartus2 free license is 90 or 180 days. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 65557
Hi all! I just started to use an apex-board with nios-softcore and want to write some programs using the plugs-library in c++! I've already done some experiments and have two questions: 1. I would like to know if using c++ is okay or if there are any backdrops (speed, size, ...)? 2. I was not able to put c++ together with the plugs library. The compiler has no problems but the linker marks all calls to that library as not resolveable (with standard c there is no such problem)! Is anyone using this combination? Do I have overlooked anything? TIA g.k.Article: 65558
BrakePiston <brakepiston@REMOVEyahoo.co.uk> wrote in message news:<gsdi109gelo848s1n8jo9nh7ge3in3d6qh@4ax.com>... > Hi there, a question about VPR: > > If I have the output of the placement and the routing, how can I see > them on screen without having to recompute it all? > > Thanks!! Unfortunately, you can't just display an existing routing in VPR. The best you can do is read the placement back in, re-route it, and then look at it. Use -route_only -route_chan_width <int> to skip placement, and route only at one channel width. If you used a binary search to find the minimum channel width in your first run, you'll have to remember what the minimum channel width was if you want to route again at that width (or that width +20%, which is commonly done). This will be quite a lot faster than re-placing and re-doing a binary search, but not as fast as just reading the routing back in from the .r file. That would be a handy feature, but I never got around to writing it before I graduated. Regards, Vaughn AlteraArticle: 65559
Shiraz, Idle speculation on the part of over-anxious authors? Austin Shiraz Kaleel wrote: > While waiting for the next announcement.... > perhaps some Xilinx person could answer these questions? > > Crista Souza's and Ron Wilson's piece in EETimes says in > the final paragraph: > > The column-based approach means that IP companies > that either license to Xilinx or want to be acquired will > **now have precise physical constraints for how to incorporate > their IP into Xilinx FPGAs**. Initially, that will whittle down > the field of qualified vendors, but ultimately it will result > in higher-quality IP, analysts said. > > Whom should one contact to find out more about these precise > physical constraints? > > Will it require the IP companies to work with expensive ASIC > design and verification software, or will there be some new > software which has the parameters which the designers can use > already set up for the base platform and taking into account these > constraints? > > Thanks > > Shiraz. > > >Article: 65560
Massi wrote: > CAn anyone tell me why I got this message on ModelSim: > "Iteration limit reached. Possible zero delay oscillation. See the > manual." I think it is a problem with sensitivity lists. At least that's where I have seen this error. What happens is that the you have listet one of a process' output signals in the sensitivity list, so that when the process runs, it causes itself to run again. In theory this causes an infinete loop, but the simulator protects you against this by having an iteration limit. > Is not possible to instatiate a simple Latch on Fpga? Try this: process(clk, reset) begin if (reset = '0') then d_out <= '0'; elsif (rising_edge(clk) then d_out <= d_in; end if; end proces; > I am sure to instante a latch because I have veruified on the netlist > in Synplify! and on the Designer netlist a Dlatch has been > implemented! > > Is it only a problem in the use of a Simulator? It may be, but it sort of sounds like you are doing something like implementing the latch with and gates and stuff, like you would in a schematic program, at the most basic level. This is not the best way to do it. -- AndersArticle: 65561
Austin Lesea <austin@xilinx.com> wrote in message news:<bvbamr$eet1@cliff.xsj.xilinx.com>... > Martin, > > Excellent point. If the unit is reconfigured (doesn't even have to be > powered off) it does not change the probability, but it will prevent > upsets from acumulating bit flips (lessening probability of functional > fail), as well as lessening the time of the outage, or the probability > that an outage is even noticed. > > Austin > > > > Martin Euredjian wrote: > > "Austin Lesea" wrote: > > > > > >>mean time to fail 4.2 years (approx). > > > > > > So, if the product in question is not operating 24/7 (powered on/off on a > > daily basis or when it gets used) the failure in question is as good as > > non-existent? > > > > Thanks for your help Guys, With your help, our franchise supplier has agreed to accept the devices in return for credit. We were also fortunate enough to find an independant supplier with unaffected Lot Numbers. Thanks again. -EmileArticle: 65562
Well, I forgot to mention that both CLKA and CLKB are derived from a clk named CLKIN.In practice, CLKA and CLKB are almost the same,the only difference is that when in power down mode the CLKB is not generated! -- BestRegards BlackShark Huang "BlackSim" <mini_monkey@163.net> wrote in message news:bvllaa$u4p2l$1@ID-199450.news.uni-berlin.de... > hi all: > I am using Xilinx Virtex2 V6000 BF957 , ISE 5.1.03i. > Now I have met hold timeing violation after PAR.The error message is like > below: > > TIMESPEC TS_CLKA = PERIOD CLKA_grp 60 ns HIGH 50% ; > TIMESPEC TS_CLKB = PERIOD CLKB_grp 60 ns HIGH 50% ; > TIMESPEC TS_CLKA_TO_CLKB = FROM CLKA_grp TO CLKB_grp 60 ns ; > > Data path delay : 1.752 ns > Source clock : CLKA ; Destination clock CLKB > Clock Skew : 2.789 ns > > Well , both CLKA and CLKB are global clock, they have the same frequence > and the same phase. > Three methods I could think out to correct this problem : > 1) tp longer the data path , > in pratice, the ISE should have known this , however my resources > usage is up to 95%, could this be the reason that the tool > failed to longer the data path to meet this timing constraint ? > 2) to reduce the clock skew : > both clock are global global clock ,and have the same frequeces, but how > to write constraints to let the tool reduce the clock skew? > 3) use only one clock with clock enable . > Well , this design is too large , and the worse is that most of the RTL > is not written by me , doing this really takes time . > > I am looking foward to your response , any suggestion will be highly > appreciated! > > -- > BestRegards > Black Huang > >Article: 65563
"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401c1026$0$13244$ba620e4c@news.skynet.be>... > What do you mean by saying "asserted"? "Asserted" means "put into the active state." It's a very common term. It's useful because it nicely ignores the detail of whether the signal is active low or active high. --aArticle: 65564
Thanks for the info. "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de news:9a2c3a75.0402020916.391b9ce6@posting.google.com... > "Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in message news:<401c1026$0$13244$ba620e4c@news.skynet.be>... > > > What do you mean by saying "asserted"? > > "Asserted" means "put into the active state." > > It's a very common term. It's useful because it nicely ignores the > detail of whether the signal is active low or active high. > > --aArticle: 65565
Hello Andrew, I was endeed using a "normal I/O port" which is synchronous or asynchronous according to the datasheets. I should be able to use it. Or I miss something. I found also a template in ISE called "debounce circuit" which seems to work. In any case I will also try what you said Thanks everyone for you cooperation, Georges. "Andrew Greensted" <ajg112@ohm.york.ac.uk> a écrit dans le message de news:bvlerm$crt$1@pump1.york.ac.uk... > Try this: > > library ieee; > use ieee.std_logic_1164.all; > > entity counter is > port( Load: in std_logic; > Rst: in std_logic; > LED: out std_logic_vector(0 to 7)); > > end counter; > > architecture behaviour of counter is > begin > > cnt : process(Rst, Load) > > variable count : std_logic_vector(7 downto 0); > > begin > > if (Rst = '1' then) then > count := "00000000"; > else if (Load'event and Load='1') then > count := count + 1; > end if; > > LED <= count; > > end process cnt; > > end behaviour; > > Now make sure that Load is 'locked' to a clock input on the FPGA, or > you'll probably get complaints of a logic line driving clock inputs. > Try using something like: > > attribute LOC : string; > attribute LOC of signal Load : signal is "pin number"; > > Every time that a rising edge of Lock occurs, the variable count is > incremented. LED will be loaded with the value of count each time the > process 'runs' (I assume this is what you want?). > > > Georges Konstantinidis wrote: > > What do you mean by saying "asserted"? > > "Andy Peters" <Bassman59a@yahoo.com> a écrit dans le message de > > news:9a2c3a75.0401301451.70df14a6@posting.google.com... > > > >>"Georges Konstantinidis" <georges_konstantinidis@hotmail.com> wrote in > > > > message news:<401ab556$0$777$ba620e4c@news.skynet.be>... > > > >>>Dear all > >>>I'm deseprately trying to make an asynchronous counter to count the > > > > number > > > >>>of inputs I have on a pin. I also want a reset input. > >>>I copied the last version of my code at this e-mail . > >>>The synthesis looks good but an error comes at the implementation > > > > design. I > > > >>>don't kow to to do any more. > >>>Thank you for fixing my bugs, Georges. > >>> > >>> > >>>library ieee; > >>>use ieee.std_logic_1164.all; > >>> > >>>entity counter is > >>> port(Load, Rst: in std_logic; > >>> LED: out std_logic_vector(0 to 7) > >>>); > >>>end counter; > >>> > >>>architecture behaviour of counter is > >>> signal Qreg: std_logic_vector(0 to 7); > >>> > >>>begin > >>> process(Rst, Load) > >>> begin > >>> if Rst = '1' then -- Async reset > >>> Qreg <= "00000000"; > >>> elsif Load='1' then > >>> Qreg<=Qreg+1; > >>> end if; > >>> > >>> end process; > >>> > >>> LED <= Qreg; > >>> > >>>end behaviour; > >> > >>Why do you want to do an async counter? No clock available? > >> > >>What is the implementation error? (Actually, I know what it is -- but > >>I want to know what you think it is.) > >> > >>Think about: > >> > >>What happens if neither Rst nor Load are asserted? > >> > >>--a > > > > > >Article: 65566
The integrator is based on the equation q=q+d. If it is a simulation problem in Simulink, make sure your simulation parameters (i.e. Solver Options, Single tasking mode etc.) and sampling rate for your source block are set correctly. There is an design example of a CIC filter which shows you how the integrator block can be incorporated into your design. The design is located in the following directory: <installation_path>\DSPBuilder\designexamples -HS hneoh@altera.com Jacob@jacob-s.net (Jacob Sørensen) wrote in message news:<2n4fzdvoi36.fsf@jacob-s.net>... > Hi > > Just wanted to here if anyone has an idea to what I am doing wrong. > > I can not get the integrator and delay components to work in the DSP > builder. > > All the Arithmetic and gates blocks I use, works well, and the FIFO > storage element workd well too. > > Any suggestions are most welcome. > > /Jacob > -- > > Msg. From Jacob Soerensen > jacob@jacob-s.net > http://jacob-s.net > > Nothing in nature is random ... > A thing appears random only through the incompleteness of our > knowledge. Spinoza, Ethics IArticle: 65567
> > I have now seen your posting and you are right. However, how widely > > available is this information? > it is available to ANYONE who has installed Quartus on their machine > just look at the libraries - I needed some 30 minutes to "derive" this > information. > as I dont have any Cyclone device or board, I can not verify in the hardware > what the asmiblock ports actually do, but this is the way NIOS does it, and > it is available for user logic, so it should be used. > A promise - if any one is kind to support openchip with Cyclone target board > I will instantly check it out how to access the ASMI port from user logic > and > publish this information, keeping special "thanks" notice to the donator of > the > board - dallaslogic are you listening ? :) > ok, promise is promise, I possible do it sooner or later, if I dont have > board > handy then possible later as I have some other things also in que. > antti Well found Antti, I had a good dig around Quartus and the SOPC installation and missed this. I also asked an Altera FAE could this be done, he checked with the States and the answer was... "Response from Altera is- No the only ASMI component that we have contains an Avalon interface. You could copy the asmi VHDL component from a Nios project to a new project that does not contain a Nios core and the customer could access the component with their own logic. However, this is not supported by Altera and the customer would need to do this at their own risk" If the cyclone_asmiblock works it'll be much simpler than what they've suggested. I'll try it on my Cyclone PCI board if I get time, but that's not likely to be in the next week or two. Good work. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 65568
Rene Tschaggelar <none@none.net> wrote in message news:<a1a691870ee18d1408d46636e8d0500a@news.teranews.com>... > Jean Nicolle wrote: > > Hi all, > > > > I tried to summarize the differences in a table. > > http://www.fpga4fun.com/table.html > > > > Sorry about the link, it wasn't easy to duplicate the table in text form for > > this posting. > > > > Things I'd be interesting to hear about: > > 1. is the info accurate? > > 2. did I miss important features that differentiate the 2 software? (without > > getting into details, these are big software...) > > > > The table is intended as a beginner's guide to FPGA's software. > > Thanks for any help/comments. > > Thanks, that is great. > A minor note : AHDL is standing for Altera Highlevel language. > AFAIK, the free version only supports Megawizard function to > be output in AHDL. > > Some pricetags would help too. The license restrictions would > also be of interest. > AFAIK, the Quartus2 free license is 90 or 180 days. > > Rene Hi, This is a correction to Rene's posting. The Quartus II 3.0 Web Edition license duration is for 180 days, and can be renewed as many times as needed from the web, i.e. there is no need to upgrade to a full subscription at the end of the 180 days. The Megawizard Plug IN Manager in the Quartus II 3.0 Web Edition provides output in VHDL, Verilog and AHDL. - Subroto Datta Altera Corp.Article: 65569
Allan, I believe that the code you referenced is called "Vector bit-select and part-select addressing". The XST User Guide does state support of "Array bit-select and part-select" which I believe is different than the code you mentioned below. XST does not support the addressing scheme [4*j +: 4] that you mentioned. best regards Steve Allan Herriman wrote: >On Fri, 23 Jan 2004 00:02:19 +1100, Allan Herriman ><allan.herriman.hates.spam@ctam.com.au.invalid> wrote: > > > >>Hi, >> >>Does anyone know if XST 6.1.3 supports the "indexed part select" >>feature of Verilog 2001? (It's in section 4.2.1 of the LRM.) >> >>The Xilinx documentation states explicitly that it does support this >>feature, yet when I try to use it, I get this error message: >> >>ERROR:Xst:850 - foo.v line 134: Unsupported . >> >>Example code: >> >>reg [7:0] bar; >>wire [31:0] foo; >> >>genvar j; >>generate >> for (j=0; j<8; j=j+1) begin : label >> always @(posedge clk) >> // error on next line: >> bar[j] <= &foo[4*j +: 4]; >> end >>endgenerate >> >>Is there something special I have to do to enable 2001 support? >> >>Thanks, >>Allan. >> >> > > >The Xilinx support guy suggested this (inappropriate) code as a >workaround, then closed the case before I'd had a chance to respond. >:( > > > >module test_module(bar,foo,clk); > > >output [31:0] bar; >input [31:0] foo; >input clk; > >reg [31:0] bar ; >wire [31:0] foo ; > > > >genvar j; > >generate >for (j = 0 ; j < 8 ; j = j + 1) >begin : label >always @ (posedge clk) >bar[j] <= &foo[4*j + 2] ; > >end >endgenerate >endmodule > > >Regards, >Allan. > >Article: 65570
I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The timing analyzer reports the clock period to be below 19ns. However, in practice, only one device out of 3 works at this speed. Two others were happy when I slowed the clock to 45 MHz (I didn't try any intermediate frequencies). The design basically consists of a 3rd party IP core, for which I don't have a source (I believe it was designed in schematic), some state machines, a bus interface and some Coregen memories. The bus runs at slower clock, but it is fully decoupled from the IP core (through the memories). The IP core is a fully synchronous design according to its author. The clock comes directly from an external crystal oscillator. I tried looking at unconstrained paths in the timing analyzer, but couldn't see anything suspicious... Any ideas to where to look? Thanks, /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65571
Antti Lukats wrote: >>>Thanks, that is great. >>>A minor note : AHDL is standing for Altera Highlevel language. >>>AFAIK, the free version only supports Megawizard function to >>>be output in AHDL. >>> >>>Some pricetags would help too. The license restrictions would >>>also be of interest. >>>AFAIK, the Quartus2 free license is 90 or 180 days. >>> >>>Rene >> >>Hi, >> >> This is a correction to Rene's posting. The Quartus II 3.0 Web >>Edition license duration is for 180 days, and can be renewed as many >>times as needed from the web, i.e. there is no need to upgrade to a >>full subscription at the end of the 180 days. The Megawizard Plug IN >>Manager in the Quartus II 3.0 Web Edition provides output in VHDL, >>Verilog and AHDL. >> >>- Subroto Datta >>Altera Corp. > > > Dear Altera Corp, > > could you please also confirm is SOPC Builder that is bundled with Altera > Quartus II 3.0 Web Edition useable at all or not. > > so far all our attempts todo something with it have failed: > NIOS is supplied (white icon?), after requesting NIOS evaluation license and > installing it, nothing changes, the NIOS in SOPC is not enabled. > and if there is no Avalon master then the SOPC doesnt do anything at all. > SOPC list DF6811 as Avalon master, so obtained eval license for DF6811 (from > provider DCD) - unfortunatly there is some problem as per DCD on Altera side > so DF6811 is not enabled in SOPC, so no way. > No Processor enabled, no avalon master no system can be built :( > > I dont get it - if SOPC is included in free edition there should be > something that can be done with it ??? > > In previous versions of Altera free software I think the NIOS evaluation was > possible, unfortunatly I had very little time then and now this older > version probably would not recon the new license. > > Ok, the long story short - is there any way to evaluate NIOS without paying > up front ? There at least were NIOS kits, meaning some FPGA, Stratix, or Cyclone hardware together with a full license upgradeable withing a year to the latest version. At around 450$ they were a bargain, considering the hardware. You're never doing your own hardware for that little. I wasn't able to run the kit due to configuration problems and lack of time. So I cannot comment any further yet. ReneArticle: 65572
I would suggest running your internal clock signal out to a pad and probing it. That was how I determined I needed to run DCI on some of my input pads instead of the default TTL. Sometimes the DCM would lock to the wrong frequency, but it would always get it correct when I slowed the frequency down. It ended up being reflective noise on the line which the DCI cleared up. As for running below specs, as far as I understand that should only happen when the incoming power or temperature are out of spec. "MM" <mbmsv@yahoo.com> wrote in message news:bvmaua$u760t$1@ID-204311.news.uni-berlin.de... > I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The > timing analyzer reports the clock period to be below 19ns. However, in > practice, only one device out of 3 works at this speed. Two others were > happy when I slowed the clock to 45 MHz (I didn't try any intermediate > frequencies). The design basically consists of a 3rd party IP core, for > which I don't have a source (I believe it was designed in schematic), some > state machines, a bus interface and some Coregen memories. The bus runs at > slower clock, but it is fully decoupled from the IP core (through the > memories). The IP core is a fully synchronous design according to its > author. The clock comes directly from an external crystal oscillator. I > tried looking at unconstrained paths in the timing analyzer, but couldn't > see anything suspicious... > > Any ideas to where to look? > > Thanks, > /Mikhail > > -- > To reply directly: > matusov at square peg ca > (join the domain name in one word and add a dot before "ca") > >Article: 65573
Brannon, "Brannon King" <bking@starbridgesystems.com> wrote in message news:bvmcge$q3l@dispatch.concentric.net... > I would suggest running your internal clock signal out to a pad and probing > it. That was how I determined I needed to run DCI on some of my input pads > instead of the default TTL. Sometimes the DCM would lock to the wrong > frequency, but it would always get it correct when I slowed the frequency > down. I am not using the DCM at all... The internal clock is what comes in and it is only 50 MHz. > up. As for running below specs, as far as I understand that should only > happen when the incoming power or temperature are out of spec. That doesn't seem to be the case. The temperature is room or slightly higher, and the core voltage I measured at 1.506V... /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")Article: 65574
MM, The most likely cause is that your design does not, in fact, meet timing. This comes about by many ways, most usually a bug in the constraints, or in the design itself. Sorry that it isn't some bizarre unheard of problem, but I can only guess based on the thousands of cases that come through. Common problems: use of the wrong clock edge, design did not specify global resources so clocks are being routed using general interconnect, unconstrained paths leading to inefficient placement by the tools. Multi-cycle constraints confusing the tool and leading to no constraints at all. Austin MM wrote: > I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The > timing analyzer reports the clock period to be below 19ns. However, in > practice, only one device out of 3 works at this speed. Two others were > happy when I slowed the clock to 45 MHz (I didn't try any intermediate > frequencies). The design basically consists of a 3rd party IP core, for > which I don't have a source (I believe it was designed in schematic), some > state machines, a bus interface and some Coregen memories. The bus runs at > slower clock, but it is fully decoupled from the IP core (through the > memories). The IP core is a fully synchronous design according to its > author. The clock comes directly from an external crystal oscillator. I > tried looking at unconstrained paths in the timing analyzer, but couldn't > see anything suspicious... > > Any ideas to where to look? > > Thanks, > /Mikhail >
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