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Messages from 69850

Article: 69850
Subject: Re: Never right, always room for improvement
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 22 May 2004 15:12:38 +1200
Links: << >>  << T >>  << A >>
john jakson wrote:
<Snip>
> I suspect that the several ASIC MT cpus that have recently come along
> for the wireless set could well have the best int response esp 1 that
> runs 8 threads at 250MHz (or was it 400MHz) because the threads run
> all the time every 8th cycle. ANd these cpus don't have context to
> swap since they have N contexts in ram.

The Ubicom part claims 0 or 1 cycles.

> Technically Transputers don't have interrupts, thats too low a level
> of looking at them, but they do service events with an incredibly
> quick response for a variety of reasons but that was at 25MHz and
> 15yrs ago.
> 
> Now the R3 cpu also being an multithreaded (MT) cpu (and also now
> running baby code BTW in C model) could designate 1 of its 16 threads
> to poll some HW and take the event home. That would mean about 20-50
> cycles of computation might pass before Pn noticed it had to do some
> work. If Pn can find away to stay active in the IX engine without
> branching (which causes process swap round robin style) then it could
> notice an event in <4cycles. I don't think I will add support for
> always stay active process. Now when the process thats does service an
> interupt does get it's turn, it will have no registers to swap but it
> may have to do some cache misses while workset becomes reloaded but
> thats transparent to MT. If it pans out at 250MHz in V2Pro it may or
> may not have fastest int response. It will however have the most
> throughput of any FPGA cpu bordering on 1.3clock Freq from the sim
> traces. It loves branches and transfers and swapping, its the nature
> of the MT beastie.

  In a hard-timesliced CPU, I can see two schemes for handling 
interrupts, that would need sightly different hardware (no problem in a 
FPGA-CPU:)
  It is a CPU structure that would seem to fit well into FPGA resource.

- First scheme allows any/(first) available free timeslot to an 
interrupt thread. This allows good granularity, but does not give the 
smallest possible INT response.

- Other scheme is carefull to leave every second time-slot free, for
possible INT. INT response/context sw is MUCH faster (1-2 clocks), but
cost is that other threads cannot have more than 50% of the CPU.
  With time-sliced CPUs threads have zero time-crosstalk, but the peak
CPU usage for any single thread is lower.

  in most embedded applications, bounding the slowest path, and reducing 
jitter, can matter more than fastest-possible-speed over a short 
distance numbers.

  -jg


Article: 69851
Subject: Re: Never right, always room for improvement
From: "Jan Gray" <jsgray@acm.org>
Date: Sat, 22 May 2004 05:59:10 GMT
Links: << >>  << T >>  << A >>
> lowest interrupt latency of any soft processor core

Interesting.  Friends, what *is* this vaunted MicroBlaze interrupt latency
(in cycles or ns)?  Is there some special mechanism, or is it simply clean
living?

(By the way, interrupt servicing (interrupt and return from interrupt)
completes in as few as 6 cycles on the good old xr16 soft processor core.)

Thanks,
Jan Gray
Gray Research LLC



Article: 69852
Subject: Re: How to handle different proccessing speeds?
From: Guenter Dannoritzer <dannoritzer@web.de>
Date: Sat, 22 May 2004 11:24:11 +0200
Links: << >>  << T >>  << A >>
Hi John,


john wrote:
> Hi,
>     I am a kind of newbie too. But this much I know. IF ever u need to
> interface two different clock domains u use an asnchronous FIFO. Now
> consider a deep enough FIFO for ur application. Let whatever be written in,
> it can be read out at different clock rate. Again I'm a newbie and there can
> be better suggestions.
> --
> Joji John ( nansung444@yahoo.com)

[snip]

Thanks for that pointer, I found some code and will study it.

Guenter

Article: 69853
Subject: FPGA Board with Flash Memory
From: "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg>
Date: Sat, 22 May 2004 17:44:52 +0800
Links: << >>  << T >>  << A >>
SGVsbG8gYWxsLA0KIA0KSSBhbSBsb29raW5nIGZvciBhIEZQR0EgYm9hcmQgKHByZWZlcmFibHk6
IFhpbGlueCBTUEFSVEFOIDEwMGstMzAwayBnYXRlcykgd2l0aCBmbGFzaCBtZW1vcnkgYXR0YWNo
ZWQgb24gdGhlIGJvYXJkIGl0c2VsZiB0byBzdG9yZSB0aGUgYml0IGZpbGUuDQogDQpBbnlvbmUg
Y2FuIGhlbHAgbWUgb3IganVzdCBnaW1tZSB0aGUgVVJMID8NCiANClRoYW5rcy4NCiANCi1CYXN1
a2ktDQogDQo=


Article: 69854
Subject: Re: FPGA Board with Flash Memory
From: "Martin Maurer" <capiman@clibb.de>
Date: Sat, 22 May 2004 12:49:25 +0200
Links: << >>  << T >>  << A >>
Hello Basuki,

have a look at

http://www.trenz-electronic.de/prod/prodde6.htm     and their shop under
http://www.te-shop.de/   (but currently not reachable).

They have a spartan II board with onboard socket for flash (for bitstream).
If you need real flash and sram, they have an extension board for it.

Regards,

         Martin



Article: 69855
Subject: Re: Atmel Zigbee solutions
From: "Ulf Samuelsson" <ulf@atmel.nospam.com>
Date: Sat, 22 May 2004 13:09:25 +0200
Links: << >>  << T >>  << A >>


"Jon Beniston" <jon@beniston.com> skrev i meddelandet
news:e87b9ce8.0405191432.6b9cea2e@posting.google.com...
> > Each has their own uses...
> > Europe fought for 30 years to determine which should prevail:
> >
> >                 Catolicism  *OR*  Protestantism.
> >
> > Guess what ....
> >
>
> What? You're saying both ZigBee and Bluetooth are a waste of time?
>
> Cheers,
> JonB

No I am saying that discussing which standard is *best*, to determine
which should be dropped, is a waste of time because both will be here for
the foreseeable future.
Disussing where each standard fits best is OK.


-- 
Best Regards,
Ulf Samuelsson   ulf@a-t-m-e-l.com
This is a personal view which may or may not be
share by my Employer Atmel Nordic AB



Article: 69856
Subject: Re: I2C Slave
From: "S Ramirez" <simon-keyword-newsgroup1.3b6264@ragingpsycho.25th.com>
Date: Sat, 22 May 2004 11:50:39 GMT
Links: << >>  << T >>  << A >>
> > Hi!
> >
> > I am searching a synthesizable I2C Slave model in VHDL.
> > Does somebody know where I can find it?
>
> Did you check opencores.org?  That is always a good place to start.
> They have a lot of IO peripherals available.
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Be careful, though, Matija, the I2C slave core in OpenCores has significant
errors.  I used it and had to debug it to the point that I totally
synchronized it, with the exception of the microprocessor interface of
course, in order for it to work properly.  Unfortunately I cannot send you
this design, because all of my work belongs to my client company, as they
paid for my efforts.  The OpenCores designs apparently are someone's pet
academic projects that aren't really being used in the real world.  They
come close but no enchilada.

I don't know if you are using Xilinx, but they have a I2C core that I would
investigate if I were doing it over again.

Good luck.

Simon Ramirez, Consultant
Oviedo, FL  USA
Synchronous Design , Inc.
Xilinx XPERTS Partner



Article: 69857
Subject: Re: Never right, always room for improvement
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 22 May 2004 06:11:34 -0700
Links: << >>  << T >>  << A >>
Multiple embedded processors?

I built a Stratix design with 6 Nios' on it a long time ago. The
design from start to finish took less than half a day. Could have been
more if I had the space on the FPGA.

-- Pete

> Processors, plural.
> 
> I'm still right.
> 
> Austin
>

Article: 69858
Subject: Re: I2C Slave
From: "Matija" <matija.habek@fer.hr>
Date: Sat, 22 May 2004 15:37:29 +0200
Links: << >>  << T >>  << A >>
Hi!

Simon , can You send me your e-mail adress?I try to reply  You direct but
that don't work

Thanks

> Be careful, though, Matija, the I2C slave core in OpenCores has
significant
> errors.  I used it and had to debug it to the point that I totally
> synchronized it, with the exception of the microprocessor interface of
> course, in order for it to work properly.  Unfortunately I cannot send you
> this design, because all of my work belongs to my client company, as they
> paid for my efforts.  The OpenCores designs apparently are someone's pet
> academic projects that aren't really being used in the real world.  They
> come close but no enchilada.
>
> I don't know if you are using Xilinx, but they have a I2C core that I
would
> investigate if I were doing it over again.
>
> Good luck.
>
> Simon Ramirez, Consultant
> Oviedo, FL  USA
> Synchronous Design , Inc.
> Xilinx XPERTS Partner
>
>



Article: 69859
Subject: Re: FPGA Board with Flash Memory
From: Dave Vanden Bout <devb@xess.com>
Date: Sat, 22 May 2004 14:29:28 GMT
Links: << >>  << T >>  << A >>
"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in
news:Z6dbuF#PEHA.2168@exchnews1.main.ntu.edu.sg: 

> Hello all,
>  
> I am looking for a FPGA board (preferably: Xilinx SPARTAN 100k-300k
> gates) with flash memory attached on the board itself to store the bit
> file. 
>  
> Anyone can help me or just gimme the URL ?


http://www.xess.com/prod026.php3


SpartanII (not Spartan).  2 Mbit flash on the board that can be used for 
storing bitstreams or data.



>  
> Thanks.
>  
> -Basuki-



-- 
----------------------------------------------------------------
Dr. Dave Van den Bout
XESS Corp.
PO Box 33091
Raleigh NC 27636
Phn: (919) 363-4695
Fax: (801) 749-6501
devb@xess.com
http://www.xess.com


Article: 69860
Subject: OT: Electronics learner kit?
From: robison_m@crane.navy.mil (Zspider)
Date: 22 May 2004 07:42:51 -0700
Links: << >>  << T >>  << A >>
My daughter will be a high school junior next year.  Over the 
summer she is wanting to play with electronics in preparation
for an electronics engineering degree.  I thought about brute-
forcing our way through simple Ohm's Law stuff and then I
thought I'd use a simple radio circuit to work with amplification
and filters, and then do some simple 7400 digital stuff, but 
it will take me a lot of time to crank that all out from
scratch.  In the summer I don't have that kind of time.

Where can I find a good electronics learning kit?

Thank you, Michael

Article: 69861
Subject: Transputer on FPGA, was: Re: Never right, always room for improvement
From: "E.S." <emu@ecubics.com>
Date: Sat, 22 May 2004 10:41:53 -0600
Links: << >>  << T >>  << A >>
Tim wrote:

> and why are there so many transputer people in fpgaland?

May I rephrase it, and make a question out ot it ?
Are the any transputer loke-a-likes WORKING on an FPGA ?



Article: 69862
Subject: Re: XIlinx V2P7: DCM won't lock
From: Sean Durkin <smd@despammed.com>
Date: Sat, 22 May 2004 19:32:47 +0200
Links: << >>  << T >>  << A >>
Phil Hays schrieb:
> Output pins with heavy loads near the clock pins can add jitter to the
> input clock signal if they happen to switch near the clock edges.

> Are you resetting the DCM?  A reset (3 clock cyles or longer) after
> configuration and stable clock may be needed to get the DCM to lock
> reliably.
Yes, I am resetting them. Actually, I'm doing now what Austin suggested 
in another thread, i.e. continually checking if the DCMs have locked, if 
not reset them, wait for 10ms, and check again.

But the thing that puzzles me, is that both designs are more or less 
identical, the only difference being that in the second variant there is 
some logic added. The rest (output pins, input clock, the entire 
hardware) is identical.

cu,
Sean


Article: 69863
Subject: Re: XIlinx V2P7: DCM won't lock
From: Sean Durkin <smd@despammed.com>
Date: Sat, 22 May 2004 19:42:58 +0200
Links: << >>  << T >>  << A >>
Austin Lesea schrieb:

> John,
> 
> Couldn't have said it better.
> 
> Also, I would start a webcase with the hotline.
OK, I'll do that. But, as I said earlier, the thing that puzzles me, is 
that input clocks, output pins etc. are all identical in both designs. 
The only difference is in design B there is some more logic added, the 
rest is the same. Obviously that affects the locking/not locking of the 
DCMs... I've experienced something similar before, when I added a 
Chipscope-Core to the design, and as long as that was connected the DCMs 
wouldn't lock either. The only solution was to use a separate DCM to 
generate a clock for Chipscope.

But could the following help:

Assuming that the amount of logic connected to the output of a DCM does 
matter or some nearby output pins add jitter to the input clock, could I 
use a BUFGMUX at the output of the DCMs, and use the lock-output of the 
DCM as select-signal to switch between the DCM-output and GND? That way 
I could disable all logic in the FPGA until the DCMs are locked.

Until then it seems I have to configure the FPGA twice to get the design 
running.

cu,
Sean


Article: 69864
Subject: More fun with VHDL
From: "Chuck McManis" <devnull@mcmanis.com>
Date: Sat, 22 May 2004 17:59:07 GMT
Links: << >>  << T >>  << A >>
State machines and synchronization.

The background is that I'm working on this PWM unit that uses a serial shift
register to hold the pulse "width" data. The original code goes something
like:

  -- process to manage clocking in the data
  sr: process (sdata_in, sclock, reset) is
  begin
    if (reset = '1') then
        serial_data <= "00000000";
    elsif rising_edge(sclock) then
        serial_data <= sdata_in & serial_data(serial_data'length-1 downto
0);
    end if;
  end process;

  -- concurrent assignment of serial data out.
  sdata_out <= serial_data(0);

  -- process to manage pwm output
  pwm: process is (pwm_count) is
  begin
    if (pwm_count < serial_data) then
        pwm_out <= '1';
    else
        pwm_out <= '0';
    end if;
  end process;

Things that aren't here is that the architecture for this thing calls for a
current PWM count as input (same width as serial_data), pwm_out as output,
and our shift register, serial_data, defined with a signal define in the
behavioral section.

This works as I would expect, and I can clock in different bit streams and
get different wave forms. However, a couple of problems persist:

1) I don't get "full" PWM. This is because the pwm process is forced to use
either < or > If I want to support both 0% on (output stays low) and 100%
on, (output stays high), I need an additional statement to cover that.

I can modify pwm as follows:
  pwm: process is (pwm_count, serial_data) is
  begin
    if (serial_data = "11111111") then
        pwm_out <= '1';
    elsif (pwm_count < serial_data) then
        pwm_out <= '1';
    else
        pwm_out <= '0';
    end if;
  end process;

Assuming the original code inferred an 8 bit comparator, I'd guess the above
code would then infer an 8 bit and gate whose output is OR'd into the output
of the comparator (at least that is what I'd do). But it seems like I should
be able to save the two macrocells this is going to eat by changing the
logic of the inferred comparator to include an output of '1' when all inputs
are 1.

2) The second problem is that I would really like the pwm output to change
exactly on the period boundary. Now I started this with a simple state
machine where a new input set a latch to tell me to change, and then added
that into the sensitivity list of the pwm function like so:

  ld: process (serial_load) is
  begin
      if rising_edge(serial_load) then
          new_data <= '1';
      end if;
  end process;

  pwm: process is (pwm_count, pwm_data, new_data) is
  begin
    if (new_data = '1') and (pwm_count = "11111111") then
        pwm_data <= serial_data;
        new_data <= '0';
    elsif (pwm_data = "11111111") then
        pwm_out <= '1';
    elsif (pwm_count < pwm_data) then
        pwm_out <= '1';
    else
        pwm_out <= '0';
    end if;
  end process;


This is designed to create a simple state machine between the ld and pwm
processes such that if there is new data, then that data is loaded when the
count is full. However I'm getting errors trying to synthesize this.
Basically XST doesn't like the way I'm assigning new_data in different
processes (although as an engineer it makes sense to me, I'd like to infer
and R/S flip flop and have pwm_count & new_data drive its "R" input and
"serial load" drive its "S" input. Trying to use this:
    ld: process (serial_load) is
    begin
        if serial_load = '1' then
            new_data <= '1';
        end if;
    end process;

Leads to the case where holding serial load high through a full PWM cyle
would cause both R/S to be asserted. So I tried to infer something like a
modified T flip flop to set it on the clock edge. Thoughts anyone?

-- 
--Chuck McManis
Email to the devnull address is discarded
http://www.mcmanis.com/chuck/robotics/



Article: 69865
Subject: Re: More fun with VHDL
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sat, 22 May 2004 12:00:25 -0700
Links: << >>  << T >>  << A >>
Chuck McManis wrote:

> State machines and synchronization.
> 
> The background is that I'm working on this PWM unit that uses a serial
> shift register to hold the pulse "width" data. The original code goes
> something like:
> 
>   -- process to manage clocking in the data
>   sr: process (sdata_in, sclock, reset) is
>   begin
>     if (reset = '1') then
>         serial_data <= "00000000";
>     elsif rising_edge(sclock) then
>         serial_data <= sdata_in & 
>         serial_data(serial_data'length-1 downto 0);
>     end if;
>   end process;

OK. We are receiving and shifting in the pwm bitstream 
into parallel bytes.

Take sdata_in out of the sensitivity list and
you have a synchronous process that will
sim and synth the same way.

Hmmm. Why are we making bytes in the first place?
-_______--______----____-------_

Don't we just want to preset a counter
while the data is high and count down
while it is low?

 -- Mike Treseler



Article: 69866
Subject: Re: Transputer on FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 22 May 2004 17:09:06 -0400
Links: << >>  << T >>  << A >>
"E.S." wrote:
> 
> Tim wrote:
> 
> > and why are there so many transputer people in fpgaland?
> 
> May I rephrase it, and make a question out ot it ?
> Are the any transputer loke-a-likes WORKING on an FPGA ?

Interesting question.  I am giving some consideration to inserting my
own cpu into an FPGA to be programmed in Forth.  I remember the
Transputer architecture and instruction set as being well suited to
implementing a stack language as well as being rather minimal.  But I
can't find my copy of the instruction set reference manual.  Anyone know
where I can find a copy? 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 69867
Subject: Reg learning FPGA backend
From: sunilsreenivas2001@yahoo.com (sunil)
Date: 22 May 2004 15:56:50 -0700
Links: << >>  << T >>  << A >>
Hi All,
        I want to learn FPGA backend and synthesis which has become a
prerequisite for VLSI related jobs. I am proficient with VHDL frontend
and also with digital circuits.I am from india. Any suggestions on how
to learn FPGA backend (books/online/CDs/name of institutes (if you
happen to be from india)) would be extremely helpful as I am totally
clueless on how to take next step.
Thanks a zillion,
Sunil.

Article: 69868
Subject: Re: Transputer on FPGA
From: John Doty <jpd@whispertel.LoseTheH.net>
Date: Sat, 22 May 2004 17:27:21 -0600
Links: << >>  << T >>  << A >>
rickman wrote:

 > Interesting question.  I am giving some consideration to inserting my
 > own cpu into an FPGA to be programmed in Forth.  I remember the
 > Transputer architecture and instruction set as being well suited to
 > implementing a stack language as well as being rather minimal.  But I
 > can't find my copy of the instruction set reference manual.  Anyone know
 > where I can find a copy?

It's a stack machine, but its model of how to use the stack is 
fundamentally different from Forth's. The stack is very shallow and must 
be *empty* at every branch! It's designed for expression evaluation in 
Algol-like languages, nothing more.

The Transputer's intended strength is very fine-grained multitasking: 
since it has almost no execution context to save, context switching is 
very fast. They were also fairly radiation tolerant, so they were used 
for some space applications. I'm sitting here watching telemetry from 
HETE-2, which has four T805 CPU's on board.

In general, I would not recommend the Transputer architecture for most 
applications. It basically combines the disadvantages of register and 
stack machines. Its ratio of instruction/data accesses is very high 
compared to other architectures, leading to serious inefficiency when 
running ordinary serial code.

-jpd


Article: 69869
Subject: Re: Transputer on FPGA, was: Re: Never right, always room for improvement
From: johnjakson@yahoo.com (john jakson)
Date: 22 May 2004 16:29:55 -0700
Links: << >>  << T >>  << A >>
"E.S." <emu@ecubics.com> wrote in message news:<ZlLrc.4206$zs2.1848@fe39.usenetserver.com>...
> Tim wrote:
> 
> > and why are there so many transputer people in fpgaland?
> 
> May I rephrase it, and make a question out ot it ?
> Are the any transputer loke-a-likes WORKING on an FPGA ?

Not yet. Somebody else over in the Tp NG said they were going to clone
the thing wholesale for code compatibility but didn't say how or when
they would (a student I thinks).

Apart from me, I don't think anyone else has the inclination to try,
most people probably have a job, and the Tp has had enough trashing to
make alot of people stay away. And the complicated UK/US thing is
there too.


The MT core I am working on will likely get Tp scheduling and message
passing and more but it takes time. The core is only now running
simple threaded codes. Today it hit 100M cpu cycles on 16threads (the
same trivial code on all), but doesn't do much interesting yet till
more opcodes implemented. Its only been 3+ months since I started. I
have to go back and bring the Verilog back into sync with C RTL code
too. There are some big issues up ahead like the cache & TLB design,
sometimes MT helps alot, maybe not always.


Now I hope you'r not asking for a precise clone because as you must
know, FPGAs don't clone anything well for which they were not
originally intended for.

Anyway stick around to see posts on progress:)

regards

johnjakson_usa_com

Article: 69870
Subject: Re: Reg learning FPGA backend
From: "Jim Wu" <NOSPAM@NOSPAM.com>
Date: Sun, 23 May 2004 00:11:28 GMT
Links: << >>  << T >>  << A >>
Download free Xilinx ISE Webpack and go from there.

http://www.xilinx.com/products/design_resources/design_tool/index.htm

HTH,
Jim (jimwu88NOOOSPAM@yahoo.com Remove NOOOSPAM)
http://www.geocities.com/jimwu88/chips

"sunil" <sunilsreenivas2001@yahoo.com> wrote in message
news:d924fa71.0405221456.38c75acd@posting.google.com...
> Hi All,
>         I want to learn FPGA backend and synthesis which has become a
> prerequisite for VLSI related jobs. I am proficient with VHDL frontend
> and also with digital circuits.I am from india. Any suggestions on how
> to learn FPGA backend (books/online/CDs/name of institutes (if you
> happen to be from india)) would be extremely helpful as I am totally
> clueless on how to take next step.
> Thanks a zillion,
> Sunil.



Article: 69871
Subject: Altium FPGA board
From: "Chuck McManis" <devnull@mcmanis.com>
Date: Sun, 23 May 2004 00:51:12 GMT
Links: << >>  << T >>  << A >>
I just got the Altium flyer in the mail today and they are offering a free
Nanoboard (with the purchase of their overpriced CAD package :-) The
Nanoboard actually looks pretty cool, has anyone used one?


-- 
--Chuck McManis
Email to the devnull address is discarded
http://www.mcmanis.com/chuck/



Article: 69872
Subject: Re: OT: Electronics learner kit?
From: Ray Andraka <ray@andraka.com>
Date: Sat, 22 May 2004 22:22:54 -0400
Links: << >>  << T >>  << A >>
I got this one:
http://www.radioshack.com/product.asp?catalog%5Fname=CTLG&product%5Fid=28-280
for my son.  It looks pretty comprehensive.

Zspider wrote:

> My daughter will be a high school junior next year.  Over the
> summer she is wanting to play with electronics in preparation
> for an electronics engineering degree.  I thought about brute-
> forcing our way through simple Ohm's Law stuff and then I
> thought I'd use a simple radio circuit to work with amplification
> and filters, and then do some simple 7400 digital stuff, but
> it will take me a lot of time to crank that all out from
> scratch.  In the summer I don't have that kind of time.
>
> Where can I find a good electronics learning kit?
>
> Thank you, Michael

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 69873
Subject: Re: Transputer on FPGA
From: johnjakson@yahoo.com (john jakson)
Date: 22 May 2004 20:22:33 -0700
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<40AFC172.C49E27FA@yahoo.com>...
> "E.S." wrote:
> > 
> > Tim wrote:
> > 
> > > and why are there so many transputer people in fpgaland?
> > 
> > May I rephrase it, and make a question out ot it ?
> > Are the any transputer loke-a-likes WORKING on an FPGA ?
> 
> Interesting question.  I am giving some consideration to inserting my
> own cpu into an FPGA to be programmed in Forth.  I remember the
> Transputer architecture and instruction set as being well suited to
> implementing a stack language as well as being rather minimal.  But I
> can't find my copy of the instruction set reference manual.  Anyone know
> where I can find a copy? 
> 
> 
> -- 


The Transputer Instruction set is easy enough to find on the web, use
google to find a few portals with all the links, like classic old
comps, wotug, etc.

In c.s.transputer NG look for Ram and his home page and links, docs,
even OS stuff. The ISA also has a compilere writers guide to explain
it.

I never looked at it myself, never will, theres too many things I
never liked about it, byte encoding, and mostly because there are just
so many instructuions for what is supposed to be a simple cpu. later
on the whole kitchen sink fell into it, graphics rendering and so on.
Even related codes have odd hex codings, like they did a,b,c,  x,y,x
then realized later to put in d but right after z.

regards

johnjakson_usa_com

Article: 69874
Subject: Re: Reg learning FPGA backend
From: johnjakson@yahoo.com (john jakson)
Date: 22 May 2004 20:25:48 -0700
Links: << >>  << T >>  << A >>
sunilsreenivas2001@yahoo.com (sunil) wrote in message news:<d924fa71.0405221456.38c75acd@posting.google.com>...
> Hi All,
>         I want to learn FPGA backend and synthesis which has become a
> prerequisite for VLSI related jobs. I am proficient with VHDL frontend
> and also with digital circuits.I am from india. Any suggestions on how
> to learn FPGA backend (books/online/CDs/name of institutes (if you
> happen to be from india)) would be extremely helpful as I am totally
> clueless on how to take next step.
> Thanks a zillion,
> Sunil.

Just download the free Xilinx Webpack or Altera Quartus and start
learning, youl need 1Gb of HD space and 100MB download or so. Both
websites so full of stuff you'd easily miss it. You can try to get a
CD from marketing but they date very quickly.

regards

johnjakson_usa_com



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