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Hejsan, We created the system in Platform Studio (was unable to use BSB because we've got a custom board) and added the required components and ports according to the tutorial on http://www.eece.unm.edu/xup/ml300ppc405.htm A few modification were made but we are pretty sure we got this bit right. We reckon the main problem is that Platform Studio won't let us select "executable" under S/W Settings -> Mode. Well, actually it can be selected, but if you go "OK" and then check again it is back to "XmdStub". Is it the case that if XmdStub is selected, then the program will not execute without the debugger? How can this be changed? The program is included in the bitfile through the "Update Bitstream" option in XPS. Many thanks for any replies, > Tjena, > > Yes, The executable can be directly merged into the bitfile, if your executable is running from internal BRAM. > If you run out of external memory, you need to download executable to the external memory. > > How did you create your system? > Did you use the Base System Builder? > > Göran BilskiArticle: 70676
Hi, im currently trying to config a virtexII (xc2v2000) by the slave selectMap mode via a vme interface. the fpga react fine the stimuli on the prog_b signal (init goes low and back to to high ) then i set rdwr_b to low, present the first data byte (oxff) and set then cs_b to low the busy signal is low also cclk is low the i generate one cclk cycle 010 (very slow rate, 8µs high periode ) shortly before the cclk signal goes again to low, the busy signal is be asserted (high) by the fpga and will only be de-asserted after deselect the fpga (cs_b = high) the configuration fails Any idea to solve this problem ? Regards andreasArticle: 70677
marco p. wrote: > Hi, > I have a problem with a Dialogic board "DM/IP301-1e1-PCI". > I installed that board in a Piv 1.6Ghz Mainboard D845WN and I can't do > it starts. The board's power requirements are 22.5W @ 5V, and using PC > Wizard I see that the PCI slot used by the Dialogic board has this > description: "In Use (32-bit) 3.3v". > Is this a problem? > Does the board fail to start by this reason? > Can I make the board and the Mainboard compatible? > thanks! > Bye PCI slots are either 3.3V or 5V PCI boards are 3.3V, 5V, or universal (fits in both 3.3V or 5V slots) PCI slots and cards are mechanically keyed to prevent plugging cards into incompatible slots. Even 3.3V slots provide 5V power supply. So the dialogic board must be a 3.3V or universal card or it would not fit in the 3.3V slot. PCI slots are required to provide 25W total power to each slot, so the dialogic requirements are high, but within spec. -- Paul Fulghum paulkf@microgate.comArticle: 70678
Hello All ! I would like to know, if anybody has already made experiances with communication between XILINX (Virtex) and MII (Medium Independent Interface ) ?? Does already exist a free VHDL CORE for this interface ? Where can I get it ? Thanks for all informations ! Brian.Article: 70679
Rajeev, should have answered your question. There are two things to be aware of: 1. The default file search order is the current project directory followed by the library paths specified in the Assignment ->Settings-.User Libraries dialog. 2. The important thing to note is that File Order is important for VHDL elaboration or you will see missing entity messages. You can use the Up, Down buttons in the Project->Add Files Dialog to organize the order in which theVHDL files will be elaborated. The ones on the top are elaborated first and the entities discovered can be referenced by files lower on the list. Hope this helps. - Subroto Datta Altera Corp. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:40D8A954.C61855BA@yahoo.com... > I would like to compile my new design to get a baseline number for > resource usage. I have done this before, but I don't remember how to > set up VHDL component libraries using Quartus. I have a common and a > hardware library and a couple of VHDL source files for each. I can't > find a way to associate the source files with the particular libraries. > In Modelsim you just create the library and make the connection in the > GUI. I can create a library in Quartus, but I can't find a way to > connect this to a source file. I am also not sure that this is the same > as a VHDL library. > > The help files seem to skirt around this issue... any advice? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70680
bayou1221@yahoo.com (Andy) wrote in message news:<cbff8633.0406222001.6d2a0e93@posting.google.com>... > Hi all, > I am trying to implement a small ALU module using the Xilinx ISE web > pack and the simulator is Silos. > When I try to synthesize this design, it gives me an error for the > division. I have implemented division directly, i.e. out <= A / B; > All I know is this is a pretty inefficient way of doing it but was not > expecting errors. / is not a synthesizable operator. Cheers, JonBArticle: 70681
Paul Fulghum wrote: > marco p. wrote: > >> Hi, >> I have a problem with a Dialogic board "DM/IP301-1e1-PCI". >> I installed that board in a Piv 1.6Ghz Mainboard D845WN and I can't do >> it starts. The board's power requirements are 22.5W @ 5V, and using PC >> Wizard I see that the PCI slot used by the Dialogic board has this >> description: "In Use (32-bit) 3.3v". >> Is this a problem? >> Does the board fail to start by this reason? >> Can I make the board and the Mainboard compatible? >> thanks! >> Bye > > > PCI slots are either 3.3V or 5V > > PCI boards are 3.3V, 5V, or > universal (fits in both 3.3V or 5V slots) > > PCI slots and cards are mechanically > keyed to prevent plugging cards into > incompatible slots. > > Even 3.3V slots provide 5V power supply. > > So the dialogic board must be a 3.3V or > universal card or it would not fit in > the 3.3V slot. > > PCI slots are required to provide 25W total power > to each slot, so the dialogic requirements are > high, but within spec. > > -- > Paul Fulghum > paulkf@microgate.com I am almost sure you don't have any 3.3V on your PCI Slot. We have designed over 10 different PCI cards for different custom projects based on our komodo board. On the first prototyping board we were using both 5V and 3.3V from the PCI Slot. Now all our new PCI boards use only 5V. Why? just because a large part of motherboards *DO NOT PROVIDE* 3.3V on the PCI slots. See our Komodo picture to find where is B side (slot side) and A side (http://www.amontec.com/komodo.shtml) You can verify your 3.3V on PCI finger pin no B-25 B- for B side B-31 B-36 B-41 B-43 B-54 A-21 A- for A side A_27 A-33 A-39 A-45 A-53 Just take time to measure the voltage on one of these point !!! Laurent Gauch www.amontec.com ------------ And now a word from our sponsor ------------------ For a quality usenet news server, try DNEWS, easy to install, fast, efficient and reliable. For home servers or carrier class installations with millions of users it will allow you to grow! ---- See http://netwinsite.com/sponsor/sponsor_dnews.htm ----Article: 70682
hello, While running the XST in batch mode; (by typing xst at command prompt) .. and followed by "help -arch virtex -command run" .... this gives a list of all the synthesis options available in the batch mode. one of the options is -mapstyle... which has two options to select from (LUT / Library) ... this option is not described in software documentation, as well not found in GUI. Does anybody have any information regarding the purpose of this option? thanks in advance. regards Varun.Article: 70683
Phil Moore schrieb:
> I am reading from the 7 segment display. I could read from LED's, it
> doesn't really matter.
What are you talking about ?
Here is a simple code fragment to show "1234" on the 7segs
Have a look into the docu of DIO4 and D2SB
j
signal cnt100: integer range 0 to 100;
signal cnt4 : std_logic_vector(1 downto 0);
--
--
--
process (mclk, reset)
begin
if reset='1' then
cnt100<=0;
cnt4<="00";
elsif mclk = '1' and mclk'Event then
if cnt100=99 then
cnt100<=0;
cnt4<=cnt4 + 1;
else
cnt100<=cnt100+1;
end if;
end if;
end process;
--
-- control the anodes of the 7segs
an(0)<='0' when cnt4="00" else '1';
an(1)<='0' when cnt4="01" else '1';
an(2)<='0' when cnt4="10" else '1';
an(3)<='0' when cnt4="11" else '1';
process(cnt4, sw(3 downto 0))
begin
case cnt4 is
when "00" =>
if sw(0)='1' then
cx<="1111001";
else
cx<="1111111";
end if;
when "01" =>
if sw(1)='1' then
cx<="0100100";
else
cx<="1111111";
end if;
when "10" =>
if sw(2)='1' then
cx<="0110000";
else
cx<="1111111";
end if;
when "11" =>
if sw(3)='1' then
cx<="0011001";
else
cx<="1111111";
end if;
when others=>
cx<="1111111";
end case;
end process;
Article: 70684Amontec Team wrote: > I am almost sure you don't have any 3.3V on your PCI Slot. The motherboard claims PCI 2.2 compliance which requires 3.3V be supplied to all slots (on PCI 2.1, 3.3V supply was optional). Marco: Take a look at this errata for the mainboard: http://support.intel.com/support/motherboards/desktop/sb/CS-009038.htm -- Paul Fulghum paulkf@microgate.comArticle: 70685
Jim,
-snip-
>
> Could you give us 1H 2004 volumes, and present lead times, for S3
> devices ?
> As a designer, a valid question is: Has Xilinx 'caught up' enough, so
> that a design could use these devices, and not have a supply problem ?
>
> -jg
No, I can not do that Jim. To get supply information, you must contact
your distributor. To get how many we have, I have to wait for a press
release (confidential and restricted information can not be released on
this newsgroup)just like you do.
I am told that distributors do have part/package combinations in stock
on the shelf. I am also told that some devices are still in short
supply. We are fab'ing as many wafers as we possibly can to catch up
(projecting ahead), but demand is ramping faster.
To that end, and by your definition, perhaps we have not caught up on
some devices (glass is half empty), but we are doing the best we can and
making a lot of progress (glass is half full).
No one is going to post on this newsgroup that their part was on the
shelf when they ordered it ('dog bites man' is not news). But if the
part is not on the shelf, then we hear all about it in this forum ('man
bites dog' is news).
I advise anyone who is designing (regardless of the part or family) to
work closely with your distributor, (as anyone would who buys in the
quantities that we are seeing for S3).
Austin
PS: I did not intend to put "words in your mouth". Poetic license
#23210098 issued 5/14/53
Article: 70686Subroto Datta wrote: > > Rajeev, should have answered your question. There are two things to be aware > of: > > 1. The default file search order is the current project directory followed > by the library paths specified in the Assignment ->Settings-.User Libraries > dialog. > > 2. The important thing to note is that File Order is important for VHDL > elaboration or you will see missing entity messages. You can use the Up, > Down buttons in the Project->Add Files Dialog to organize the order in which > theVHDL files will be elaborated. The ones on the top are elaborated first > and the entities discovered can be referenced by files lower on the list. Thanks, but no, this does not help. I have already added the libraries using the settings dialog. But I don't know how to connect the VHDL package files to the library. I think I am missing something basic to how this works. In modelsim, you just create a library, say "common", and then click on each file that goes into that library and change its association to link it to the library. I gather that Quartus work rather differently? Do I need to separately compile the library sources or something? I have two user libraries; common and hardware; with two source files each and more may be added later. BTW, I really can't find any info about this in the help files. There is info on how to write the VHDL, but nothing that I can find on how to hook all this together. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70687
hello, While running the XST in batch mode; (by typing xst at command prompt) .. and followed by "help -arch virtex -command run" .... this gives a list of all the synthesis options available in the batch mode. one of the options is -mapstyle... which has two options to select from (LUT / Library) ... this option is not described in software documentation, as well not found in GUI. Does anybody have any information regarding the purpose of this option? thanks in advance. regards Varun.Article: 70688
Hello, everybody! I have the following question regarding Xilinx Spartan-3 family. Can these devices, which require 2.5V to be connected to the VCCAUX (JTAG and DLL power) be configured using former Parallel III cable, JTAG mode? Does it require some small series resistors on the JTAG signals as motioned it the SPARTAN-3 data sheet? Thanks a lot in advance. Alex Shrabstein.Article: 70689
Martin Thompson wrote: >>Interesting. I did not know about this. I generally use XFlow on >>Solaris and now Linux so I have not encountered this. For UNIX >>machines, it creates an xflow.scr file which is a CSH script of all of >>the commands however I personally never use it. > > > Ahh, my understanding of the way it worked was that the script was > created and then executed by the XFLOW executable, rather than that > executable doing all the execs itself.. Not at all. The bat file is supposed to be more for reference than for use in my opinion. There is a lot of "smarts" in the tool that would not happen if it was used in that way. It is a shame they named that file xflow.bat and I am going to suggest they rename it to something like xflowbat.bat to get around the problem you cite. -- Brian <snip>Article: 70690
If you want division and don't have a Virtex4 (?!) you'll have to do the division yourself in hardware or in software. Small microcontrollers have rarely had division in their ALUs with the software division supported by routines with a series of add/subtract, rotate through carry, and shift operations. "Andy" <bayou1221@yahoo.com> wrote in message news:cbff8633.0406222001.6d2a0e93@posting.google.com... > Hi all, > I am trying to implement a small ALU module using the Xilinx ISE web > pack and the simulator is Silos. > When I try to synthesize this design, it gives me an error for the > division. I have implemented division directly, i.e. out <= A / B; > All I know is this is a pretty inefficient way of doing it but was not > expecting errors. > > Any tips or pointers will be very helpful. > > Thanks, > AndyArticle: 70691
Yes if the motherboard is in the PCI 2.2 spec. But anyway, I would verify the 3.3V ! following CS-009038, your BIOS revision should be P05 or higher ! Larry www.amontec.com Paul Fulghum wrote: > Amontec Team wrote: > >> I am almost sure you don't have any 3.3V on your PCI Slot. > > > The motherboard claims PCI 2.2 compliance which requires 3.3V > be supplied to all slots (on PCI 2.1, 3.3V supply was optional). > > Marco: > > Take a look at this errata for the mainboard: > > http://support.intel.com/support/motherboards/desktop/sb/CS-009038.htm > > -- > Paul Fulghum > paulkf@microgate.com > ------------ And now a word from our sponsor ------------------ Want to have instant messaging, and chat rooms, and discussion groups for your local users or business, you need dbabble! -- See http://netwinsite.com/sponsor/sponsor_dbabble.htm ----Article: 70692
"Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message news:40D8C416.8060607@NOSPAM.com... > This seems to be a bug in projnav when using the XMP as a source file. > > ISE creates the EDK project in VHDL mode. This has to be changed. > The only way to do that today is to open the xmp file in an editor > and change VHDL to VERILOG. > > Basically the projnav could not resolve the path to the edk data from > the xmp. One way around this is to generate the netlist in XPS and > then take that system.v file and instantiate it as a source > in projnav. You will need to remove the xmp as a source. > > Antti Lukats wrote: > > Hi > > > > does anybody know if it is possible to use EDK system in ISE toplevel if the > > toplevel is in verilog? Thanks Paulo, well unfortunatly if I remove the .XMP from project I can not do "update sources" any more from Project Navigator! so the fix is not a real solution! :( Any ideas when/which service pack will fix this problem?? ISE/EDK integration is getting better, but would be real nice to see it working one day !! (before doom-day hopefully!) AnttiArticle: 70693
"Austin Lesea" <austin@xilinx.com> wrote in message news:cbc6gt$cn31@cliff.xsj.xilinx.com... > > I advise anyone who is designing (regardless of the part or family) to > work closely with your distributor, (as anyone would who buys in the > quantities that we are seeing for S3). > Very good advice Austin. To be fair to Xilinx, our Distie, knowing our volumes and lead time requirements, advised us to steer clear of S3 for a while. From some of the posts I read on here, this appears to have been the correct thing to do for my company. (Although, as you say Austin, the people who got their parts don't post here to complain!) When I try to see things from Xilinx's point of view, of course they're gonna supply their biggest customers first, and keep pushing the product with as much hype as possible to these main guys, fair enough. Also, don't forget that if it weren't for the big guys buying loads of parts, the small guys wouldn't get any of these parts _ever_. It's just that the marketing spiel eventually becomes a little frustrating! Maybe what we need is not only price vs. volume data, but lead-time vs. volume too! Finally, you can be sure people are impressed with the product, Austin. No-one would complain about lead-time if the chips were a pile of poo. Cheers, Syms.Article: 70694
Dear Sir, I have been trying to the contents of readback block ram on spartan II kit. This is how i tried I syntheized and implemented the design using Jtag clk as start up clk and enableing the readback in configuartion option. then connnecting the jtag cable to the board . i tried to program using Jtag Programmer(Foundation Series 3.1). I clicked on the program in the Menu , it gave 2 warning one that the device ID is not tht of a Xilinx device . And the other saying some BSDL file error. I proceeded to excetute the step given in xapp188 for readback writing CFG_IN in IR and load FAR , loading RCFG in cmd and other till CFG_OUT was written but i saw no chnage . I did this through debug chain option . I dont think i am doing it right please do help me on this i need to readback the memory how should be do it exactly with regrads sushmitaArticle: 70695
You can't count on having a 5-volt supply on your 3.3V PCI bus. You also can't count on having a 3.3-volt supply on your 5V PCI bus. The PCI spec specifies that both should be there, but my development team was caught with these "gotchas". The real world implementation of the PCI spec does not guarantee the presence of both supplies in commercial PCs. If you are able to physically install the Dialogic card in your Mainboard slot, and the Dialogic card requires 5V, then the card must have universal PCI card slot keys. Electrically, however, it won't work if your mainboard doesn't supply 5 volts to the 3.3-volt PCI slots. They are basically incompatible unless you do some mainboard mods that are not guaranteed to work with the card, and may kill compatibility with other cards. I'd recommend replacing the card. 3.3V PCI slots are becoming the norm, especially with PCI-X gaining wider acceptance. Dwayne Surdu-MillerArticle: 70696
Jonas, I'm assuming you are using EDK 6.2. The mode of XMDSTUB v/s EXECUTABLE can be selected on per application basis. Go to the Sw Applications tab in the left column and for your application, right click --> Compiler Options. In this dialog box,you will fix option to choose between xmdstub and executable mode. Amit Jonas Floden wrote: > Hello all, > > We are currently doing a project where we would like to evaluate the > advantages of the PPC405 hard processor core in the Virtex-II Pro FPGA > compared to the Microblaze soft core. We've got the Microblaze up and > running but we are struggling to get the PPC to execute any code. > > The chip is an Engineering Sample: > > Virtex-II Pro > XC2VP7 > FF672ALB0237 > D127316A > 6C-ES > > The program is a very simple one - just trying to get a diod on the > board to flash. In our EDK project, under S/W settings, we are unable to > select Mode - Executable. XmdStub is pre-selected and grayed out. > Therefore we suspect that the code is compiled to run in a debugging > mode. > After the circuit has been programmed through the JTAG interface (thus > the JTAG is properly connected and working) we try to use the XMD > debugger to connect to the PPC405 JTAG port. (We've tried to connect > both directly to the PPC405 JTAG and to the normal JTAG chain). > XMD then presents us with an error message: > > ERROR: Unable to connect to PowerPC target. Invalid Prcessor Version No > 0x00000000 > Unable to establish connection to the PowerPC target. Make sure the > PPC405 JTAG signals are connected to the JTAGPPC primitive and the cable > connections are correct. > > The question is - is it possible to get EDK to compile the code to > execute straight away without the need of a debugger and JTAG > connection? If not, any suggestion on what might be wrong is highly > appreciated. Could the error message have anything to do with the fact > that we're using an Engineering Sample of the chip? > > Best Regards, > > Jonas Floden > Bjorn Saete >Article: 70697
Antti, Did you try goign to EDK and doign an Tools-> Export To ProjNav. This will create a new ProjNav project for you after runnign synthesis for EDK subsystem. Remember to go to Project Options and select * This is submodule of my design * Implementation Flow: ISE Once the new projnav project is created, you can add your own files there. If there are any chagnes in EDK, you can re-export from EDK to the existing ProjNav project. Amit. Antti Lukats wrote: > "Paulo Dutra" <paulo.dutra@NOSPAM.com> wrote in message > news:40D8C416.8060607@NOSPAM.com... > >>This seems to be a bug in projnav when using the XMP as a source file. >> >>ISE creates the EDK project in VHDL mode. This has to be changed. >>The only way to do that today is to open the xmp file in an editor >>and change VHDL to VERILOG. >> >>Basically the projnav could not resolve the path to the edk data from >>the xmp. One way around this is to generate the netlist in XPS and >>then take that system.v file and instantiate it as a source >>in projnav. You will need to remove the xmp as a source. >> >>Antti Lukats wrote: >> >>>Hi >>> >>>does anybody know if it is possible to use EDK system in ISE toplevel if > > the > >>>toplevel is in verilog? > > > Thanks Paulo, > > well unfortunatly if I remove the .XMP from project I can not do "update > sources" any more from Project Navigator! > so the fix is not a real solution! :( Any ideas when/which service pack will > fix this problem?? > > ISE/EDK integration is getting better, but would be real nice to see it > working one day !! > (before doom-day hopefully!) > > Antti > > >Article: 70698
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0406230554.1198a15a@posting.google.com... > bayou1221@yahoo.com (Andy) wrote in message news:<cbff8633.0406222001.6d2a0e93@posting.google.com>... > > / is not a synthesizable operator. > Oh yes it (sort of) is! From the Synplify reference manual:- Operators /, mod, and rem are supported for compile-time constants or when the right argument is a power of 2. Cheers, Symon 'Pedant' Brewer.Article: 70699
Neil Glenn Jacobson wrote:
> Stephen Williams wrote:
>
>> Neil Glenn Jacobson wrote:
>>
> Ooops. I forgot. Xilinx does not release a LInux version of WebPACK.
> Nix that previous message.
But could the windows version using wine be used here?
Can the linuxdrivers be used of are they only for the native Linux version of ISE?
I recently bought a Spartan-3 board from NuHorizons in the hope to use
it using WebPACK under wine on Linux.
Regards,
Sietse Achterop
Computing Science department
University of Groningen
The Netherlands
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