Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
John_H wrote: > I'd suggest looking at the results with the series resistor at the S3 driver > before the transmission line for a baseline and then moved to the end of the > transmission line before the split for a comparison. You may see very > little difference, suggesting the location of the resistor isn't critical; > but then you might see it is. In motherboards, the series resistors are > often at the edge of the DDR connector, not as close to the driver as > possible. Looking at the results that doesn't change much the appearence of the signals or the delay. > Having a series resistor at your input shouldn't affect your timing much > (such as for bidir lines); at that point the only delay seen is the RC for > the series resistor and the input parasitics. For example, 35 ohm and 8 pF > gives a 280 ps time constant which is small for the overall timing budget in > the slower DDR implementation. Yes, I'm planning on slow DDR (100Mhz), so that doesn't seem to have much impact. > The biggest suggestion I have is to keep the DDR-side stubs to a minimum, > reducing the problems introduced by the impedance mismatch. Ok, given that the DDR chips are very close to the FPGA, the resitors might in fact be at the same distance from FPGA than the DDR chips. SylvainArticle: 72251
THX Open the schematic with the older software to know what do and know how work; and then redo the project into the most generic VHDL as possible; without trying to copy a schematic into VHDL. ( One more reason to use VHDL standard ) Walter "buke2" <cubah@tlen.pl> a écrit dans le message de news:cff932$pv0$1@atlantis.news.tpi.pl... > Anybody knows how convert schemtic from Xilinx 2.1 to ISE6.2 Webpack? > It is very strange that ISE6.2 cannot convert earlier version of schematic > (the same company). > > THX > >Article: 72252
Steven K. Knapp wrote: > Just in case you haven't already seen it, I would recommend taking a look at > the Spartan-3 133 MHz DDR SDRAM reference design that supports up to DDR266 > (PC2100) . Much of the engineering effort is already done. > > The application note and reference design is on the Xilinx Memory Corner. > http://www.xilinx.com/memory > > http://www.xilinx.com/products/design_resources/mem_corner/resource/xaw_dram_ddr.htm > > You'll want "XAPP768c: 133 MHz DDR Interface for Spartan-3 HDL Code". The > application note and reference design are available to registered Xilinx web > site viewers (which is a PITA, but unfortunately, that's the policy). I had a look at some application notes from Xilinx of course. But I didn't saw that one. I'm waiting for approbation from the "memory team". The ones I looked at had no mention of terminations, only considerations about trace lenght/delay. (Or I missed them). I just saw on a Virtex2 userguide and in SelectI/O app note that for SSTL_2 and DDR, they use a pull resistor of 50 ohm to Vtt=1.25v at both ends with a series of 25ohm. But that seem complicated, probably not needed for slow DDR and that will draw significantly more current than a simple series termination. In a Micron app note, then they only use a 60 ohm series resitor at the middle of point to point connection. > Another recommendation is to take a look at the following overview > application note. This one is available without registering. > > XAPP802: Memory Interface Application Notes Overview > http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf Not much informations about signal integrity there. > Also, depending on the specific memory device you are using, you probably > want to use one of the SSTL I/O standards. Likewise, some of the Micron > devices, and probably others, have SSTL_2, Class II output buffers and offer > a reduced drive strength option for low load or point-to-point designs. Yes, they indeed uses SSTL_2 (Micron's chips) Thanks for the suggestions, Sylvain MunautArticle: 72253
Hi all, I'm cuurently working on a xilinx spartan 2e design, for debug I'm using the chipscope pro LA. the problem is as follows: I'm using the chipscope pro for looking at the logic lines (bus) that define the "state" of the state machine in order to determine the present state of the machine at a given time. but the chipscope is giving me the binary (or oct, hex etc.) value of the bus. when I'm declaring the state machine in VHDL I'm giving each state a name (the synt' does the enumeration automatically) so I do not know what is the corresponding bus value for each state. I'm pretty sure that the Xilinx synthisizer generates this kind of data but I dont know where to find it and so is their FAE :) for example: if I declare a simple state machine with the follwoing states: type state_type is (idle , first , second , last) I would like to get a reference data such as: idle = 00 first = 01 second = 10 last = 11 that would be very helpfull when debugging large state machines with chipscope. So if anyone knows where to find it (if possible) I would realy appreciate it. thanks in advance, Moti.Article: 72254
"Thomas Nilsen" <nospam@nospam.nospam> wrote in message news:cffdsu$ios$1@services.kq.no... > Hello. > Im a new masters degree student and i want to have a kit at home. > I need help on selecting the right development kit for me. > What are the difference in capabilities for the Spartan 3, Spartan 2, > Spartan 2E. These three types seems like the boards that have a reasonable > price for me. All three device families are quite capable and boards containing any of the three will help in learning about FPGAs. Spartan-3, however, is architecturally similar to the other modern Xilinx FPGA families like Virtex-II/Pro, etc. Also, the latest free Xilinx WebPack software typically supports the two most recent Spartan FPGA families, Spartan-3 being the most recent of all three. The older families are still supported, but only in "Classic" software that may not include the latest enhancements. Just in case you haven't already seen it, the Spartan-3 Starter Kit board also includes 1Mbyte of RAM on the board, plus RS-232, VGA, and PS/2 ports. http://www.xilinx.com/s3boards --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72255
Hi everyone I am having a strange problem with programming Xilinx XC2s200 FG 256. Following is a brief description: 1) I am able to download .bit file to the FPGA using slave serial mode. The code is primarily a DMA state machine which is responsible for transfering date from peripherals to DSP and vice versa. We have a diagnostic DMA test in place which tells the user about incorrect accesses. The DMA test in this case works impeccably- no errors even after running overnight. 2) We also need the same system in a standalone mode and hence we need a PROM device to store the configuration file for the FPGA. So I convert the .bit file to .mcs file using Xilinx 6.2i. The PROM that we use is XC17s200A one time programmable PROM. The FPGA gets programmed in master serial mode in this case. The same DMA test runs fine for the first 3 or 4 mins and then starts reporting errors. I am not sure why. Is there any difference between the 2 methods that could cause this error. We also thought of the possibility of bitstream getting corrupted when getting converted to .mcs file.But we have not faced this problem before. The line between the PROM and FPGA is a serial bit stream.The circuitry of from the PROM matches exactly as what is specified in the datasheets- including a 3.3 K pull resistor for the ~INIT line . Has anybody seen a problem like this before? Please let me know thanks Krishna Kumar DSP system Engineer Signalogic Inc Dallas TXArticle: 72256
Hi I have problems instantiating the ramb4_s1_s16 in vhdl. ramb4_s2_s16 works fine. The error message is ... ========================================================================= * Low Level Synthesis * ========================================================================= ERROR:Xst:79 - Model 'RAMB4_S1_S16' has different characteristics in destination library ERROR:Xst:1831 - Missing ports are:DOA0 DIA0 ERROR:Xst:1832 - Unknown ports are:DOA DIA ERROR: XST failed Process "Synthesize" did not complete. Following I have listed my test code for both blockrams. Can anybody show me what I missed? Frank ///////////////////////////////////////////////////////////////////////////// library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity testram2 is port ( DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end testram2; architecture Behavioral of testram2 is component RAMB4_S1_S16 port ( DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end component; begin ram0 : RAMB4_S1_S16 port map( CLKA => CLKA, WEA => WEA, ADDRA => ADDRA, DIA => DIA, DOA => DOA, ENA => ENA, RSTA => RSTA, CLKB => CLKB, WEB => WEB, ADDRB => ADDRB, DIB => DIB, DOB => DOB, ENB => ENB, RSTB => RSTB ); end Behavioral; /////////////////////////////////////////////////////////////// library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity testram is port ( DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end testram; architecture Behavioral of testram is component RAMB4_S2_S16 port ( DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end component; begin ram0 : RAMB4_S2_S16 port map( CLKA => CLKA, WEA => WEA, ADDRA => ADDRA, DIA => DIA, DOA => DOA, ENA => ENA, RSTA => RSTA, CLKB => CLKB, WEB => WEB, ADDRB => ADDRB, DIB => DIB, DOB => DOB, ENB => ENB, RSTB => RSTB ); end Behavioral;Article: 72257
If I have a PPC BRAM program running on a V-II Pro, can it reconfig the CLB slices? I'd like to be able to do this w/o using an external MCU. I know about PAVE SIF, but would like to avoid running VxWorks RTOS on the PPC. I.e. if the PPC gets a new bitstream over RocketIO/Ethernet/serial, can it selectively reprogram part of the FPGA, using SelectMAP/JTAG/serial or whatever? Thanks for any advice ! Jim jimwang at cal dot berkeley dot eduArticle: 72258
Hey Xilinx, There're are a *lot* of us who don't give a flying f which operating system the tools run on. We'd rather you concentrated on improving the quality, speed, accuracy and ease of use of the tools, rather than provide freebies to students. ;-) Cheers, Syms. p.s. Anyone tried FPGA tools on XP SP2 yet? "Adam Megacz" <megacz@cs.berkeley.edu> wrote in message news:x1pt5wu628.fsf_-_@nowhere.com... > > John Williams <jwilliams@itee.uq.edu.au> writes: > > I don't know about the Altera tools, but my understanding is that > > Xilinx webpack is not available for linux because they would have to > > pay per-seat licensing to the developer of the cross-platform GUI that > > they use. > > Hey Xilinx, if you're listening, there are a *lot* of us who would > rejoice if you released the command line tools for Linux for free. > ESPECIALLY bitgen. We can do without the gui. > > - aArticle: 72259
Hi Jim, Search for Internal Configuration Access Port (ICAP) Cheers, Syms. "Jim Wang" <jim@may.sd.cox.net> wrote in message news:m3hdr8xqxm.fsf@may.sd.cox.net... > If I have a PPC BRAM program running on a V-II Pro, can it reconfig the CLB > slices? I'd like to be able to do this w/o using an external MCU. I know > about PAVE SIF, but would like to avoid running VxWorks RTOS on the PPC. > > I.e. if the PPC gets a new bitstream over RocketIO/Ethernet/serial, can it > selectively reprogram part of the FPGA, using SelectMAP/JTAG/serial or > whatever? > > Thanks for any advice ! > > Jim > > jimwang at > cal dot berkeley dot edu > >Article: 72260
Hi, I'm trying to build a system with Xilinx EDK 3.2 which will have 2 Microblaze processors running separate code on a Virtex-II (xc2v-1000). In XPS, each microblaze component is attached to it's own data and instruction LMB's which have BRAM and BRAM controller blocks attached in turn. When I attempt to generate the bitstream, the process fails during the map stage. I get the following error message: ERROR:Pack:18 - The design is too large for the given device and package. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. . . . Number of bonded IOBs: 132 out of 172 76% Number of Tbufs: 1 out of 2,560 1% Number of Block RAMs: 64 out of 40 160% (OVERMAPPED) Number of MULT18X18s: 6 out of 40 15% Number of GCLKs: 1 out of 16 6% So it looks to me like the number of block RAM's is where the problem is. In the properties for each block ram, I've set the following properties: C_MEMSIZE = 8192 C_PORT_AWIDTH = 13 There is a total of 64k of block RAM available, so I figured that allocating 8k to each processor should be fine. If anyone has tried something similar I'd appreciate some ideas. Thanks in advance, Alastair.Article: 72261
I was trying to use the SDRAM controller without using the NIOS. I am now using the vhdl file generated from SOPC builder. Things are great during simulation i.e. However, when I try to synthesize it. I receive the following warning message: Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin. +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node zs_addr[10] -- logic cell cannot be packed as I/O register +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node sdram_0:sdram_con_inst|m_addr[10] -- logic cell cannot be packed as I/O register +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and I/O node sdram_0:sdram_con_inst|i~28445 -- logic cell cannot be packed as I/O register The m_addr[10] ties to the address pin of the RAM. Bits 9 and 8 are the same as well. Can't seem to find out the reason. I understand that a register is inserted at the pins to optimize timing. If this this node is not packed, does it mean to say that it is bypassed to the pin. In a sentence, how does this impact functionality? Timing analyzer tests indicate that +ve slack so in the end, timing seems up to scratch. Thanks for your help! ;-> TedArticle: 72262
I have a question about Virtex-II configuration architecture. Any help/pointers would be greatly appreciated. Thanks, Sudarshan problem: according to XAPP 151 (vertex config architecture user's guide), each CLB column in Virtex has 48 frames So, XC2V2000 (56 rows 48 columns), should have at least 48 * 48 = 2244 frames however, Virtex-II platform user's guide (v 1.8, page 309) says there are only 1456 frames. So, it seems Virtex-II configuration architecture is different from Virtex configuration architecture. Unfortunately I have so far not been able to locate any document specific to Virtex-II configuration architectureArticle: 72263
Hello Does anybody have the internal circuit diagram of the Xilinx POD 3 Model DLC5 (Power 5 V 10 mA typical)? Please let me know. thanks Krishna KumarArticle: 72264
Alastair, Check the memory mapping of all the Block RAM attached to the processors. The mapping could be read from the following parameters of the LMB Block RAM controllers: PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff The above example is 8k of memory and will use 4 Block RAMs. Shalin- alastair wrote: > Hi, > > I'm trying to build a system with Xilinx EDK 3.2 which will have 2 > Microblaze processors running separate code on a Virtex-II > (xc2v-1000). > > In XPS, each microblaze component is attached to it's own data and > instruction LMB's which have BRAM and BRAM controller blocks attached > in turn. When I attempt to generate the bitstream, the process fails > during the map stage. I get the following error message: > > ERROR:Pack:18 - The design is too large for the given device and > package. > Please check the Design Summary section to see which resource > requirement for > your design exceeds the resources available in the device. > . > . > . > Number of bonded IOBs: 132 out of 172 76% > Number of Tbufs: 1 out of 2,560 1% > Number of Block RAMs: 64 out of 40 160% > (OVERMAPPED) > Number of MULT18X18s: 6 out of 40 15% > Number of GCLKs: 1 out of 16 6% > > So it looks to me like the number of block RAM's is where the problem > is. In the properties for each block ram, I've set the following > properties: > C_MEMSIZE = 8192 > C_PORT_AWIDTH = 13 > > There is a total of 64k of block RAM available, so I figured that > allocating 8k to each processor should be fine. > > If anyone has tried something similar I'd appreciate some ideas. > > Thanks in advance, > > Alastair.Article: 72265
I agree 100% -- while the GUI may *look* user-friendly, it hides what is really happening while it "helps" you. With command-line, you are in control. Just give us the Linux command lines and a few sample Makefiles, forget the GUI. Jim jimwang at cal dot berkeley dot edu -------------- Adam Megacz <megacz@cs.berkeley.edu> writes: > John Williams <jwilliams@itee.uq.edu.au> writes: > > I don't know about the Altera tools, but my understanding is that > > Xilinx webpack is not available for linux because they would have to > > pay per-seat licensing to the developer of the cross-platform GUI that > > they use. > > Hey Xilinx, if you're listening, there are a *lot* of us who would > rejoice if you released the command line tools for Linux for free. > ESPECIALLY bitgen. We can do without the gui. > > - aArticle: 72266
I was looking at the Spartan 3 kit and it seems that this suits my needs in more than one way with some onboard io stuff and a nice price. Thanks for you reply. - Thomas "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:cfg5cm$e6n1@cliff.xsj.xilinx.com... > > > "Thomas Nilsen" <nospam@nospam.nospam> wrote in message > news:cffdsu$ios$1@services.kq.no... > > Hello. > > Im a new masters degree student and i want to have a kit at home. > > I need help on selecting the right development kit for me. > > What are the difference in capabilities for the Spartan 3, Spartan 2, > > Spartan 2E. These three types seems like the boards that have a reasonable > > price for me. > > > All three device families are quite capable and boards containing any of the > three will help in learning about FPGAs. > > Spartan-3, however, is architecturally similar to the other modern Xilinx > FPGA families like Virtex-II/Pro, etc. Also, the latest free Xilinx WebPack > software typically supports the two most recent Spartan FPGA families, > Spartan-3 being the most recent of all three. The older families are still > supported, but only in "Classic" software that may not include the latest > enhancements. > > Just in case you haven't already seen it, the Spartan-3 Starter Kit board > also includes 1Mbyte of RAM on the board, plus RS-232, VGA, and PS/2 ports. > http://www.xilinx.com/s3boards > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > >Article: 72267
>Just give us the Linux command lines and a few sample Makefiles, forget the >GUI. That's not enough. You also need documentation on the format of the files that you will need to edit by hand. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72268
Now I tried it with ISE BaseX and it worked. With ISE Webpack it doesn't. In both cases I used the spartan 2 xc2s50. It should work with webpack to! What going wrong? FrankArticle: 72269
Jim Wang wrote: > If I have a PPC BRAM program running on a V-II Pro, can it reconfig the CLB > slices? I'd like to be able to do this w/o using an external MCU. I know > about PAVE SIF, but would like to avoid running VxWorks RTOS on the PPC. > > I.e. if the PPC gets a new bitstream over RocketIO/Ethernet/serial, can it > selectively reprogram part of the FPGA, using SelectMAP/JTAG/serial or > whatever? > > Thanks for any advice ! As Symon said, look for ICAP, the "Internal Configuration Access Port". xapp660-xapp662 and xapp290 should be interesting for you as well. EDK 6.X comes with an IP-Core connecting ICAP to the OPB, so theoretically you can reconfigure the FPGA with simple memory writes. But in real life, it's so complicated and there's so many restrictions and bugs in the tools that in most cases it's useless and not worth the trouble. It's a bit easier if you use a MicroBlaze instead of the PowerPC, since you can put the MicroBlaze pretty much everywhere you want, which makes the whole process a lot easier. cu, SeanArticle: 72270
Hal Murray wrote: >>Just give us the Linux command lines and a few sample Makefiles, forget the >>GUI. > > > That's not enough. You also need documentation on the > format of the files that you will need to edit by hand. > The command line tools are already well documented, in the "Developement System Reference Guide". http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.htm And the Windows command line tools run quite well under Wine. -- My real email is akamail.com@dclark (or something like that).Article: 72271
gilles wrote: > ... > Regarding Duane solution, how can i use the same clock for both signals > when use opb ddr core : sould i modify the core design itself ?? > You probably have to modify the design anyway, since the EDK core is for a single DDR chip, and the DIMM has multiple chips on it (unless you are not interested in using all the chips). You make a copy of the core in your project pcores directory, name it something else, and start modifying away. That is what I did. -- My real email is akamail.com@dclark (or something like that).Article: 72272
Frank Benoit wrote: > Now I tried it with ISE BaseX and it worked. > With ISE Webpack it doesn't. > In both cases I used the spartan 2 xc2s50. It should work with webpack to! > What going wrong? > > Frank > I don't know if this will fix your problem or not but I highly suggest you uncomment the UNISIM library declaration and get rid of the component declaration. When I do that, it gets rid of all of the warnings in XST when I try this code. Not only does it get rid of unnecessary warnings but these changes are necessary if you plan to simulate this code and it should clean up the hierarchy tree in the Project Navigator view as well. Try this: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. library UNISIM; use UNISIM.VComponents.all; entity testram2 is port ( DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_ULOGIC; ENB : in STD_ULOGIC; RSTA : in STD_ULOGIC; RSTB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end testram2; architecture Behavioral of testram2 is begin ram0 : RAMB4_S1_S16 port map( CLKA => CLKA, WEA => WEA, ADDRA => ADDRA, DIA => DIA, DOA => DOA, ENA => ENA, RSTA => RSTA, CLKB => CLKB, WEB => WEB, ADDRB => ADDRB, DIB => DIB, DOB => DOB, ENB => ENB, RSTB => RSTB ); end Behavioral;Article: 72273
Thanks for your answer I think I tried it like that too. But I will try it again tomorrow in office. I spent 2 days with that problem. And then on my other office where I have a BaseX it worked. What a shock. So, I think the problem is in the webpack, not in the code? But I need it working on the place with the ISE webpack. FrankArticle: 72274
Moti, As you say, the synthesiser automatically assigns binary values to the states. The states could be assigned linearly (e.g. "00", "01", "10", "11"), or as one-hot (e.g. "0001", "0010", "0100", "1000"), or using any other scheme that the synth wants. The assignments could change as your code is changed (e.g. if timing becomes harder to meet due to some change). Therefore, for your debug purposes, it would be best to assign a different value to a STATE_DEBUG signal upon entering every state, and bring this STATE_DEBUG signal out for your debugging. This still allows the synth the flexibilty of chosing the "best" binary values for the states, but ensures that the debug signal values do not change between builds. Remove the m after my name for emails, otherwise they will be bounced. Good Luck, Ken Morrow, Morrow Electronics Limited, UK. FPGA design for comms www.morro.co.uk "Moti Cohen" <moti@terasync.net> wrote in message news:c04bfe33.0408120546.6e78d19b@posting.google.com... > Hi all, > > I'm cuurently working on a xilinx spartan 2e design, for debug I'm > using the chipscope pro LA. > the problem is as follows: I'm using the chipscope pro for looking at > the logic lines (bus) that define the "state" of the state machine in > order to determine the present state of the machine at a given time. > but the chipscope is giving me the binary (or oct, hex etc.) value of > the bus. > when I'm declaring the state machine in VHDL I'm giving each state a > name (the synt' does the enumeration automatically) so I do not know > what is the corresponding bus value for each state. > I'm pretty sure that the Xilinx synthisizer generates this kind of > data but I dont know where to find it and so is their FAE :) > > for example: > if I declare a simple state machine with the follwoing states: > > type state_type is (idle , first , second , last) > > I would like to get a reference data such as: > > idle = 00 > first = 01 > second = 10 > last = 11 > > that would be very helpfull when debugging large state machines with > chipscope. > So if anyone knows where to find it (if possible) I would realy > appreciate it. > > thanks in advance, Moti.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z