Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 73200

Article: 73200
Subject: adder VS increment
From: "Jimmy zhang" <crackeur@comcast.net>
Date: Wed, 15 Sep 2004 21:17:18 GMT
Links: << >>  << T >>  << A >>
Hi, All,
  A 32 bit adder takes two 32 bit inputs. The propogation delay
can be significant. if one of those two 32 bit inputs is a constant
1, can the add logic be optimized so that the delay for increment
(+1) is reduced?
 The ohter question is that for 32 bit add, can I achieve 100Mhz
on the latest FPGAs?

Thanks,
Jimmy




Article: 73201
Subject: Re: Xilinx Core Gen Question
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 15 Sep 2004 14:59:24 -0700
Links: << >>  << T >>  << A >>

"Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message
news:414838f8$1@news.vsnet.ch...
> Hi all,
>
> Can I insert my own IP core in the Xilinx Core Gen?
> Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
> If not, why Xilinx does not allow that feature.
>
> Larry,
> www.amontec.com

yes you can.

well there are some problems and I guess not all the core gen funtions are
accesible to regular non privileged users, but you can create your own
coregen cores

Antti



Article: 73202
Subject: Re: problem with ALtera CPLD
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Wed, 15 Sep 2004 23:45:17 +0100
Links: << >>  << T >>  << A >>
"greg" <xgrzes@poczta.onet.pl> wrote in message 
news:ciaa1c$s55$1@news.onet.pl...
> Hello
> I'm nev on this group and have following problem.
> I need to program EPM7064SLC44 using JTAG cable (ByteBlasterII) and 
> Quartus
> 4.1 and it doesn't work
> Auto detection does not work either. When i connect EPM7128SLC84 all 
> works,
> so cable and software is OK.
> I tried different chips (EPM7064SLC44 ones with different speed grades) 
> and
> all don't work.
> i connected scope and TDI,TMS and TCK signals seems to be ok, but there is
> no TDO signal...
> Does anybody had similar problem?
> maybe there is something wrong with quartus?
> I used altera 7000 series chips and never had any problems (but never used
> 7064 one)

I've not had any problems with the EPM7064BTC44-7 using Quartus and my own 
version of the ByteBlaster.

Leon
-- 
Leon Heller, G1HSM
http://www.geocities.com/leon_heller 



Article: 73203
Subject: Looking for a Design for a Small FPGA Board
From: daragoth@kuririnmail.com (Daragoth)
Date: 15 Sep 2004 16:07:20 -0700
Links: << >>  << T >>  << A >>
Hi, I'm a hobbyist, and about a month and a half ago I made a post to
this newsgroup looking for a compact FPGA board that I could purchase
online in small quantities for a project I was doing.  It seemed that
no one knew of a board with the specs I needed (and the closest ones I
was able to find were the ones at www.fpgas4fun.com, but they were
slighty too large for what I needed), so I decided to try and design
one myself with PCB design software (EAGLE 4.13).  But I have very
little experience in PCB design and am pretty overwhelmed with created
a design from scratch.  So I was wondering if there was a place I
could download the design or (in case anyone missed my original post)
purchase a board with the following specs:

-FPGA device with at least 15,000 usable gates (more would be
preferable).  I only need a small number of user IOs, so that
shouldn't be an issue at all.
-clock to run the FPGA with only around 4 MHz frequency range...
higher isn't a problem however.
-in-circuit reprogrammable non-volatile memory device for storing the
FPGA's configuration data, if the FPGA doesn't have one built-in.
-The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less
volume (this is important).

I'm planning on just soldering wires directly to the board, so no
specific connectors are necessary.  And I don't mind if the specs
aren't exactly what I need, just so long as they are relatively easy
to alter to my specifications.  Thanks a lot for any help.


-Darien

Article: 73204
Subject: Re: Looking for a Design for a Small FPGA Board
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 15 Sep 2004 23:20:11 GMT
Links: << >>  << T >>  << A >>
To make a complete system, what do you have/want for the system clock?  Is
there a need for an on-board oscillator?

What about power?  Are you supplying a predetermined external fixed voltage?
An external voltage to satisfy the FPGA?  Several external voltages to match
the FPGA's every whim?

Are you expecting your I/O to be 5V tolerant/compatible?

These questions and perhaps a few more might be needed to get the fully
working board.

Another thought might be to get a TQFP prototyping board (or adapter) and
wire together your own regulators, bypass, and frequency sources.  There are
100 pin TQFP packages that are pretty small - the support stuff might take
up the most room.


"Daragoth" <daragoth@kuririnmail.com> wrote in message
news:317379a8.0409151507.68edc201@posting.google.com...
> Hi, I'm a hobbyist, and about a month and a half ago I made a post to
> this newsgroup looking for a compact FPGA board that I could purchase
> online in small quantities for a project I was doing.  It seemed that
> no one knew of a board with the specs I needed (and the closest ones I
> was able to find were the ones at www.fpgas4fun.com, but they were
> slighty too large for what I needed), so I decided to try and design
> one myself with PCB design software (EAGLE 4.13).  But I have very
> little experience in PCB design and am pretty overwhelmed with created
> a design from scratch.  So I was wondering if there was a place I
> could download the design or (in case anyone missed my original post)
> purchase a board with the following specs:
>
> -FPGA device with at least 15,000 usable gates (more would be
> preferable).  I only need a small number of user IOs, so that
> shouldn't be an issue at all.
> -clock to run the FPGA with only around 4 MHz frequency range...
> higher isn't a problem however.
> -in-circuit reprogrammable non-volatile memory device for storing the
> FPGA's configuration data, if the FPGA doesn't have one built-in.
> -The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less
> volume (this is important).
>
> I'm planning on just soldering wires directly to the board, so no
> specific connectors are necessary.  And I don't mind if the specs
> aren't exactly what I need, just so long as they are relatively easy
> to alter to my specifications.  Thanks a lot for any help.
>
>
> -Darien



Article: 73205
Subject: Re: altera quartus II handbook is wrong??
From: sdatta@altera.com (Subroto Datta)
Date: 15 Sep 2004 16:26:32 -0700
Links: << >>  << T >>  << A >>
Hello Sebastian,
  You have a pointed out an error in the handbook which will be
corrected. The piece of code that will infer a ROM in Quartus (used
4.1) is shown below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sync_rom IS
PORT (
clock: IN STD-LOGIC;
address: IN STD_LOGIC_VECTOR(7 downto 0);
data_out: OUT STD_LOGIC_VECTOR(5 downto 0)
);
END sync_rom;

 

ARCHITECTURE rtl OF sync_rom IS
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
CASE address IS
WHEN "00000000" => data_out <= "101111";
WHEN "00000001" => data_out <= "110110";
...

WHEN "11111110" => data_out <= "000001";
WHEN "11111111" => data_out <= "101010";
WHEN OTHERS => data_out <= "101111";
END CASE;
END IF;
END PROCESS;

END rtl;

 
Hope this helps,

Subroto Datta
Altera Corp.

Article: 73206
Subject: Re: altera quartus II handbook is wrong??
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 15 Sep 2004 16:48:47 -0700
Links: << >>  << T >>  << A >>
"sebastian" <malaka@email.it> wrote in message
news:6aefd6be.0409150556.64bda2f2@posting.google.com...
> hi,
>
> im supposed to evaluate the same design in both altera and xilinx
> devices, the problem is that altera's software seems a bit "unusual"
> and doesnt understand code that all others synthetisers i've tried
> recognise.
>
> first i was having trouble with RAMs, but i solved that following
> quartus II handbook coding guidelines (though i had to change several
> files...and i dont like when that happens...specially because i'll
> have three versions, one for each fpga family and then another for
> asic!!)
>
> now, im having trouble with ROMs, specially because the handbook has
> an error...it says

try different settings, small ROMs are not "auto recognized" if not
instructed todo so.
from some ROM size an ROM will be used below the trigger point logic will be
used.
there is an option to choose the ROM extraction behavior

antti
http://altera.openchip.org



Article: 73207
Subject: Re: Looking for a Design for a Small FPGA Board
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 15 Sep 2004 20:25:41 -0400
Links: << >>  << T >>  << A >>
Daragoth wrote:
> 
> Hi, I'm a hobbyist, and about a month and a half ago I made a post to
> this newsgroup looking for a compact FPGA board that I could purchase
> online in small quantities for a project I was doing.  It seemed that
> no one knew of a board with the specs I needed (and the closest ones I
> was able to find were the ones at www.fpgas4fun.com, but they were
> slighty too large for what I needed), so I decided to try and design
> one myself with PCB design software (EAGLE 4.13).  But I have very
> little experience in PCB design and am pretty overwhelmed with created
> a design from scratch.  So I was wondering if there was a place I
> could download the design or (in case anyone missed my original post)
> purchase a board with the following specs:
> 
> -FPGA device with at least 15,000 usable gates (more would be
> preferable).  I only need a small number of user IOs, so that
> shouldn't be an issue at all.
> -clock to run the FPGA with only around 4 MHz frequency range...
> higher isn't a problem however.
> -in-circuit reprogrammable non-volatile memory device for storing the
> FPGA's configuration data, if the FPGA doesn't have one built-in.
> -The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less
> volume (this is important).
> 
> I'm planning on just soldering wires directly to the board, so no
> specific connectors are necessary.  And I don't mind if the specs
> aren't exactly what I need, just so long as they are relatively easy
> to alter to my specifications.  Thanks a lot for any help.

I don't want to be too pessimistic, but I expect it will be very
unlikely that you will find a board that is as small as you are asking
for.  Typically a prototyping board does not have significant size
constraints.  Instead, a proto board will be trying to fit a number of
applications which will require it to be a bit larger than just a chip
on a board.  40 x 30 mm is a very small board.  We build IO modules as
daughterboards on a PC/104 board (already a small foot print) and these
are a bit larger than you are asking for.  One of our big problems with
this format is the lack of space for components.  

I think you need to go back to designing your own.  Perhaps you can get
someone to do the layout for you?  I did my own layout for a couple of
boards and did not find it so difficult.  Is your problem one of being
able to route all the signals in a small space?  

Can you tell me why your board needs to be so tiny?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 73208
Subject: Re: Virtex 4 released today
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 16 Sep 2004 13:42:26 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> Jim,
> 
> Afraid not.  Still limited in the DCM mux to the clock trees, I think it 
> still is only 4 outputs from a single DCM.
> 
> But you could use all DCMs from the same clock, and generate a lot of 
> phases.  Don't think you could get to 32 of them, but perhaps more than 
> 24.  Now you couldn't use them all in one place.  Still need CLKFB 
> connections from BUFGs, as well as something to get to all the inputs of 
> all of the DCMs....
> 
> And the jitter is still there on all of them, so you would have 24+ some 
> phases fuzzily distributed (but accurately placed over time) thoughout 
> the period.

  Understood - but that jitter is relatively low - correct ?
(did someone mention 25ps for V4 ?)

  Maybe the pin-sychronisers can also have independently and fine-grain
control ?


> Not sure why anyone would want to do that, but.....

  Hmmm ? - I can think of quite a few application, where a design
could go into the time-domain, rather than simply be clocked.
  FPGA clock ceilings are relatively low (NB: that's relative to their
time-precision ability!) - we are now at ~500MHz ?

  Some examples : Pulse duration/width measurement to << 1ns,
Pulse generation with edge control << 1ns,
  Phase modulation, and demodulation....
( there are bound to be many more.. )

-jg


Article: 73209
Subject: Re: I/O state of max7000s during power-up?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 16 Sep 2004 13:50:17 +1200
Links: << >>  << T >>  << A >>
u722534179@spawnkill.ip-mobilphone.net wrote:

> I'm using EPM7128S now.Some of the outputs connect 
> to a Darlington array which controls some relays.
> So I want to know the exact state of these outputs 
> during the Power-up.But the datasheet of max7000s 
> doesnt mention it. 
> Somebody tell me the voltage of I/Os is uncertain 
> before the POR completed.Then how can I control them 
> before the device running properly? 

PLDs have internal Power On resets,
IIRC Atmel specify ~3.8V POR release on 5V parts.
(Altera should will be similar).

If your supply takes a really long time to climb to
3.8V, then you could have problems, but normally
by the time there is enough system voltage to work the relays,
you have correctly powered up the CPLD.

If it is vital the relays are never invalid, you
could look to use Reset/Watchdog/hardwired logic to
force a known, safe state.

-jg


Article: 73210
Subject: Re: Looking for a Design for a Small FPGA Board
From: Christoph Loew <christoph@zmp.co.jp>
Date: Thu, 16 Sep 2004 10:50:31 +0900
Links: << >>  << T >>  << A >>
Daragoth wrote:

> Hi, I'm a hobbyist, and about a month and a half ago I made a post to
> this newsgroup looking for a compact FPGA board that I could purchase
> online in small quantities for a project I was doing.  It seemed that
> no one knew of a board with the specs I needed (and the closest ones I
> was able to find were the ones at www.fpgas4fun.com, but they were
> slighty too large for what I needed), so I decided to try and design
> one myself with PCB design software (EAGLE 4.13).  But I have very
> little experience in PCB design and am pretty overwhelmed with created
> a design from scratch.  So I was wondering if there was a place I
> could download the design or (in case anyone missed my original post)
> purchase a board with the following specs:
> 
> -FPGA device with at least 15,000 usable gates (more would be
> preferable).  I only need a small number of user IOs, so that
> shouldn't be an issue at all.
> -clock to run the FPGA with only around 4 MHz frequency range...
> higher isn't a problem however.
> -in-circuit reprogrammable non-volatile memory device for storing the
> FPGA's configuration data, if the FPGA doesn't have one built-in.
> -The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less
> volume (this is important).
> 
> I'm planning on just soldering wires directly to the board, so no
> specific connectors are necessary.  And I don't mind if the specs
> aren't exactly what I need, just so long as they are relatively easy
> to alter to my specifications.  Thanks a lot for any help.

It sounds as if your best aproach would be to find a sufficiently
documented evaluation board that fits your needs , maybe
http://www.parallax.com/detail.asp?product_id=60004
(the schematics are downloadable from there) and re-design the PCB
to fit your space requirements as you suggested. I'd recommend
checking available souces for the parts before deciding on which
board to clone, some of the evaluation-board may use components
difficult to obtain for a hobbyist.

That should save you a lot of headaches compared to doing everything
from scratch.

Good Luck !

Chris

Article: 73211
Subject: Re: Xilinx DCMs
From: hmurray@suespammers.org (Hal Murray)
Date: Wed, 15 Sep 2004 20:51:16 -0500
Links: << >>  << T >>  << A >>
>I need accurate frequency, I'm using a 2 ppm osc as source and need to
>maintain that.

That's an interesting spec.  What sort of crystal/box are you using
to get that level of stability?  How expensive?

That got me thinking...  Many applications that need good accuracy
also need low jitter.  DLL type designs have lots of jitter.  (For
some value of "lots".)

Is it interesting to use something like a DLL in an unlocked mode?
That is, run a calibration phase then lock it at the best tap.

The idea is to kill the tap-changing jitter in trade for timing
wander as temperature or Vcc changes while still getting most
of the timing fixup from the DLL calibration step.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 73212
Subject: Programming Altera Config Device
From: "Gary Pace" <xxx@yyy.com>
Date: Thu, 16 Sep 2004 02:07:53 GMT
Links: << >>  << T >>  << A >>
We have a number of PCB's with Altera Cyclone/Config device systems.

In R&D we use Quartus to program this.

For production, we have a bed of nails based ATE system, using LabView.

We want to program the config. device automatically.

Has anyone done this ?

Does Altera produce a .dll or .ocx version of the programming tools ?
Can the programmer be run as a WIN32 console app. (ie from the command line) 
?
Does National Instruments (or a third party) have anything ?

Any advice much appreciated,

Gary 



Article: 73213
Subject: Re: adder VS increment
From: "Peter C. Wallace" <pcw@freeby.mesanet.com>
Date: Wed, 15 Sep 2004 19:09:45 -0700
Links: << >>  << T >>  << A >>
On Wed, 15 Sep 2004 14:17:18 -0700, Jimmy zhang wrote:

> Hi, All,
>   A 32 bit adder takes two 32 bit inputs. The propogation delay
> can be significant. if one of those two 32 bit inputs is a constant 1,
> can the add logic be optimized so that the delay for increment (+1) is
> reduced?
>  The ohter question is that for 32 bit add, can I achieve 100Mhz
> on the latest FPGAs?
> 
> Thanks,
> Jimmy
 
Well if you are only going to add '1'  you only need a counter, not an
adder, but I suspect with the fast carry chains in newer FPGA's,
adders may be faster than counters 

(Assuming you need a synchronous counter - 
ripple counters can be much faster) 

One of the frequency counter experts here can probably tell you how to
make a fast synchronous counter. 

A 100 MHz adder should be really easy (a 48 bit DDS I've done runs at 
110 MHz in a SpartanII and thats 2 (and 1/2?) generations old)

Peter Wallace

Article: 73214
Subject: Re: Programming Altera Config Device
From: "Subroto Datta" <sdatta@altera.com>
Date: Thu, 16 Sep 2004 02:24:03 GMT
Links: << >>  << T >>  << A >>

"Gary Pace" <xxx@yyy.com> wrote in message 
news:Zz62d.1762$Gz.1605@fe2.texas.rr.com...
> We have a number of PCB's with Altera Cyclone/Config device systems.
> Can the programmer be run as a WIN32 console app. (ie from the command 
> line) ?
> Does National Instruments (or a third party) have anything ?
>
> Any advice much appreciated,
>
> Gary
>
Hi Gary,

The Quartus Programmer is a command line application. Here is the output 
when when you type quartus_pgm --help in a DOS box.

D:\>quartus_pgm --help
Quartus II Programmer
Version 4.1 Build 181 06/29/2004 SJ Full Version
Copyright (C) 1991-2004 Altera Corporation

Usage:
------

quartus_pgm [-h | --help[=<option|topic>] | -v]
quartus_pgm -c <cable name> filname.cdf  --- If you want to use cdf file
quartus_pgm -c <cable name> -m <programming mode> -o <value> [-o 
<value>...] --- If you want to use individual programming file(s)
quartus_pgm -l --- to display the list of available hardware
quartus_pgm -c <cable name> -a --- to display the list of devices connected 
to the cable

Description:
------------

The Quartus(R) II Programmer programs Altera(R) devices.
The Programmer uses one of the valid supported file formats:
Programmer Object Files (.pof), SRAM Object Files (.sof),
Jam File (.jam), or Jam Byte-Code File (.jbc).

Make sure you specify a valid programming mode,
programming cable, and operation for a given device.

Options:
--------

        -f <argument file>
        -m <programming mode> | --mode=<programming mode>
        -c <cable name> | --cable=<cable name>
        -o <programming options> | --operation=<programming options>
        -l | --list
        -a | --auto
        --lower_priority

Help Topics:
------------

        arguments
        makefiles

For more information on specific options, use --help=<option|topic>.

Hope this helps,
Subroto Datta
Altera Corp. 



Article: 73215
Subject: Re: Xilinx DCMs
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 16 Sep 2004 14:29:46 +1200
Links: << >>  << T >>  << A >>
Hal Murray wrote:
>>I need accurate frequency, I'm using a 2 ppm osc as source and need to
>>maintain that.
> 
> 
> That's an interesting spec.  What sort of crystal/box are you using
> to get that level of stability?  How expensive?
> 
> That got me thinking...  Many applications that need good accuracy
> also need low jitter.  DLL type designs have lots of jitter.  (For
> some value of "lots".)
> 
> Is it interesting to use something like a DLL in an unlocked mode?
> That is, run a calibration phase then lock it at the best tap.
> 
> The idea is to kill the tap-changing jitter in trade for timing
> wander as temperature or Vcc changes while still getting most
> of the timing fixup from the DLL calibration step.

  Why stop there :)
You could check the error, and run some local heating on the
die (gated ring oscillators?), to correct the wander. Get a TXCO inside 
the FPGA...
  ( or some apps may allow a calibrate/send phase alternate )

-jg


Article: 73216
Subject: Handel C writing to flash ram & sampling hey guys clock setting
From: "Ben_Koh" <email_benjamin@yahoo.com>
Date: Wed, 15 Sep 2004 22:46:48 -0400
Links: << >>  << T >>  << A >>
hey guys,

Problem 1:
i wrote the following code to write 10 'D' to the flash ram after which i
read from the flash ram location 200000 using the FTU. But i got DDDDD  D
 instead. Can someone please tell me what went wrong. Is there anyway in
which i can phyically see what was written to my ram other than
transfering it to the flash ram and reading it using FTU?   

Code:
#define RC100_CLOCK_DIVIDE 20
#define RC100_BOARD
// Include libraries and headers
#include <stdlib.h>
#include <RC100.h>

void main()
{
RC100FlashEnable();

RC100FlashBlockErase(10);
RC100FlashWriteByte( 0x00200000, (unsigned 8)0x44);//ascii D
RC100FlashWriteByte( 0x00200001, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200002, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200003, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200004, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200005, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200006, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200007, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200008, (unsigned 8)0x44);
RC100FlashWriteByte( 0x00200009, (unsigned 8)0x44);

RC100FlashSetReadMode();
}


Problem 2:
i'm actually trying to communicate with the USB D+
and D- signal using the expansion slot pins on the RC100. The speed is
about 1.5Megabits/s. So i will need to read from the pins at 3MHz. Is
there anyway in which i can set the #define RC100_CLOCK_DIVIDE to 3MHz or
any sampling function that i can use for setting. if i were to used higher
clock rate the using the #define RC100_CLOCK_DIVIDE , i will get much more
data as a logic 1 or 0 will be read several times rather than 1 time only.


Also, can you also please advise on time/length for each output bit that i
output with the below function.


I'm using the following function:
interface bus_ts_clock_in (unsigned int 1 read )
Dplus(unsigned int 1 writePort=z,
unsigned 1 enable=condition)
with {data = {"AA15"} };

Thanks a lot in advance. Really appreciate it if you guys can give me some
advice. Thanks once again.







Article: 73217
Subject: Synthesis problems with while and non-constant terminal point.
From: Andre Bonin <Yoyoma_2@[at-]Hotmail.com>
Date: Thu, 16 Sep 2004 02:58:09 GMT
Links: << >>  << T >>  << A >>
Hello all,
I have an algorithm i would like to implement in an fpga.  I have no 
idea of knowing how many times the 'while' loop should run.

But doing something like this seems to be illegal in verilog.  Any ideas 
of how i can get around this?  How could i implement a c-style loop in 
verilog?

I tried to make a simple example of this.  I'me using Quartus2 Web 
edition for the synthesis.

	integer V;
	integer X;
	
	always @(V)
	begin
		V = 1;

		while( V )
		begin
			V = V + 1;
			X = X + V;

			if( X < 30 )
			begin
				V = 0;
			end
		end
	end


Thanks!

Article: 73218
Subject: Re: Virtex 4 released today
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 15 Sep 2004 20:58:32 -0700
Links: << >>  << T >>  << A >>
"Eric Crabill" <eric.crabill@xilinx.com> wrote in message
news:41488CC8.FD9C8E74@xilinx.com...
>
> Hi,
>
> > It really interest me how is the Xilinx Real PCI exprress
> > working - there is nothing mentioned about the need of
> > external PLL but without it can not work??
>
> Your assertion is false.  There is nothing in the PCI
> Express specification that requires you use a distributed
> reference clock.  It's present in some form factors, but
> not all.  When it's present, you might view it as a
> "convenience".
>
> You can use a distributed reference clock with a PLL if
> you want.  But you'll have to convert from 100 MHz to 125 MHz
> and "clean it up" so that it meets the frequency and +/- 100 ppm
> requirements of the Virtex-II Pro transceiver blocks.

YOU CAN NOT! (not at least to 100% compliance!)

Read the PCIe spec and check MGT datasheet!

Do your work! (its your work, not your homework!)
ok, relax, maybe that is not exactly your work :)

> You can also use a local 125 MHz oscillator that is +/- 100 ppm.

Eric, I do not think my assumptions are false (they very seldomly are)

PCIe spec says that clock must be +-300ppm, i.e. in the worst the case the
non-Virtex end of the PCIe has the maximum allowed per PCIe spec clock
error.

As the lock range of V2Pro(x) MGT's (and I assume also for V4)  is +-100ppm
then using an non locked to PCIe reference clock local oscillator for MGT
reference will not be working solution as the MGT will never get initial
lock. It might but is not guaranteed, as the clock error may be outside the
MGT lock range.

As much as I know DCM's (in V2Pro at least) are no suitable for MGT reflock,
so the ***only*** that would ever allow the V2Pro MGT to be used for PCIe is
the use of external PLL that is locked to PCIe ref and does 100>125MHz
(there are special chips for this purpose from ICS)

No other method  (like using external 125Mhz oscillator) would not yield to
PCIe compliant solution.

Correct me if I am wrong!

(maybe the V4 has DCM things that suitable for MGT reflclock, that is what I
do not know but would like to know)

Antti
PS good to see some Xilinx person has courage to reply to the MGT PCIe
issue, my previous posting did not get any replies at all :(



Article: 73219
Subject: Re: Virtex 4 released today
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 15 Sep 2004 21:01:50 -0700
Links: << >>  << T >>  << A >>

"Antti Lukats" <antti@case2000.com> wrote in message
news:cia35m$5jg$04$1@news.t-online.com...
> "Eric Crabill" <eric.crabill@xilinx.com> wrote in message
> news:41488CC8.FD9C8E74@xilinx.com...

Sorry my previous post had one quote in wrong place, fixed here


> > Hi,
> >
> > > It really interest me how is the Xilinx Real PCI exprress
> > > working - there is nothing mentioned about the need of
> > > external PLL but without it can not work??
> >
> > Your assertion is false.  There is nothing in the PCI
> > Express specification that requires you use a distributed
> > reference clock.  It's present in some form factors, but
> > not all.  When it's present, you might view it as a
> > "convenience".
> >
> > You can use a distributed reference clock with a PLL if
> > you want.  But you'll have to convert from 100 MHz to 125 MHz
> > and "clean it up" so that it meets the frequency and +/- 100 ppm
> > requirements of the Virtex-II Pro transceiver blocks.
>
> YOU CAN NOT! (not at least to 100% compliance!)

[SORRY]
the above section was supposed to be later!!
my typo!!

YOU *MUST* use external PLL is correct


> Read the PCIe spec and check MGT datasheet!
>
> Do your work! (its your work, not your homework!)
> ok, relax, maybe that is not exactly your work :)
>
> > You can also use a local 125 MHz oscillator that is +/- 100 ppm.

the ***CAN NOT SHOULD BE HERE***


> Eric, I do not think my assumptions are false (they very seldomly are)
>
> PCIe spec says that clock must be +-300ppm, i.e. in the worst the case the
> non-Virtex end of the PCIe has the maximum allowed per PCIe spec clock
> error.
>
> As the lock range of V2Pro(x) MGT's (and I assume also for V4)  is
+-100ppm
> then using an non locked to PCIe reference clock local oscillator for MGT
> reference will not be working solution as the MGT will never get initial
> lock. It might but is not guaranteed, as the clock error may be outside
the
> MGT lock range.
>
> As much as I know DCM's (in V2Pro at least) are no suitable for MGT
reflock,
> so the ***only*** that would ever allow the V2Pro MGT to be used for PCIe
is
> the use of external PLL that is locked to PCIe ref and does 100>125MHz
> (there are special chips for this purpose from ICS)
>
> No other method  (like using external 125Mhz oscillator) would not yield
to
> PCIe compliant solution.
>
> Correct me if I am wrong!
>
> (maybe the V4 has DCM things that suitable for MGT reflclock, that is what
I
> do not know but would like to know)
>
> Antti
> PS good to see some Xilinx person has courage to reply to the MGT PCIe
> issue, my previous posting did not get any replies at all :(
>
>



Article: 73220
Subject: Re: Looking for a Design for a Small FPGA Board
From: "Tony Burch" <tony@burched.com.au>
Date: Thu, 16 Sep 2004 14:44:54 +1000
Links: << >>  << T >>  << A >>
Hi Darien,

Here is a new board that may meet your needs
http://www.trenz-electronic.de/prod/proden19.htm

It's dimension is 50.7 x 43.6mm, however if you
took off the USB connector, and then used a dremel
tool, or a small mill, to route off the top egde and
the left edge (no, I'm serious:) ), then I think you
may be able to bring it down to your needed size.

You could then solder your wires to the bottom
edge connector.

Best regards,

Tony Burch
B  U  R  C  H  E  D
Simple FPGA Boards, The Most Free I/O, Easy Prototyping
http://www.burched.biz


"Daragoth" <daragoth@kuririnmail.com> wrote in message
news:317379a8.0409151507.68edc201@posting.google.com...
> Hi, I'm a hobbyist, and about a month and a half ago I made a post to
> this newsgroup looking for a compact FPGA board that I could purchase
> online in small quantities for a project I was doing.  It seemed that
> no one knew of a board with the specs I needed (and the closest ones I
> was able to find were the ones at www.fpgas4fun.com, but they were
> slighty too large for what I needed), so I decided to try and design
> one myself with PCB design software (EAGLE 4.13).  But I have very
> little experience in PCB design and am pretty overwhelmed with created
> a design from scratch.  So I was wondering if there was a place I
> could download the design or (in case anyone missed my original post)
> purchase a board with the following specs:
>
> -FPGA device with at least 15,000 usable gates (more would be
> preferable).  I only need a small number of user IOs, so that
> shouldn't be an issue at all.
> -clock to run the FPGA with only around 4 MHz frequency range...
> higher isn't a problem however.
> -in-circuit reprogrammable non-volatile memory device for storing the
> FPGA's configuration data, if the FPGA doesn't have one built-in.
> -The board's must be able to fit with a 40 mm x 30 mm x 10 mm or less
> volume (this is important).
>
> I'm planning on just soldering wires directly to the board, so no
> specific connectors are necessary.  And I don't mind if the specs
> aren't exactly what I need, just so long as they are relatively easy
> to alter to my specifications.  Thanks a lot for any help.
>
>
> -Darien



Article: 73221
Subject: VHDL Design for running sorter
From: vizziee@yahoo.com (Kumar Vijay Mishra)
Date: 15 Sep 2004 23:05:20 -0700
Links: << >>  << T >>  << A >>
Hi.

I am working on inmplementation of order statistics CFAR, where
sorting of a continuous stream of data is required.

Exactly problem is as under:
I am getting a continuous stream of 16-bit data. In every clock cyle I
have to sort 32-size array. When I have sorted the array in ascending
order, I want to choose 24th number only. In the next clock cycle, I
get a new no added to my array while the first number gets out of the
array. The new array that I get is to be sorted again and he 24th
position number is to be taken out.
So, in every clock cycle, I get a new data (in an array of 32 16-bit
numbers) (with the oldest data getting deleted from this array) and in
the same clock cycle, I need to have the 24th-position data available
to me for further processing.

Can anybody help me in this? Plus if someone can direct me to any
useful link on VHDL designs of sorting, since I am new to FPGA and
VHDL.

Thanx in advance.

Article: 73222
Subject: Re: Xilinx Core Gen Question
From: Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com>
Date: Thu, 16 Sep 2004 08:47:32 +0200
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> "Laurent Gauch" <laurent.gauch@DELETEALLCAPSamontec.com> wrote in message
> news:414838f8$1@news.vsnet.ch...
> 
>>Hi all,
>>
>>Can I insert my own IP core in the Xilinx Core Gen?
>>Can I use Xilinx Core Gen to manage my OWN VHDL IP core?
>>If not, why Xilinx does not allow that feature.
>>
>>Larry,
>>www.amontec.com
> 
> 
> yes you can.
> 
> well there are some problems and I guess not all the core gen funtions are
> accesible to regular non privileged users, but you can create your own
> coregen cores
> 
> Antti
> 
> 

Hi Antti,

... and how to do that ?
I am searching in xilinx doc, but found nothing usable.

Regards,
Laurent
www.amontec.com

Article: 73223
Subject: Re: Virtex 4 released today
From: news@sulimma.de (Kolja Sulimma)
Date: 16 Sep 2004 01:00:55 -0700
Links: << >>  << T >>  << A >>
General Schvantzkoph <schvantzkoph@yahoo.com> wrote in message news:<pan.2004.09.15.00.25.27.975530@yahoo.com>...
> There are lots of situations where you need multiple clocks. If you
> are interfacing to a number of devices that each have their own clock you
> need a separate clock for each of them. Even if the devices are all using
> the same source clock their output clocks (for clock forwarded interfaces)
> are all phase shifted by an indeterminate amount so they have to be
> treated as asynchronous. 

I thought that is exactly what the new I/O phase shift feature is about....

Kolja Sulimma

Article: 73224
Subject: Quartus In-system Memory bug
From: "io" <tartampion@nullepart.com>
Date: Thu, 16 Sep 2004 10:10:45 +0200
Links: << >>  << T >>  << A >>
I try to use Quartus In-system Memory Editor but it doesn't work.

I have implement a RAM and I can read data from it.
But the problem is that I can't modify data  like I want.
If I change a word, my data is corrupt and if I update all the memory, all 
my RAM began corrupted.

Did someone have ever make work that tools ?
For me it's seems to be at prototype state. 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search