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It is a Pb-free version of XC2S100-xFG256 and it has the same arichtecture, speed file and bitstream, so you just think it as XC2S100-xFG256 in ISE environment. Just like the case that you cannot find different temperature range such as I-grade with devices in ISE. "Marlboro" <ccon67@netscape.net> ???? news:e3fd5378.0410071258.46868825@posting.google.com... > Hi all, > Xilinx claimed all their currents device are available in lead free > packages, but that not true... at least that's what I firgure out > today. Does this device ever exist XC2S100-FGG256 (speed doesn't > matter)? Seems I can't find any distributor has it, or just because > this device is OBSOLETE? If so we probably shut down our business... > > Any advice is appreciate,Article: 74376
In Virtex-derived architectures, you can implement o = add ? (a + b) : c; or o = sel ? (a + b) : (a + c); or even o = addsub ? (addand ? a+b : a-b) : (addand ? a&b : a^b); in one LUT per bit. The trick is to use a MULT_AND to kill the carry propagation when add=0. See http://www.fpgacpu.org/log/nov00.html#001112. But as Philip points out, you'd need five input signals to do o = sel ? (add ? a + b : a - b) : c; and I don't think that can be done in one LUT per bit. Jan GrayArticle: 74377
What's the easiest way to partition one 128 MB dram into
two 64 MB sections with each section control by one of the
ppc in the VP20?
Another way to ask this question:
Is it possible to use the same plb_ddr_sdram core or more
plb_ddr_sdram core to control the same pysical DRAM interface
while partition the DDR to share by both ppc?
Also if I like to have some special fpga logic to
* offload some special ppc packet processing functions
* the functions require access the DDR used and update by the
ppc CPU at the same time.
what's the best way to do this?
-Tony
Article: 74378"Jan Gray" <jsgray@acm.org> schrieb im Newsbeitrag news:CXJ9d.11048$Vm1.2497@newsread3.news.atl.earthlink.net... > In Virtex-derived architectures, you can implement > o = add ? (a + b) : c; > or > o = sel ? (a + b) : (a + c); > or even > o = addsub ? (addand ? a+b : a-b) : (addand ? a&b : a^b); > in one LUT per bit. > > The trick is to use a MULT_AND to kill the carry propagation when > add=0. > See http://www.fpgacpu.org/log/nov00.html#001112. > > But as Philip points out, you'd need five input signals to do > o = sel ? (add ? a + b : a - b) : c; > and I don't think that can be done in one LUT per bit. > The original request needs even six inputs. In your notation I want to achieve following function: d = ena ? (sload ? c : (addnsub ? a+b : a-b)) : d However, the Cyclone LC has LAB wide signals for addnsub, sload and ena. You only need three of the LUT inputs for a,b and c which are available in arithmetic mode. For the Spartan LC I can see only the CE signal as additional 'global' input that can serve as ena. There are two inputs (FIXINA/B) for the register load, but it seems to me that GYMUX is statically configured. So it can't be used for the sload part. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74379
Try adding the file to the Modelsim project by compiling it first into your work library. "Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message news:JTc*E4Awq@news.chiark.greenend.org.uk... > I'm trying to simulate some Verilog to run on my XPort card. The card > plugs into a Gameboy, so any configuration of its FPGA has to include > a couple of provided blocks for interfacing to the Gameboy's bus. > > So the program begins `include "primary.v" > > When I try compiling this in modelsim, it says it can't find primary.v, > even if I figure out where in my directory heirarchy primary.v is hiding > and add it to the modelsim project. > > So, how do I set what in C I'd call the include directory? The manual > suggests I should use the compile -> compile options... menu option, > but that's greyed out. > > Sorry to ask such a dumb question, > > Tom >Article: 74380
Has anyone ever had issues with the RapidIO verilog functional simulation off the Xilinx site? Even though I have my simprim library compiled in my project, the simulator can't find any of the "X_INV" or whatever when I simulate the phy_8_lvds model.Article: 74381
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10mdncb3u5g8ve7@corp.supernews.com... > Where is the demo software for this wonderful Spartan 3 kit? > > I was most surprised when I plugged in a VGA monitor and saw > all the switches, buttons, and jumper dispalyed in multicolors. > > Does the keyboard input do something as well? http://www.xilinx.com/products/spartan3/s3boards.htmArticle: 74382
anyone have problems instantiating the verilog simprims (x_inv or x_lut2, etc) in the phy_8_lvds before? Even though I have the simprim library compiled in my Modelsim libraries, when I simulate it complains that he can't find the crummy simprims. Thanks.Article: 74383
Thank you!!!!!!!!!!!!!!!!!!
"pborut" <borut.preloznik@siol.net> wrote in message news:<e7a2bb9aec8474c8ce0443d5ed6787cb@localhost.talkaboutelectronicequipment.com>...
> Hi Mike,
> I was looking for same thing and found 30-day evaluation on:
> http://www.embeddedtechnology.com/content/Downloads/SoftwareDesc.asp?DocID={1e91e7bc-edee-11d2-94bd-00a0c9b3bdf2}&VNETCOOKIE=NO
> I had to register first.
> Good luck,
> Borut.
Article: 74384You may have a library naming problem: simprim versus simprims. Check out what Xilinx created, and check out what you are calling out. (It may not be your issue, but it was mine. The VHDL library was simprim, while the verilog library was simprims.) Jason "yyy" <yyy@usjet.net> wrote in message news:Pe1ad.818$f02.76685@news.uswest.net... > anyone have problems instantiating the verilog simprims (x_inv or x_lut2, > etc) in the phy_8_lvds before? Even though I have the simprim library > compiled in my Modelsim libraries, when I simulate it complains that he > can't find the crummy simprims. Thanks. > >Article: 74385
Has anyone used the DCT core available in Xilinx ISE 6.1's coregen? I am currently getting the following error message in the translate stage: ERROR:NgdBuild:604 - logical block 'u2' with type 'DA_2D_DCT' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'DA_2D_DCT' is not supported in target 'spartan2'. I get a similar error message reguardless of the device I select. I instantiate as directed in the .vho file. Does anyone know what I am doing wrong? Brandon SternerArticle: 74386
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<ck1rpt$ubf$1@bunyip.cc.uq.edu.au>... > Hi Austin, > Austin Lesea wrote: > > I refer to this as a 'tap dance.' (please forgive my humor, but it is > > part of my personality....) Austin, Keep it up, I for one enjoy the pun-ishment. > I'm picturing a self-reconfiguring microblaze uClinux system dynamically > scaling its own clock... John, I'd suggest a numerically controlled oscilator (NCO) / scaling accumulator / DDFS (see http://www.xilinx.com/xcell/xl31/xl31_32.pdf). In the latest parts, you can clock a 10 bit accumulator at >500 MHz, allowing your microblaze to run up to 250MHz (do they go that fast? I'll be using one soon). You would get more resolutions than the 5-bits M, 5-bits D of the CLKFX. If you are scaling the clock for power conservation, you probably would not need more than 6 bits. Also, no worries about the period dropping below the minimum that the microblaze configuration was routed for. And far easier to program than partial re-config. Regards, JohnArticle: 74387
Hi, I just found and tried to evaluate the xmil007 memory-intercae compiler for the Spartan-3 and the recent Virtex devices ... It seems to work quiet nice for the ballgrid devices fg320 and above but for the very common vc3s400pq208 and other none ballgrid-devices there are always errors like this one : ------------------------------------------------------------------ %Reserve Vrp & Vrn pins: Checked %Reserved pins: Selected Design option: Full controler %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Unable to find the necessary attributes for all pins. Requested data pins: 64. Found locations: 0. Could not find the pins for all the data and dqs . Time:Sun October 10 14:32:52 2004 ************************************************************************* -------------------------------------------------------------------- Is there anyone out here who has been able to use this approach to generate a ddr-1 memory interface for a Spartan-3 in a PQFP package ? Reagrds, ThorstenArticle: 74388
Hi! I'm completely new to FPGAs and now I want to buy an eva-board to learn about them. What is the right device to start with? How many cells are suggestive? Perhaps you can give some application examples and the cells needed? What do you think about this one? http://www.trenz-electronic.de/prod/proden7.htm Or perhaps better Alteras Cyclone series? Thanks for any comments! AndreasArticle: 74389
<brandon@detachedsolutions.com> wrote in message news:<10mhh7hoj5odpbb@news.supernews.com>... > Has anyone used the DCT core available in Xilinx ISE 6.1's coregen? I am > currently getting the following error message in the translate stage: > > ERROR:NgdBuild:604 - logical block 'u2' with type 'DA_2D_DCT' could not be > resolved. A pin name misspelling can cause this, a missing edif or ngc > file, > or the misspelling of a type name. Symbol 'DA_2D_DCT' is not supported in > target 'spartan2'. > > I get a similar error message reguardless of the device I select. I > instantiate as directed in the .vho file. Does anyone know what I am doing > wrong? > > Brandon Sterner Brandon, You're probably doing nothing wrong. There is an old bug in the ISE S/W, dating back to 1-D DCT apparently. Check through the answer database on the Xilinx site, and find Record Number: 17816, which will tell you "To resolve this issue, disable the "Read Cores" option within the synthesis properties. For XST, select Synthesis options -> Read Cores to disable this option." HTH, JohnArticle: 74390
SD wrote: > Hi all, > I am trying to implement a DSP algorithm in a FPGA. My algorithm has > sine and cosine functions in it. Can somebody comment on implementing > sine and cosine functions in VHDL or MATLAB fixed point (using fixed > point toolbox). > Thanks, > SD CORDIC algorithm (see http://www.dspguru.com/info/faqs/cordic2.htm , Section 4.4 ) Another option could be a look-up table. Impossible to say which is better for your case, depends on the application. J.S.Article: 74391
Thanks Alex, I was looking for the font and I think I found it under opb_color_video_ctrl_v1_00_a/ hdl/ vhdl/ opb_color_video_ctrl_v1_00_a/ char_gen_rom. The comments state what bits are what but not what character order the bits are in. Boy, there is a lot of files here. Has anybody deciphered and written about this?Article: 74392
Help! I have a state machine on my top level for an SRAM controller. The states are sram_state_read, sram_state_write, sram_state_idle, and sram_state_reset. Presently the design is flat with no components. I want to put the SRAM paths in a component by itself. Since the SRAM state machine may influence other parts of the design, I want to have a separate component for it, or leave it in the top level. Now it seems to me that one should be able to pass these states down to to the SRAM paths' component using the type that I decleare on the top level. However I have been unable to find the syntax for doing this. I suppose I could "hard code" the states into known patterns of 1s and 0s and pass the the info into the component using std_logic_vector but this seems counter to high level language philosophy. Can anybody help? Thanks, Brad Smallridge b r a d @ a i v i s i o n. c o mArticle: 74393
The Spartan 3 Dev Kit is very good and I seem to be able to get all the answers that I need (and I generate a lot of questions) from this FPGA user group, the reps at Memec Insight, the engineers at Xilinx (yes, they actually pick up the phone) and the volumous application notes on the Xilinx web site.Article: 74394
I have donloaded all the files. Since I didn't find an .NPL file I created a new project and added the VHDL source files to it. When I went to synthesize it, however, I got an error saying it couldn't find this library file, which I gather has something to do with MicroBlaze. library Common_v1_00_a; use Common_v1_00_a.pselect; architecture IMP of opb_color_video_ctrl is So can I get this file or can I synthesize something without it? b r a d @ a i v i s i o n . c o mArticle: 74395
Hello friends,
i am using MXE, i got the post-translate simulation model (which gives
us the filename_translate.vhd file) and i am not getting the
post-translate simulation results.
error messages are:
1) Unknown identifier: init.
this message is related to the flip-flops the NGDbuild has
generated. if i remove the generic map from this component ... then
also i am not getting the final output results.
c_1_0 : X_FF
generic map(
INIT => '0'
)
port map (
I => Q_n0000,
RST => c_1_GSR_OR,
CLK => clk_bm_BUFGP,
O => c_1,
CE => VCC,
SET => GND
);
2) Unknown identifier: x_roc
# ERROR: bm_translate.vhd(267): Unknown component name
Unknown identifier: x_toc
# ERROR: bm_translate.vhd(269): Unknown component name
this error message is related to the netlist given below, this
netlist is always generated for all the design. I have seen the
SIMPRIM library.
SIMPRIM library have these components X_ROC, X_TOC.
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
please help me to debug this problem ...
Thanks
Article: 74396Thanks this helped a lot. At first I had trouble finding the "read cores" option. It turns out I had to select advanced mode by going to edit->preferences->processes and change property display level from standard to advanced. Thanks again, this saved me from having to write my own. Brandon "John" <john.l.smith@titan.com> wrote in message news:5b9931fd.0410100858.430f0ba3@posting.google.com... > <brandon@detachedsolutions.com> wrote in message news:<10mhh7hoj5odpbb@news.supernews.com>... > > Has anyone used the DCT core available in Xilinx ISE 6.1's coregen? I am > > currently getting the following error message in the translate stage: > > > > ERROR:NgdBuild:604 - logical block 'u2' with type 'DA_2D_DCT' could not be > > resolved. A pin name misspelling can cause this, a missing edif or ngc > > file, > > or the misspelling of a type name. Symbol 'DA_2D_DCT' is not supported in > > target 'spartan2'. > > > > I get a similar error message reguardless of the device I select. I > > instantiate as directed in the .vho file. Does anyone know what I am doing > > wrong? > > > > Brandon Sterner > > Brandon, > You're probably doing nothing wrong. There is an old bug in the ISE > S/W, dating back to 1-D DCT apparently. Check through the answer > database on the Xilinx site, and find Record Number: 17816, which will > tell you "To resolve this issue, disable the "Read Cores" option > within the synthesis properties. For XST, select Synthesis options -> > Read Cores to disable this option." > HTH, > JohnArticle: 74397
I was curious if there is much difference in leakage current or other heat-effecting conditions between FPGA logic blocks that are programmed and those that are idle. Presumably, logic that is switching is generating heat. However, is there an optimal programming state for inactive gates in order to reduce heat? In particular, if I have 8 ARINC-429 channels in my FPGA, but the current configuration of the system only uses 2 of them, would it be beneficial (from a heat point of view) to have a different bitstream that only has 2 ARINC-429 channels? -bhArticle: 74398
I need to accomplish the following using the Spartan-3 Starter Kit. This is a small part of my overall project and I don't have time to do it. Inputs- 5V differential quadrature (A+ A- B+ B-) signal Enable (active high) Counter Reset (active high) Output- Trigger Pulse (active low) Specifics- I need a trigger pulse that is n clocks wide (n should be changeable in code- pulse length will need to range between 10us and 500us) whenever the quadrature counter (24 bit) increments/decrements by x counts (x should be changeable in code and will range from around 15 to 200). Quadrature input max speed is 7.8mhz. The trigger pulse should only be output when the enable signal is active (the counter can run all the time). I am not asking for free help, I just need a complete solution and I will pay for it ;) Thanks, GaryArticle: 74399
Hi, I am trying to place and route my design to a specific portion of the FPGA by using the Xilinx modular design flow, coupled with AREA_GROUP constraints. But the par for a module gives the following error message for some (not all) region constraints. FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute route area extrema. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is: INST "u1" AREA_GROUP=g1; AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y3; AREA_GROUP g1 MODE=RECONFIG; AREA_GROUP g1 PLACE=CLOSED; Could not find any help in the answers database at Xilinx. Can someone please help me? Thanks in anticipation. Aman
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